library verilog;
use verilog.vl_types.all;
entity ampel is
    generic(
        FUSS_AUS        : vl_logic_vector(0 to 1) := (Hi0, Hi0);
        FUSS_ROT        : vl_logic_vector(0 to 1) := (Hi1, Hi0);
        FUSS_GRUEN      : vl_logic_vector(0 to 1) := (Hi0, Hi1);
        AUTO_AUS        : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi0);
        AUTO_ROT        : vl_logic_vector(0 to 2) := (Hi1, Hi0, Hi0);
        AUTO_GELB       : vl_logic_vector(0 to 2) := (Hi0, Hi1, Hi0);
        AUTO_GRUEN      : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi1)
    );
    port(
        CLOCK_50        : in     vl_logic;
        KEY             : in     vl_logic_vector(1 downto 0);
        LEDH_L          : out    vl_logic_vector(2 downto 0);
        LEDH_R          : out    vl_logic_vector(2 downto 0);
        LEDN_L          : out    vl_logic_vector(2 downto 0);
        LEDN_R          : out    vl_logic_vector(2 downto 0);
        LEDF_L          : out    vl_logic_vector(1 downto 0);
        LEDF_R          : out    vl_logic_vector(1 downto 0)
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of FUSS_AUS : constant is 1;
    attribute mti_svvh_generic_type of FUSS_ROT : constant is 1;
    attribute mti_svvh_generic_type of FUSS_GRUEN : constant is 1;
    attribute mti_svvh_generic_type of AUTO_AUS : constant is 1;
    attribute mti_svvh_generic_type of AUTO_ROT : constant is 1;
    attribute mti_svvh_generic_type of AUTO_GELB : constant is 1;
    attribute mti_svvh_generic_type of AUTO_GRUEN : constant is 1;
end ampel;
