library verilog;
use verilog.vl_types.all;
entity mod_n_counter_10bit is
    generic(
        N               : integer := 10
    );
    port(
        CLK             : in     vl_logic;
        RST             : in     vl_logic;
        EN              : in     vl_logic;
        Q               : out    vl_logic_vector(9 downto 0);
        TC              : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of N : constant is 1;
end mod_n_counter_10bit;
