// counter testbench

`timescale 1ns/1ps

module tb_counter();

// DUT inputs
reg clk_tb;
reg rst_tb;
reg en_tb;

// DUT 1 outputs 
wire [9:0] q_tb_dut_1;
wire tc_tb_dut_1;

// DUT 2 outputs 
wire [9:0] q_tb_dut_2;
wire tc_tb_dut_2;

integer i = 0;

initial begin  
  clk_tb = 1'b0;
  rst_tb = 1'b0;
  en_tb  = 1'b0;
end

// Create 50 MHz clock
always begin
  #10;
  clk_tb = ~clk_tb;
end

initial begin
    
  // delay for four clk cycles
  for (i = 0; i < 4; i = i+1) begin
    @(negedge clk_tb);
  end
  
  // assert reset
  rst_tb <= 1'b1;
  @(negedge clk_tb);
  
  // de-assert reset
  rst_tb <= 1'b0;
  @(negedge clk_tb);
  
  // enable counter for 8 cycles
  en_tb = 1'b1;

  for (i = 0 ; i < 8 ; i = i+1 ) begin
    @(negedge clk_tb);
  end

  // disable counter
  en_tb = 1'b0;
  
  // wait some time
  @(negedge clk_tb);
  @(negedge clk_tb);
  // enable counter again
    en_tb = 1'b1;
end

// DUT 1 instance
mod_n_counter_10bit DUT_1(
  //module inputs
  .CLK(clk_tb),
  .RST(rst_tb),
  .EN(en_tb),
  //module outputs
  .Q(q_tb_dut_1),
  .TC(tc_tb_dut_1)
);

// DUT 2 instance
mod_n_counter_10bit #(.N(12)) DUT2(
  .CLK(clk_tb),
  .RST(rst_tb),
  .EN(en_tb),
  .Q(q_tb_dut_2),
  .TC(tc_tb_dut_2)
);

endmodule