library verilog;
use verilog.vl_types.all;
entity d_ff is
    port(
        D               : in     vl_logic;
        CLK             : in     vl_logic;
        RST             : in     vl_logic;
        ENA             : in     vl_logic;
        Q               : out    vl_logic;
        Qn              : out    vl_logic
    );
end d_ff;
