library verilog;
use verilog.vl_types.all;
entity jk_ff is
    port(
        R               : in     vl_logic;
        CLK             : in     vl_logic;
        EN              : in     vl_logic;
        J               : in     vl_logic;
        K               : in     vl_logic;
        Q               : out    vl_logic
    );
end jk_ff;
