/******************************************************
*                                                     
*  Description:  tb_ampel                                
*         Date:  13.01.2018                           
*    File Name:  tb_ampel.v                              
*      Version:  1.0                                  
*       Target:  Simulation             
*   Technology:                                       
*                                                     
* Rev   Author   Date          Changes                
* -----------------------------------------------------        
* 1.0   JZ       13.01.2018    Testbench zur Ampelsteuerung
*******************************************************/

`timescale 1ns / 1ps

module tb_ampel;

reg CLK;
reg RSTn;
reg SW;

wire [2:0] HAUPTSTR_LINKS;
wire [2:0] NEBENSTR_LINKS;
wire [1:0] FUSSGAENGER_LINKS;
wire [2:0] HAUPTSTR_RECHTS;
wire [2:0] NEBENSTR_RECHTS;
wire [1:0] FUSSGAENGER_RECHTS;

//50 MHz clock
initial
  begin
  CLK  = 1'b0;
  end

always
  CLK = #10 ~CLK;

//push buttons
initial
  begin
  RSTn = 1'b1;
  SW = 1'b1;
  #100;
  RSTn = 1'b0;
  #10;
  RSTn = 1'b1;
  #50_000;
  SW = 1'b0;
  #100;
  SW = 1'b1;
  end

ampel ampel(
.CLOCK_50 (CLK),
.KEY ({RSTn, SW}),
.LEDH_L(HAUPTSTR_LINKS),
.LEDN_L(NEBENSTR_LINKS),
.LEDF_L(FUSSGAENGER_LINKS),
.LEDH_R(HAUPTSTR_RECHTS),
.LEDN_R(NEBENSTR_RECHTS),
.LEDF_R(FUSSGAENGER_RECHTS)
);



endmodule
