// counter testbench

`timescale 1ns/1ps

module tb_counter();

// DUT inputs

// DUT 1 outputs 

// DUT 2 outputs 


integer i = 0;


// Create 50 MHz clock


initial begin  
  
  clk_tb = 1'b0;
  rst_tb = 1'b0;
  en_tb  = 1'b0;
    
  // delay for four clk cycles
  for (i = 0; i < 4; i = i+1) begin
    @(negedge clk_tb);
  end
  
  // assert reset
  rst_tb <= 1'b0;
  @(negedge clk_tb);
  
  // de-assert reset
  rst_tb <= 1'b1;
  @(negedge clk_tb);
  
  // enable counter for 8 cycles

  // disable counter
  
  // wait some time
  @(negedge clk_tb);
  @(negedge clk_tb);
  // enable counter again
    en_tb = 1'b1;
end

// DUT 1 instance

// DUT 2 instance


endmodule