module ring_sr(
  //inputs
  PATTERN,
  CLK,
  RSTn,
  ENA,
  //outputs
  Q);
  
  input [15:0] PATTERN;
  input CLK,RSTn,ENA;
  output reg [15:0] Q;
  
  always @(posedge CLK)
    if(~RSTn) Q <= PATTERN;
    
    else if (ENA) 
      begin
        Q[15:1] <= Q[14:0];
        Q[0] <= Q[15];
      end
      
endmodule // ring_sr 