module down_counter
(
    input [7:0] CLK_DIVIDER;
    input CLK,
    input RESETn,
    output wire SYNC
);

output reg [$clog2(CLK_DIVIDER)-1 : 0] Q,

always @(posedge CLK or negedge RESETn) begin
    if(~RESETn) begin
        Q <= 1'd0;
    end
    else begin
        if (Q > 1'd0) begin
            Q <= Q - 1'd1;
        end
        else if(Q == 1'd0) begin
            Q <= CLK_DIVIDER;
        end
    end
end

assign SYNC = (Q == 1'd0);
    
endmodule