`timescale 1ns/1ps

module spi_master_tb;
// top level testbench, no inputs or outputs

  reg RESETn_TB, RUN_TB, CLOCK_50_TB;
  reg [7:0] CLK_DIVIDER_TB, SLAVE_SELECT_TB;
  reg [1:0] DATA_LENGTH_TB, MODE_TB;
  reg [31:0] TX_TB;

//DUT module outputs
  wire [31:0] RX_TB;
  wire [7:0]  SSn_TB;
  wire SCLK_TB, MOSI_TB, BUSY_TB, MISO_TB;
  
//DUT test signals
  wire [2:0] STATE_TEST_TB;
  wire SYNC_TEST_TB, ENA_TEST_TB;
  
  assign MISO_TB = 1'b0;
  
  initial begin
    // Reset
    CLOCK_50_TB <= 1'b0;
    RESETn_TB <= 1'b1;
    
    TX_TB <= 32'h0;
    CLK_DIVIDER_TB <= 8'h0;
    SLAVE_SELECT_TB <= 8'h0;
    DATA_LENGTH_TB <= 2'b00;
    MODE_TB <= 2'b00;
    RUN_TB <= 1'b0;
    
    #20 RESETn_TB <= 1'b0;
    #80 RESETn_TB <= 1'b1;
    
    // spi_master setup: 8 Bit Daten, Mode 0
        
    TX_TB <= 32'h000000AA;
    CLK_DIVIDER_TB <= 8'h1;
    SLAVE_SELECT_TB <= 8'h1;
    DATA_LENGTH_TB <= 2'b00;
    MODE_TB <= 2'b00;
    
    #100 RUN_TB <= 1'b1;
    #100 RUN_TB <= 1'b0;

    #5000

    // spi_master setup: 16 Bit Daten, Mode 3    
    TX_TB <= 32'h000084A8;
    CLK_DIVIDER_TB <= 8'h4;
    SLAVE_SELECT_TB <= 8'h1;
    DATA_LENGTH_TB <= 2'b01;
    MODE_TB <= 2'b11;
    
    #100 RUN_TB <= 1'b1;
    #100 RUN_TB <= 1'b0;
    
    #7000
    
    // spi_master setup: 8 Bit Daten, Mode 2    
    TX_TB <= 32'h000084A8;
    CLK_DIVIDER_TB <= 8'h4;
    SLAVE_SELECT_TB <= 8'h2;
    DATA_LENGTH_TB <= 2'b00;
    MODE_TB <= 2'b10;
    
    #100 RUN_TB <= 1'b1;
    #100 RUN_TB <= 1'b0;
    
  end
  
  always begin
    #10 CLOCK_50_TB <= ~CLOCK_50_TB;
  end
  
  spi_master spi_master_test(
  .RESETn(RESETn_TB),
  .CLK(CLOCK_50_TB),
  .RUN(RUN_TB),
  .MODE(MODE_TB),
  .DATA_LENGTH(DATA_LENGTH_TB),
  .CLK_DIVIDER(CLK_DIVIDER_TB),
  .SLAVE_SELECT(SLAVE_SELECT_TB),
  .TX(TX_TB),
  .SCLK(SCLK_TB),
  .MISO(MISO_TB),
  .MOSI(MOSI_TB),
  .SSn(SSn_TB),
  .RX(RX_TB),
  .BUSY(BUSY_TB),
  .SYNC_TEST(SYNC_TEST_TB),
  .STATE_TEST(STATE_TEST_TB),
  .ENA_TEST(ENA_TEST_TB));  
endmodule