library verilog;
use verilog.vl_types.all;
entity down_counter is
    generic(
        CLOCK_DIVIDER   : integer := 5
    );
    port(
        CLK             : in     vl_logic;
        RESETn          : in     vl_logic;
        Q               : out    vl_logic_vector;
        SYNC            : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of CLOCK_DIVIDER : constant is 1;
end down_counter;
