library verilog;
use verilog.vl_types.all;
entity spi_master is
    port(
        RESETn          : in     vl_logic;
        CLK             : in     vl_logic;
        CLK_DIVIDER     : in     vl_logic_vector(7 downto 0);
        SLAVE_SELECT    : in     vl_logic_vector(7 downto 0);
        DATA_LENGTH     : in     vl_logic_vector(1 downto 0);
        MODE            : in     vl_logic_vector(1 downto 0);
        MISO            : in     vl_logic;
        TX              : in     vl_logic_vector(31 downto 0);
        RUN             : in     vl_logic;
        RX              : out    vl_logic_vector(31 downto 0);
        SCLK            : out    vl_logic;
        MOSI            : out    vl_logic;
        SSn             : out    vl_logic_vector(7 downto 0);
        BUSY            : out    vl_logic;
        SYNC_TEST       : out    vl_logic;
        STATE_TEST      : out    vl_logic_vector(2 downto 0);
        ENA_TEST        : out    vl_logic
    );
end spi_master;
