module sclk_gen (
    input wire ENA,
    input wire SYNC,
    input  wire RESETn,
    input  wire CPHA,
    input  wire CLK,
    input  wire CPOL,
    output reg SCLK
);

//SCLK_X Variablen
reg SCLK_0;
reg SCLK_1;
reg SCLK_2;
reg SCLK_3;

//T1 Out
reg T1;

//Q1 Out
reg Q1;

//D-FlipFlops
always @(posedge CLK or negedge RESETn) begin
    if(~RESETn) begin
        T1 <= 1'b0;
        Q1 <= 1'b0;
    end
    else if (SYNC) begin
        T1 <= ENA && ~T1;
        Q1 <= T1;
    end
end

//EXOR
always @(*) begin
    SCLK_1 = CPHA && T1;
    SCLK_0 = Q1 && ~CPHA;
    SCLK_2 = SCLK_0 || SCLK_1;
    SCLK_3 = SCLK_2 ^ CPOL;
    SCLK = SCLK_3;
end
    
endmodule