library verilog;
use verilog.vl_types.all;
entity sclk_gen is
    port(
        ENA             : in     vl_logic;
        SYNC            : in     vl_logic;
        RESETn          : in     vl_logic;
        CPHA            : in     vl_logic;
        CLK             : in     vl_logic;
        CPOL            : in     vl_logic;
        SCLK            : out    vl_logic
    );
end sclk_gen;
