//n_bit_counter testbench

`timescale 1ns/1ps

module tb_n_bit_counter();

reg tb_clk;
reg tb_rst;
reg tb_en;

localparam TERMINAL_COUNT = 7 ;

wire [$clog2(TERMINAL_COUNT)-1 : 0] dut_q;
wire dut_tc;

integer i = 0;

initial begin
    tb_clk = 1'b0;
    tb_rst = 1'b0;
    tb_en = 1'b0;
end

always begin
    #10
    tb_clk = ~tb_clk;
end

initial begin
    for (i = 0; i < 4; i = i+1) begin
        @(negedge tb_clk);
    end

    tb_rst = 1'b1;
    @(negedge tb_clk);
    tb_rst = 1'b0;
    @(negedge tb_clk);

    for (i = 0; i < 4; i = i+1) begin
        @(negedge tb_clk);
    end

    tb_en = 1'b1;
    @(negedge tb_clk);
    
    for (i = 0; i < 20; i = i+1) begin
        @(negedge tb_clk);
    end
end

n_bit_counter #(.terminalCount(TERMINAL_COUNT)) dut(
    .CLK(tb_clk),
    .CLK_EN(tb_en),
    .RST(tb_rst),
    .Q(dut_q),
    .TC(dut_tc)
);
    
endmodule