//counters_leds testbench
`timescale 1ns/1ps

module tb_counters_leds();

    reg clock_50_tb;
    reg [0:0] key_tb;
    wire [2:0] ledg_tb;

    integer i = 0;

    initial begin
        clock_50_tb = 1'b0;
        key_tb = 1'b0;
    end

    always begin
        #10;
        clock_50_tb = ~clock_50_tb;
    end

    initial begin
        // delay for four clk cycles
        for (i = 0; i < 4; i = i+1) begin
            @(negedge clock_50_tb);
        end
  
        // assert reset
        key_tb <= 1'b0;
        @(negedge clock_50_tb);
        
        // de-assert reset
        key_tb <= 1'b1;
        @(negedge clock_50_tb);
    end

counters_leds DUT(
    .CLOCK_50(clock_50_tb),
    .KEY(key_tb),
    .LEDG(ledg_tb)
);

endmodule