`timescale 1ns/1ps
module n_bit_counter 
# (parameter terminalCount = 5)
(
    input CLK,
    input CLK_EN,
    input RST,
    output reg [$clog2(terminalCount)-1 : 0] Q,
    output reg TC
);

always @(posedge CLK or posedge RST) begin
    if (RST) begin
        Q = 1'd0;
    end
    else if (CLK_EN) begin
        if(Q<terminalCount) begin
            Q = Q + 1'd1;
            if(Q==terminalCount) begin
                TC = 1'b1;
            end else begin   
                TC = 1'b0;
            end
        end
        else if(Q==terminalCount) begin
            Q = 1'd0;  
            TC = 1'b0;
        end
    end
end
    
endmodule