library verilog;
use verilog.vl_types.all;
entity counters_leds is
    port(
        CLOCK_50        : in     vl_logic;
        KEY             : in     vl_logic_vector(0 downto 0);
        LEDG            : out    vl_logic_vector(2 downto 0)
    );
end counters_leds;
