library verilog;
use verilog.vl_types.all;
entity n_bit_counter is
    generic(
        terminalCount   : integer := 5
    );
    port(
        CLK             : in     vl_logic;
        CLK_EN          : in     vl_logic;
        RST             : in     vl_logic;
        Q               : out    vl_logic_vector;
        TC              : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of terminalCount : constant is 1;
end n_bit_counter;
