diff --git a/labor_4/Aufgabe_6-3/src/sclk_gen.v b/labor_4/Aufgabe_6-3/src/sclk_gen.v
new file mode 100644
index 0000000..0a8d035
--- /dev/null
+++ b/labor_4/Aufgabe_6-3/src/sclk_gen.v
@@ -0,0 +1,19 @@
+module sclk_gen (input ENA,input SYNC,input  RESETn,input  CPHA,input  CLK,input  CPOL,output SCLK);
+
+wire T1_D
+wire T1_ENA
+wire T1_CLR
+reg T1_Q
+
+wire Q1_D
+wire Q1_ENA
+wire Q1_CLR
+reg Q1_Q
+
+reg 
+
+always @(posedge CLK or posedge RESETn) begin
+    
+end
+    
+endmodule
\ No newline at end of file