From 1305535fdf1a4969c427578b45514d5379509930 Mon Sep 17 00:00:00 2001 From: musabe24 Date: Wed, 28 Feb 2024 16:28:41 +0100 Subject: [PATCH] sclk_gen angelegt --- labor_4/Aufgabe_6-3/src/sclk_gen.v | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 labor_4/Aufgabe_6-3/src/sclk_gen.v diff --git a/labor_4/Aufgabe_6-3/src/sclk_gen.v b/labor_4/Aufgabe_6-3/src/sclk_gen.v new file mode 100644 index 0000000..0a8d035 --- /dev/null +++ b/labor_4/Aufgabe_6-3/src/sclk_gen.v @@ -0,0 +1,19 @@ +module sclk_gen (input ENA,input SYNC,input RESETn,input CPHA,input CLK,input CPOL,output SCLK); + +wire T1_D +wire T1_ENA +wire T1_CLR +reg T1_Q + +wire Q1_D +wire Q1_ENA +wire Q1_CLR +reg Q1_Q + +reg + +always @(posedge CLK or posedge RESETn) begin + +end + +endmodule \ No newline at end of file