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Musab Erdem
2024-02-22 12:24:10 +01:00
parent 906e16c100
commit 4337a72010
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22
labor_3/Übungen/ampel/sim/sim.tcl Normal file
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#JZ 2020
#remove working directory
file delete -force work
#Creating the work lib
vlib work
vmap ampel "designlib/ampel"
vmap work work
#Top level testbench
vlog tb_ampel.v
#vlog ../src/ampel.v +define+SIMULATION
#Simulate
vsim -c -t ps -L ampel tb_ampel
#vsim -c -t ps tb_ampel
#get wave
do wave.do
run 1500 us

67
labor_3/Übungen/ampel/sim/tb_ampel.v Normal file
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/******************************************************
*
* Description: tb_ampel
* Date: 13.01.2018
* File Name: tb_ampel.v
* Version: 1.0
* Target: Simulation
* Technology:
*
* Rev Author Date Changes
* -----------------------------------------------------
* 1.0 JZ 13.01.2018 Testbench zur Ampelsteuerung
*******************************************************/
`timescale 1ns / 1ps
module tb_ampel;
reg CLK;
reg RSTn;
reg SW;
wire [2:0] HAUPTSTR_LINKS;
wire [2:0] NEBENSTR_LINKS;
wire [1:0] FUSSGAENGER_LINKS;
wire [2:0] HAUPTSTR_RECHTS;
wire [2:0] NEBENSTR_RECHTS;
wire [1:0] FUSSGAENGER_RECHTS;
//50 MHz clock
initial
begin
CLK = 1'b0;
end
always
CLK = #10 ~CLK;
//push buttons
initial
begin
RSTn = 1'b1;
SW = 1'b1;
#100;
RSTn = 1'b0;
#10;
RSTn = 1'b1;
#50_000;
SW = 1'b0;
#100;
SW = 1'b1;
end
ampel ampel(
.CLOCK_50 (CLK),
.KEY ({RSTn, SW}),
.LEDH_L(HAUPTSTR_LINKS),
.LEDN_L(NEBENSTR_LINKS),
.LEDF_L(FUSSGAENGER_LINKS),
.LEDH_R(HAUPTSTR_RECHTS),
.LEDN_R(NEBENSTR_RECHTS),
.LEDF_R(FUSSGAENGER_RECHTS)
);
endmodule

29
labor_3/Übungen/ampel/sim/wave.do Normal file
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /tb_ampel/CLK
add wave -noupdate /tb_ampel/RSTn
add wave -noupdate /tb_ampel/SW
add wave -noupdate -expand -subitemconfig {{/tb_ampel/HAUPTSTR_LINKS[2]} {-color Red} {/tb_ampel/HAUPTSTR_LINKS[1]} {-color Gold}} /tb_ampel/HAUPTSTR_LINKS
add wave -noupdate -expand -subitemconfig {{/tb_ampel/NEBENSTR_LINKS[2]} {-color Red} {/tb_ampel/NEBENSTR_LINKS[1]} {-color Gold}} /tb_ampel/NEBENSTR_LINKS
add wave -noupdate -expand -subitemconfig {{/tb_ampel/FUSSGAENGER_LINKS[1]} {-color Red}} /tb_ampel/FUSSGAENGER_LINKS
add wave -noupdate -expand -subitemconfig {{/tb_ampel/HAUPTSTR_RECHTS[2]} {-color Red} {/tb_ampel/HAUPTSTR_RECHTS[1]} {-color Gold}} /tb_ampel/HAUPTSTR_RECHTS
add wave -noupdate -expand -subitemconfig {{/tb_ampel/NEBENSTR_RECHTS[2]} {-color Red} {/tb_ampel/NEBENSTR_RECHTS[1]} {-color Gold}} /tb_ampel/NEBENSTR_RECHTS
add wave -noupdate -expand -subitemconfig {{/tb_ampel/FUSSGAENGER_RECHTS[1]} {-color Red}} /tb_ampel/FUSSGAENGER_RECHTS
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {833117378 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 5000
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {1575 us}

159
labor_3/Übungen/ampel/src/ampel_wo_src.v Normal file
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/******************************************************
*
* Description: Vorlage Ampelsteurerung
* Date: 05.01.2018
* File Name: ampel_wo_src.v
* Version: 1.2
* Target: Simulation and Synthesis
* Technology:
*
* Rev Author Date Changes
* -----------------------------------------------------
* 1.0 RHK 10.10.2011 Initial Release
* 1.1 JZ 10.03.2016 several bugfixes
* 1.2 JZ 05.01.2018 angepasst auf neues Ampelboard
* 1.3 MW 07.03.2019 STATE Konstanten angepasst
*******************************************************/
`timescale 1ns / 1ps
module ampel (
input CLOCK_50,
input [1:0] KEY,
output [2:0] LEDH_L,
output [2:0] LEDH_R,
output [2:0] LEDN_L,
output [2:0] LEDN_R,
output [1:0] LEDF_L,
output [1:0] LEDF_R,
output reg DBG
);
reg [9:0] CLKDIV1;
reg [9:0] CLKDIV2;
reg [9:0] CLKDIV3;
reg MELDER;
reg MELDER_Q;
reg MELDER_QQ;
reg MELDER_ACK;
reg CLOCK_ENABLE;
reg START_WARTEN;
reg [3:0] STATE;
reg [2:0] HAUPTSTR;
reg [2:0] NEBENSTR;
reg [1:0] FUSSGAENGER;
reg [3:0] WARTEZAEHLER;
reg [3:0] WARTEWERT;
// R Gr
parameter FUSS_AUS = 2'b00;
parameter FUSS_ROT = 2'b10;
parameter FUSS_GRUEN = 2'b01;
// R Ge Gr
parameter AUTO_AUS = 3'b000;
parameter AUTO_ROT = 3'b100;
parameter AUTO_GELB = 3'b010;
parameter AUTO_GRUEN = 3'b001;
assign RESETn = KEY[1];
assign LEDH_L = HAUPTSTR;
assign LEDH_R = HAUPTSTR;
assign LEDN_L = NEBENSTR;
assign LEDN_R = NEBENSTR;
assign LEDF_L = FUSSGAENGER;
assign LEDF_R = FUSSGAENGER;
`ifdef SIMULATION
`define DIVVAL1 10-1
`define DIVVAL3 5-1
`else
`define DIVVAL1 1000-1
`define DIVVAL3 50-1
`endif
`define FUSS_WARTEN 4 //Wartezeit
`define GELB_DAUER 4 //Wartezeit
`define FUSS_GRUEN_DAUER 4 //Wartezeit
`define ALLE_ROT_DAUER 4 //Wartezeit
`define HAUPT_GRUEN_DAUER 4 //Wartezeit
`define NEBEN_GRUEN_DAUER 4 //Wartezeit
`define PHASEVAL 8
//clock divider to generate 1 Hz
//
// HIER IHREN CODE EINFÜGEN
// synchronisze KEY to CLOCK_50
always @(posedge CLOCK_50) begin
// HIER IHREN CODE EINFÜGEN
end
// Melder sofort setzen
// Melder zuruecksetzen wenn die Anforderung von der Statemachine verarbeitet
// wurde. Die Ampelanlage gibt den FUSSGAENGERn nur dann gruen wenn
// ein Melder anstehst...
always @(posedge CLOCK_50 or negedge RESETn) begin
if (~RESETn)
MELDER <= 1'b0;
else begin
// HIER IHREN CODE EINFÜGEN
end
end
//Wartezaehler
// HIER IHREN CODE EINFÜGEN
assign WARTEN_FERTIG = // HIER IHREN CODE EINFÜGEN;
always @(posedge CLOCK_50 or negedge RESETn)
if (~RESETn)
begin
HAUPTSTR <= AUTO_GRUEN;
NEBENSTR <= AUTO_ROT;
FUSSGAENGER <= FUSS_ROT;
START_WARTEN <= 1'b0;
STATE <= 4'd0;
MELDER_ACK <= 1'b0;
end
else
if (CLOCK_ENABLE)
case (STATE)
4'd0: begin
end
4'd1: begin
end
4'd2: begin
end
4'd3: begin
end
4'd4: begin
end
4'd5: begin
end
4'd6: begin
end
4'd7: begin
end
default:
STATE <= 4'd1;
endcase
endmodule

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labor_3/Übungen/ampel/src/mod_n_counter_10bit.v Normal file
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module mod_n_counter_10bit
# (parameter N = 10)
(
// module inputs
input CLK,
input RST,
input EN,
// module outputs
output reg [9:0] Q,
output TC
);
localparam TERMINAL_COUNT = N-1;
always @ (posedge CLK or posedge RST) begin
if (RST) begin
Q <= 10'd0;
end else if (EN) begin
if (Q == TERMINAL_COUNT) begin
Q <= 10'd0;
end else begin
Q <= Q + 10'd1;
end
end else begin
Q <= Q;
end
end
assign TC = (Q == TERMINAL_COUNT);
endmodule