diff --git a/labor_4/res/spi_master/Schaltplaene_Erweiterungsboard.pdf b/labor_4/res/spi_master/Schaltplaene_Erweiterungsboard.pdf new file mode 100644 index 0000000..b31bd8a Binary files /dev/null and b/labor_4/res/spi_master/Schaltplaene_Erweiterungsboard.pdf differ diff --git a/labor_4/res/spi_master/quartus/led_chaser.sdc b/labor_4/res/spi_master/quartus/led_chaser.sdc new file mode 100644 index 0000000..46cd82b --- /dev/null +++ b/labor_4/res/spi_master/quartus/led_chaser.sdc @@ -0,0 +1,41 @@ +#************************************************************ +# THIS IS A WIZARD-GENERATED FILE. +# +# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition +# +#************************************************************ + +# Copyright (C) 1991-2012 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +# Clock constraints + +create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}] -waveform {0.000 10.000} + + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +#derive_clock_uncertainty +# Not supported for family Cyclone II + +# tsu/th constraints + +# tco constraints + +# tpd constraints + diff --git a/labor_4/res/spi_master/quartus/led_chaser_pin_assignments.csv b/labor_4/res/spi_master/quartus/led_chaser_pin_assignments.csv new file mode 100644 index 0000000..6cdede0 --- /dev/null +++ b/labor_4/res/spi_master/quartus/led_chaser_pin_assignments.csv @@ -0,0 +1,93 @@ +# Quartus II Version 5.1 Internal Build 160 09/19/2005 TO Full Version, +# File: D:\de2_pins\de2_pins.csv, +# Generated on: Wed Sep 28 09:40:34 2005, + +# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software., + +To,Location +SW[0],PIN_N25 +SW[1],PIN_N26 +SW[2],PIN_P25 +SW[3],PIN_AE14 +SW[4],PIN_AF14 +SW[5],PIN_AD13 +SW[6],PIN_AC13 +SW[7],PIN_C13 +SW[8],PIN_B13 +SW[9],PIN_A13 +SW[10],PIN_N1 +SW[11],PIN_P1 +SW[12],PIN_P2 +SW[13],PIN_T7 +SW[14],PIN_U3 +SW[15],PIN_U4 + +LEDR[0],PIN_AE23 +LEDR[1],PIN_AF23 +LEDR[2],PIN_AB21 +LEDR[3],PIN_AC22 +LEDR[4],PIN_AD22 +LEDR[5],PIN_AD23 +LEDR[6],PIN_AD21 +LEDR[7],PIN_AC21 +LEDR[8],PIN_AA14 +LEDR[9],PIN_Y13 +LEDR[10],PIN_AA13 +LEDR[11],PIN_AC14 +LEDR[12],PIN_AD15 +LEDR[13],PIN_AE15 +LEDR[14],PIN_AF13 +LEDR[15],PIN_AE13 + +LEDG[0],PIN_AE22 +LEDG[1],PIN_AF22 +LEDG[2],PIN_W19 +LEDG[3],PIN_V18 +LEDG[4],PIN_U18 +LEDG[5],PIN_U17 +LEDG[6],PIN_AA20 +LEDG[7],PIN_Y18 +CLOCK_50,PIN_N2 + +SSn_A[0],PIN_D25 +SSn_A[1],PIN_J22 +SSn_A[2],PIN_E26 +SSn_A[3],PIN_E25 +MOSI_A,PIN_F24 +SCLK_A,PIN_F23 +MISO_A1,PIN_J21 +MISO_A2,PIN_J20 +SSn_D[0],PIN_F25 +SSn_D[1],PIN_F26 +SSn_D[2],PIN_N18 +SSn_D[3],PIN_P18 +MOSI_D,PIN_G23 +SCLK_D,PIN_G24 +MISO_D,PIN_K22 +PWM_OUT_A,PIN_G25 +PWM_OUT_B,PIN_H23 +PWM_IN_A,PIN_H24 +PWM_IN_B,PIN_J23 + +MOSI_SCOPE,PIN_W23 +SCLK_SCOPE,PIN_V23 +MISO_SCOPE,PIN_W25 + +LCD_RW,PIN_K4 +LCD_EN,PIN_K3 +LCD_RS,PIN_K1 +LCD_DATA[0],PIN_J1 +LCD_DATA[1],PIN_J2 +LCD_DATA[2],PIN_H1 +LCD_DATA[3],PIN_H2 +LCD_DATA[4],PIN_J4 +LCD_DATA[5],PIN_J3 +LCD_DATA[6],PIN_H4 +LCD_DATA[7],PIN_H3 +LCD_ON,PIN_L4 +LCD_BLON,PIN_K2 + +KEY[0],PIN_G26 +KEY[1],PIN_N23 +KEY[2],PIN_P23 +KEY[3],PIN_W26 diff --git a/labor_4/res/spi_master/quartus/output_files/led_chaser.sof b/labor_4/res/spi_master/quartus/output_files/led_chaser.sof new file mode 100644 index 0000000..d3fdc4f Binary files /dev/null and b/labor_4/res/spi_master/quartus/output_files/led_chaser.sof differ diff --git a/labor_4/res/spi_master/sim/libs/spi_master/_info b/labor_4/res/spi_master/sim/libs/spi_master/_info new file mode 100644 index 0000000..74645c2 --- /dev/null +++ b/labor_4/res/spi_master/sim/libs/spi_master/_info @@ -0,0 +1,21 @@ +m255 +K3 +13 +cModel Technology +dC:\digitale_systeme\spi_master\sim +vspi_master +!s100 PDm=HJzS7gNQJSYmeO1UX1 +IN33U 10'b0) + CLKDIV0[9:0] <= CLKDIV0[9:0] - 1'b1; + else + CLKDIV0[9:0] <= `DIVVAL0; + +always @(posedge CLOCK_50 or negedge RESETn) + if (~RESETn) CLKDIV1 <=`DIVVAL1; + else if (CLKDIV0[9:0] == 10'b0) + begin + if (CLKDIV1 > 10'b0) + CLKDIV1[9:0] <= CLKDIV1[9:0] - 1'b1; + else + CLKDIV1[9:0] <= `DIVVAL1; + end + +always @(posedge CLOCK_50 or negedge RESETn) + if (~RESETn) CLKDIV2<=`DIVVAL2; + else if ((CLKDIV1[9:0] == 10'b0) & (CLKDIV0[9:0] == 10'b0)) + begin + if (CLKDIV2 > 10'b0) + CLKDIV2[9:0] <= CLKDIV2[9:0] - 1'b1; + else + CLKDIV2[9:0] <= `DIVVAL2; + end + +// ring_sr + +ring_sr ring_shift_reg( + .CLK(CLOCK_50), + .RSTn(RESETn), + .ENA((CLKDIV0[9:0] == 10'b0) & (CLKDIV1[9:0] == 10'b0) & (CLKDIV2[9:0] == 10'b0)), + .PATTERN(SW), + .Q(LEDS[15:0])); + +// SPI-Master +spi_master spimaster( + .RESETn(RESETn), + .CLK(CLOCK_50), + .CLK_DIVIDER(8'd10), + .SLAVE_SELECT(8'h1), + .DATA_LENGTH(2'd1), + .MODE(2'd1), + .MISO(1'b1), + .TX({16'h0,LEDS}), + .RUN((CLKDIV0[9:0] == 10'b0) & (CLKDIV1[9:0] == 10'b0) & (CLKDIV2[9:0] == 10'b0)), + //module outputs + .RX(), + .SCLK(SCLK_D), + .MOSI(MOSI_D), + .SSn(SSn_D), + .BUSY(), + // module test outputs + .SYNC_TEST(), + .STATE_TEST(), + .ENA_TEST() +); + +endmodule diff --git a/labor_4/res/spi_master/src/ring_sr.v b/labor_4/res/spi_master/src/ring_sr.v new file mode 100644 index 0000000..15fe63f --- /dev/null +++ b/labor_4/res/spi_master/src/ring_sr.v @@ -0,0 +1,23 @@ +module ring_sr( + //inputs + PATTERN, + CLK, + RSTn, + ENA, + //outputs + Q); + + input [15:0] PATTERN; + input CLK,RSTn,ENA; + output reg [15:0] Q; + + always @(posedge CLK) + if(~RSTn) Q <= PATTERN; + + else if (ENA) + begin + Q[15:1] <= Q[14:0]; + Q[0] <= Q[15]; + end + +endmodule // ring_sr \ No newline at end of file diff --git a/labor_4/res/spi_master/src/spi_master_template.v b/labor_4/res/spi_master/src/spi_master_template.v new file mode 100644 index 0000000..0c86962 --- /dev/null +++ b/labor_4/res/spi_master/src/spi_master_template.v @@ -0,0 +1,86 @@ +// module spi_master +// Author: M. Walz + +module spi_master( + //module inputs + // --- Definition of control inputs --- + input wire RESETn, + input wire CLK, + input wire [7:0] CLK_DIVIDER, + input wire [7:0] SLAVE_SELECT, + input wire [1:0] DATA_LENGTH, + input wire [1:0] MODE, + input wire MISO, + input wire [31:0] TX, + input wire RUN, + //module outputs + output reg [31:0] RX, + output SCLK, + output reg MOSI, + output reg [7:0] SSn, + output reg BUSY, + // module test outputs + output wire SYNC_TEST, + output wire [2:0] STATE_TEST, + output wire ENA_TEST + ); + + + + +// --- Definition of internal varibles --- + reg [31:0]TX_SR, RX_SR; + reg [7:0] CLK_DIVIDER_REG; + reg [5:0] CYCLE_CTR; + reg [2:0] STATE; + reg ENA; // Enables operation of SCLK generator + reg T1, Q1; // Used for SLCK generation + wire CPOL, CPHA; // SPI Mode + wire SYNC; // SYNC Signal + +// --- Implementation --- + +// assignments of test signals + assign STATE_TEST = STATE; + assign ENA_TEST = ENA; + assign SYNC_TEST = SYNC; + +// assignments MODE to control wires + assign CPOL = MODE [1]; + assign CPHA = MODE [0]; + +// Clockdivider for generation of SYNC signal + +always @ (posedge CLK or negedge RESETn) begin +end + +// SPI-interface control logic + +always @ (posedge CLK or negedge RESETn) begin + if (~RESETn) begin + end + else case (STATE) + // STATE: Wait + + // STATE: Initialize + + // STATE: Shift + + // STATE: Latch + + // STATE: + + // When transfering data from RX to RX_SR, ignore previously received bytes + case (DATA_LENGTH[1:0]) + 2'h0 : RX[31:0] <= {24'h0, RX_SR[ 7:0]}; // 1 Byte received + 2'h1 : // 2 Bytes received + 2'h2 : // 3 Bytes received + 2'h3 : // 4 Bytes received + endcase + + endcase +end + +// SPI SCLK generation + +endmodule