From 6045facbe511cb0b911894ec864674513bda177b Mon Sep 17 00:00:00 2001 From: musabe24 Date: Wed, 21 Feb 2024 20:03:44 +0100 Subject: [PATCH] =?UTF-8?q?Vorbereitungsaufgabe=202:=20-=20Das=20Zeichen?= =?UTF-8?q?=20"-"=20in=20den=20Dateinamen=20musste=20in=20"=5F"=20umge?= =?UTF-8?q?=C3=A4ndert=20werden.=20-=20Simulation=20lauff=C3=A4hig=20gemac?= =?UTF-8?q?ht=20-=20Wave=20Konfiguration=20angelegt=20-=20Logik=20der=20Te?= =?UTF-8?q?stbench=20angepasst=20-=20Aufgabe=20abgeschlossen=20(-=20ChatGP?= =?UTF-8?q?T=20bewerten=20lassen)=20-=20Kommentare=20eingef=C3=BCgt?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../jk-ff/sim/modelsim.ini | 324 ++++++++++++++++++ .../jk-ff/sim/sim_jk_ff.tcl | 27 ++ .../jk-ff/sim/{tb_jk-ff.v => tb_jk_ff.v} | 37 +- .../Vorbereitungsaufgabe 2/jk-ff/sim/vsim.wlf | Bin 0 -> 73728 bytes .../jk-ff/sim/wave_jk_ff.tcl | 26 ++ .../jk-ff/sim/work/_info | 43 +++ .../jk-ff/sim/work/_vmake | 3 + .../jk-ff/sim/work/jk_ff/_primary.dat | Bin 0 -> 454 bytes .../jk-ff/sim/work/jk_ff/_primary.dbs | Bin 0 -> 531 bytes .../jk-ff/sim/work/jk_ff/_primary.vhd | 12 + .../jk-ff/sim/work/jk_ff/verilog.prw | Bin 0 -> 198 bytes .../jk-ff/sim/work/jk_ff/verilog.psm | Bin 0 -> 4792 bytes .../jk-ff/sim/work/tb_jk_ff/_primary.dat | Bin 0 -> 1243 bytes .../jk-ff/sim/work/tb_jk_ff/_primary.dbs | Bin 0 -> 1486 bytes .../jk-ff/sim/work/tb_jk_ff/_primary.vhd | 4 + .../jk-ff/sim/work/tb_jk_ff/verilog.prw | Bin 0 -> 893 bytes .../jk-ff/sim/work/tb_jk_ff/verilog.psm | Bin 0 -> 11368 bytes .../Vorbereitungsaufgabe 2/jk-ff/src/jk-ff.v | 32 -- .../Vorbereitungsaufgabe 2/jk-ff/src/jk_ff.v | 38 ++ 19 files changed, 497 insertions(+), 49 deletions(-) create mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/modelsim.ini create mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/sim_jk_ff.tcl rename labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/{tb_jk-ff.v => tb_jk_ff.v} (76%) create mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/vsim.wlf create mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/wave_jk_ff.tcl create mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/_info create mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/_vmake create mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/jk_ff/_primary.dat create mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/jk_ff/_primary.dbs create mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/jk_ff/_primary.vhd create mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/jk_ff/verilog.prw create mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/jk_ff/verilog.psm create mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/tb_jk_ff/_primary.dat create mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/tb_jk_ff/_primary.dbs create mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/tb_jk_ff/_primary.vhd create mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/tb_jk_ff/verilog.prw create mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/tb_jk_ff/verilog.psm delete mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/src/jk-ff.v create mode 100644 labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/src/jk_ff.v diff --git a/labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/modelsim.ini b/labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/modelsim.ini new file mode 100644 index 0000000..b0f61a8 --- /dev/null +++ b/labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/modelsim.ini @@ -0,0 +1,324 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both diff --git a/labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/sim_jk_ff.tcl b/labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/sim_jk_ff.tcl new file mode 100644 index 0000000..1f7e6e2 --- /dev/null +++ b/labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/sim_jk_ff.tcl @@ -0,0 +1,27 @@ +# simulation control script für jk-ff Testbench +#Autor: M. Erdem +#Mat.-Nr.: 8757524 +#Datum: 21.02.2024 + +# Vorbereitung der work Library +file delete -force work +vlib work +vmap work work + +# Kompiliere Testbench +puts "Compile Testbench" +vlog tb_jk_ff.v + +# Kompiliere dut Module +puts "Compile DUT module" +vlog ../src/jk_ff.v \ + +# Starten der Simulation +puts "Starting Simulation" +vsim -c -t ps tb_jk_ff + +# Darstellung des Graphen +do wave_jk_ff.tcl + +# Simulation Berechnen für angegebene Zeit +run 300 ns \ No newline at end of file diff --git a/labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/tb_jk-ff.v b/labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/tb_jk_ff.v similarity index 76% rename from labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/tb_jk-ff.v rename to labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/tb_jk_ff.v index 4c78c42..2ae5a92 100644 --- a/labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/tb_jk-ff.v +++ b/labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/tb_jk_ff.v @@ -1,15 +1,24 @@ //Testbench: jk-ff +//Autor: M. Erdem +//Mat.-Nr.: 8757524 +//Datum: 21.02.2024 //Einstellung der Zeitskalierung `timescale 1ns/1ps -module tb_jk-ff; +module tb_jk_ff(); //Definition globaler Pins reg clk; reg res; reg en; +//Definition der Ein- und Ausgänge vom dut +reg dut_j; +reg dut_k; + +wire dut_q; + //Zählervariable i integer i; @@ -27,14 +36,9 @@ always begin #10 clk = ~clk; end -//Definition der Ein- und Ausgänge vom dut -reg dut_j; -reg dut_k; - -wire dut_q; - //Ablauf des Testszenarios initial begin + //Warte 4 Clock-Zyklen for (i=0;i<4;i=i+1) begin @ (negedge clk); @@ -45,24 +49,25 @@ initial begin #40 res = ~res; - //Alle Schaltmöglichkeiten für JK probieren (getriggert auf pos. Flanke) - @ (posedge clk); + //Alle Schaltmöglichkeiten für JK probieren + //Es wird immer auf eine neg. Flanke des clk gewartet, damit das Signal bei einer pos. Flanke bereits anliegt. + @ (negedge clk); dut_j = 1'b0; dut_k = 1'b1; - @ (posedge clk); + @ (negedge clk); dut_j = 1'b1; dut_k = 1'b0; - @ (posedge clk); + @ (negedge clk); dut_j = 1'b1; dut_k = 1'b1; - @ (posedge clk); + @ (negedge clk); dut_j = 1'b0; dut_k = 1'b0; //Enable Eingang aktivieren en = 1'b1; - //Alle Schaltmöglichkeiten für JK probieren (getriggert auf pos. Flanke) + //Alle Schaltmöglichkeiten für JK probieren @ (negedge clk); dut_j = 1'b0; dut_k = 1'b1; @@ -75,13 +80,11 @@ initial begin @ (negedge clk); dut_j = 1'b0; dut_k = 1'b0; - @ (negedge clk); - - + #20; end //Instanziierung des jk-ff -jk-ff dut( +jk_ff dut( .R(res), .CLK(clk), .EN(en), diff --git a/labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/vsim.wlf b/labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/vsim.wlf new file mode 100644 index 0000000000000000000000000000000000000000..22cf21d5239698f3211fba9939f899bce257a37a GIT binary patch literal 73728 zcmeI)?@t^>7{Kvoc4uxEFg-vL8!YV|oY6GG-GM=aTw36WRU~bMtBobWqby1}e#qTX zZA^oSFIwLi(HP?^;v4@7U-Y%_^hKjFF(khCwTaqu=HSj6;*X}L3CVYo8HU}Rndd&) zef8{Y`TgCgSFDxyE$v#obf?H`HRs$9pG4w2kfZPV3qaUn6exfrd+^OG}Ev*$1L zPtRN!dTwZH|FZoyy7R(Klg$id7ma8;hwoaEglqN}b3F9t>^!h1mseLL=XU+aa-IxLjLa2Fl}I*=bJ?MROj$OvbF1r%QAtVPe6bwO z$+hLRp}}HlJ&ac8yk`d@c{|E^rhj8yZ&oB29vqfTCg;Wb%N1E%uU3|pOHsI1T$N;I zLPpYsad~QEn(AKA7t(66tzq&HNv^21lRL8>5#Ff_<)7REFUt7_SsyjPgxBAh9 zdDGr0&vffVc)UXX%;ood?(>6Cr*@*YW?@ds_W)=GVsXGtCwLxp(o&_T+DFCD*ABZglSNNRLX^!|d@B z`a3s;i{x*nsE3xUxz+42-MH|tVc0WusQR>WILvv^X009ILKmY**5I_I{1Q0*~0R#|0009IL zKmY**5I_I{1Q0kX0>%c~-2YGhpZtIQ#x3*+`TwKx2oom)2q1s}0tg_000IagfB*sr zAb:04>jiF40n1 +Z1 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_3\Vorbereitungsaufgaben\Vorbereitungsaufgabe 2\jk-ff\sim +w1708541791 +8../src/jk_ff.v +F../src/jk_ff.v +L0 2 +Z2 OV;L;10.1d;51 +r1 +!s85 0 +31 +!s108 1708541825.484000 +!s107 ../src/jk_ff.v| +!s90 -reportprogress|300|../src/jk_ff.v| +!s101 -O0 +o-O0 +vtb_jk_ff +Z3 ISgG=LbWX]jL6OJOWU_5jb2 +Z4 VUT[Z^]I>AQgS]P1gjENDb3 +R1 +Z5 w1708541779 +Z6 8tb_jk_ff.v +Z7 Ftb_jk_ff.v +L0 6 +R2 +r1 +31 +o-O0 +!i10b 1 +Z8 !s100 K>`z4HiDMJNSBPT)niOV^Kox)mf`5 zBR4N!9?P84v5%1@%-~ib>%0qI8`$;*b8TbSjF;b(S6J|X?GlIKbbYn|i7o;M4a~vDhtiiG@Mz(fW2Icq2y~(E8zvw* z@f4@PvRs#AZ7dAmCvH_#aMWtl6J{+IZPHea@nT|S$Xqzz(YE=kINJf4ZyM~=lNydz zw||xf>3nMnA}>~QO+1h{f#ZVEZgr5UwZ0(Hj~$#Bl-_#YZv%0*@`K1kUha>Y>zp_O zw(rgXE4&R>xP<3I)!U!k|Z<5de#0N-j}Q=Np-H;f539G=< literal 0 HcmV?d00001 diff --git a/labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/jk_ff/_primary.dbs b/labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/jk_ff/_primary.dbs new file mode 100644 index 0000000000000000000000000000000000000000..76378a0a067cf542f79f70522fff75a0f93f8773 GIT binary patch literal 531 zcmZ`#El)#15S;sfe$XBX$OnN|@evF)HE2W~h9HVW6R?O1916n^AS47+P=G74%YBmIbIXS;_^iQMRg3m1}ZjS%4Z^ zlp{SSpdr6pKx~j@E#Kkti3BSAL#@oFR%cSSK{42-CO!w;es=9$WB>R!`F^kO++0nb z(_wRrZohXw+01G*`fxVLcGoVm$BX*Q!F6?N(a;0e&-v4!)y}_*(tca7^I=$>j}#=E Z4~0PfB*4$0D?ciT>F@wQhO<~(`2&Z4ExrH% literal 0 HcmV?d00001 diff --git a/labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/jk_ff/_primary.vhd b/labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/jk_ff/_primary.vhd new file mode 100644 index 0000000..cead14d --- /dev/null +++ b/labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/jk_ff/_primary.vhd @@ -0,0 +1,12 @@ +library verilog; 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