diff --git a/labor_4/Aufgabe_6-4/src/sr_fsm.v b/labor_4/Aufgabe_6-4/src/sr_fsm.v index 82a9882..e9299c9 100644 --- a/labor_4/Aufgabe_6-4/src/sr_fsm.v +++ b/labor_4/Aufgabe_6-4/src/sr_fsm.v @@ -3,13 +3,14 @@ module sr_fsm ( input reset, input run, input Sync, - input CYCLE_CTR, input MISO, output MOSI, output [7:0] SSn, output ENA ); +reg CYCLE_CTR; //= Anzahl der zu verschickende Daten + //Definition der States parameter STATE_WAIT = 3'h0; parameter STATE_INIT = 3'h1; @@ -36,51 +37,65 @@ always @(STATE) begin case (STATE) STATE_WAIT: if (run == 1'b1) begin - NEXT_STATE = STATE_INIT; + NEXT_STATE <= STATE_INIT; end else begin - NEXT_STATE = STATE_WAIT; + NEXT_STATE <= STATE_WAIT; end STATE_INIT: if (Sync == 1'b1) begin - NEXT_STATE = STATE_SHIFT; + NEXT_STATE <= STATE_SHIFT; end else begin - NEXT_STATE = STATE_INIT; + NEXT_STATE <= STATE_INIT; end STATE_SHIFT: - CYCLE_CTR = CYCLE_CTR - 1; //CYCLE_CTR dekrementieren - //Schieberegister schieben?? - if (Sync == 1'b1) begin - NEXT_STATE = STATE_LATCH; + NEXT_STATE <= STATE_LATCH; end else begin - NEXT_STATE = STATE_SHIFT; + NEXT_STATE <= STATE_SHIFT; end STATE_LATCH: if (Sync == 1'b1 && CYCLE_CTR != 6'h0) begin - NEXT_STATE = STATE_SHIFT; + NEXT_STATE <= STATE_SHIFT; end else if (Sync == 1'b1 && CYCLE_CTR == 6'h0) begin - NEXT_STATE = STATE_CLEAR; + NEXT_STATE <= STATE_CLEAR; end else begin - NEXT_STATE = STATE_LATCH; + NEXT_STATE <= STATE_LATCH; end STATE_CLEAR: if (Sync == 1'b1) begin - NEXT_STATE = STATE_WAIT; + NEXT_STATE <= STATE_WAIT; end else begin - NEXT_STATE = STATE_CLEAR; + NEXT_STATE <= STATE_CLEAR; end - default: NEXT_STATE = STATE; + default: NEXT_STATE <= STATE_WAIT; + endcase +end + +always @(STATE) begin + case (STATE) + STATE_WAIT: + + STATE_INIT: + + STATE_SHIFT: + CYCLE_CTR <= CYCLE_CTR - 1; + + STATE_LATCH: + + STATE_CLEAR: + + default: endcase end diff --git a/labor_4/Aufgabe_6-5/src/down_counter.v b/labor_4/Aufgabe_6-5/src/down_counter.v index 959fe45..2d31e6b 100644 --- a/labor_4/Aufgabe_6-5/src/down_counter.v +++ b/labor_4/Aufgabe_6-5/src/down_counter.v @@ -1,13 +1,13 @@ -module down_counter #( - parameter CLOCK_DIVIDER = 5 -) +module down_counter ( + input [7:0] CLK_DIVIDER; input CLK, input RESETn, - output reg [$clog2(CLOCK_DIVIDER)-1 : 0] Q, output wire SYNC ); +output reg [$clog2(CLK_DIVIDER)-1 : 0] Q, + always @(posedge CLK or negedge RESETn) begin if(~RESETn) begin Q <= 1'd0; @@ -17,7 +17,7 @@ always @(posedge CLK or negedge RESETn) begin Q <= Q - 1'd1; end else if(Q == 1'd0) begin - Q <= CLOCK_DIVIDER; + Q <= CLK_DIVIDER; end end end diff --git a/labor_4/res/spi_master/sim/modelsim.ini b/labor_4/res/spi_master/sim/modelsim.ini new file mode 100644 index 0000000..81610e2 --- /dev/null +++ b/labor_4/res/spi_master/sim/modelsim.ini @@ -0,0 +1,325 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + +work = work +spi_master = libs/spi_master +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both diff --git a/labor_4/res/spi_master/sim/vsim.wlf b/labor_4/res/spi_master/sim/vsim.wlf new file mode 100644 index 0000000..62012ed Binary files /dev/null and b/labor_4/res/spi_master/sim/vsim.wlf differ diff --git a/labor_4/res/spi_master/sim/work/_info b/labor_4/res/spi_master/sim/work/_info new file mode 100644 index 0000000..110cef9 --- /dev/null +++ b/labor_4/res/spi_master/sim/work/_info @@ -0,0 +1,24 @@ +m255 +K3 +13 +cModel Technology +Z0 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_4\res\spi_master\sim +vspi_master_tb +!i10b 1 +!s100 WzH7KW]Xga2>VXnFzWQ6=2 +I_fR75FE 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both diff --git a/labor_4_drive/sim/sim.do b/labor_4_drive/sim/sim.do new file mode 100644 index 0000000..2491ad7 --- /dev/null +++ b/labor_4_drive/sim/sim.do @@ -0,0 +1,19 @@ +#remove working directory +file delete -force work + +#Creating the work lib +vlib work +vmap work work + + +#Top level testbench +vlog spi_master_tb.v \ + ../src/spi_master.v + +#Simulate +vsim -c -t ps spi_master_tb + +#get wave +do wave.do + +run 25 us \ No newline at end of file diff --git a/labor_4_drive/sim/spi_master_tb.v b/labor_4_drive/sim/spi_master_tb.v new file mode 100644 index 0000000..172ebdf --- /dev/null +++ b/labor_4_drive/sim/spi_master_tb.v @@ -0,0 +1,96 @@ +`timescale 1ns/1ps + +module spi_master_tb; +// top level testbench, no inputs or outputs + + reg RESETn_TB, RUN_TB, CLOCK_50_TB; + reg [7:0] CLK_DIVIDER_TB, SLAVE_SELECT_TB; + reg [1:0] DATA_LENGTH_TB, MODE_TB; + reg [31:0] TX_TB; + +//DUT module outputs + wire [31:0] RX_TB; + wire [7:0] SSn_TB; + wire SCLK_TB, MOSI_TB, BUSY_TB, MISO_TB; + +//DUT test signals + wire [2:0] STATE_TEST_TB; + wire SYNC_TEST_TB, ENA_TEST_TB; + + assign MISO_TB = 1'b0; + + initial begin + // Reset + CLOCK_50_TB <= 1'b0; + RESETn_TB <= 1'b1; + + TX_TB <= 32'h0; + CLK_DIVIDER_TB <= 8'h0; + SLAVE_SELECT_TB <= 8'h0; + DATA_LENGTH_TB <= 2'b00; + MODE_TB <= 2'b00; + RUN_TB <= 1'b0; + + #20 RESETn_TB <= 1'b0; + #80 RESETn_TB <= 1'b1; + + // spi_master setup: 8 Bit Daten, Mode 0 + + TX_TB <= 32'h000000AA; + CLK_DIVIDER_TB <= 8'h1; + SLAVE_SELECT_TB <= 8'h1; + DATA_LENGTH_TB <= 2'b00; + MODE_TB <= 2'b00; + + #100 RUN_TB <= 1'b1; + #100 RUN_TB <= 1'b0; + + #5000 + + // spi_master setup: 16 Bit Daten, Mode 3 + TX_TB <= 32'h000084A8; + CLK_DIVIDER_TB <= 8'h4; + SLAVE_SELECT_TB <= 8'h1; + DATA_LENGTH_TB <= 2'b01; + MODE_TB <= 2'b11; + + #100 RUN_TB <= 1'b1; + #100 RUN_TB <= 1'b0; + + #7000 + + // spi_master setup: 8 Bit Daten, Mode 2 + TX_TB <= 32'h000084A8; + CLK_DIVIDER_TB <= 8'h4; + SLAVE_SELECT_TB <= 8'h2; + DATA_LENGTH_TB <= 2'b00; + MODE_TB <= 2'b10; + + #100 RUN_TB <= 1'b1; + #100 RUN_TB <= 1'b0; + + end + + always begin + #10 CLOCK_50_TB <= ~CLOCK_50_TB; + end + + spi_master spi_master_test( + .RESETn(RESETn_TB), + .CLK(CLOCK_50_TB), + .RUN(RUN_TB), + .MODE(MODE_TB), + .DATA_LENGTH(DATA_LENGTH_TB), + .CLK_DIVIDER(CLK_DIVIDER_TB), + .SLAVE_SELECT(SLAVE_SELECT_TB), + .TX(TX_TB), + .SCLK(SCLK_TB), + .MISO(MISO_TB), + .MOSI(MOSI_TB), + .SSn(SSn_TB), + .RX(RX_TB), + .BUSY(BUSY_TB), + .SYNC_TEST(SYNC_TEST_TB), + .STATE_TEST(STATE_TEST_TB), + .ENA_TEST(ENA_TEST_TB)); +endmodule \ No newline at end of file diff --git a/labor_4_drive/sim/vsim.wlf b/labor_4_drive/sim/vsim.wlf new file mode 100644 index 0000000..dfabca4 Binary files /dev/null and b/labor_4_drive/sim/vsim.wlf differ diff --git a/labor_4_drive/sim/wave.do b/labor_4_drive/sim/wave.do new file mode 100644 index 0000000..43bd9d7 --- /dev/null +++ b/labor_4_drive/sim/wave.do @@ -0,0 +1,43 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /spi_master_tb/RESETn_TB +add wave -noupdate /spi_master_tb/RUN_TB +add wave -noupdate /spi_master_tb/CLOCK_50_TB +add wave -noupdate -radix unsigned /spi_master_tb/CLK_DIVIDER_TB +add wave -noupdate /spi_master_tb/SLAVE_SELECT_TB +add wave -noupdate /spi_master_tb/DATA_LENGTH_TB +add wave -noupdate -radix unsigned /spi_master_tb/MODE_TB +add wave -noupdate -radix hexadecimal /spi_master_tb/TX_TB +add wave -noupdate -radix hexadecimal /spi_master_tb/RX_TB +add wave -noupdate -divider {SPI Interface} +add wave -noupdate /spi_master_tb/SSn_TB +add wave -noupdate /spi_master_tb/SCLK_TB +add wave -noupdate /spi_master_tb/MOSI_TB +add wave -noupdate /spi_master_tb/BUSY_TB +add wave -noupdate /spi_master_tb/MISO_TB +add wave -noupdate -divider {SPI Master intern} +add wave -noupdate /spi_master_tb/SYNC_TEST_TB +add wave -noupdate -radix unsigned -childformat {{{/spi_master_tb/STATE_TEST_TB[2]} -radix unsigned} {{/spi_master_tb/STATE_TEST_TB[1]} -radix unsigned} {{/spi_master_tb/STATE_TEST_TB[0]} -radix unsigned}} -subitemconfig {{/spi_master_tb/STATE_TEST_TB[2]} {-height 15 -radix unsigned} {/spi_master_tb/STATE_TEST_TB[1]} {-height 15 -radix unsigned} {/spi_master_tb/STATE_TEST_TB[0]} {-height 15 -radix unsigned}} /spi_master_tb/STATE_TEST_TB +add wave -noupdate /spi_master_tb/ENA_TEST_TB +add wave -noupdate /spi_master_tb/spi_master_test/BUSY +add wave -noupdate -radix hexadecimal /spi_master_tb/spi_master_test/TX_SR +add wave -noupdate -radix hexadecimal /spi_master_tb/spi_master_test/RX_SR +add wave -noupdate -radix unsigned /spi_master_tb/spi_master_test/CYCLE_CTR +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {24527614 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 232 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {26250 ns} diff --git a/labor_4_drive/sim/work/_info b/labor_4_drive/sim/work/_info new file mode 100644 index 0000000..44e8f7f --- /dev/null +++ b/labor_4_drive/sim/work/_info @@ -0,0 +1,43 @@ +m255 +K3 +13 +cModel Technology +Z0 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_4_drive\sim +vspi_master +!i10b 1 +!s100 eeKKVXnFzWQ6=2 +I_fR75FE 8'h0) begin + CLK_DIVIDER_REG <= CLK_DIVIDER_REG - 1'b1; + end + end + +assign SYNC = (CLK_DIVIDER_REG == 8'h0); + +// SPI-interface control logic +always @(posedge CLK or negedge RESETn) begin + if (~RESETn) begin + STATE <= 3'b000; + TX_SR <= 32'h0; + RX_SR <= 32'h0; + CYCLE_CTR <= 6'h0; + SSn <= 8'hFF; + ENA <= 1'b0; + MOSI <= 1'b0; + RX <= 32'b0; + BUSY <= 1'b0; + end else begin + case (STATE) + // STATE: Wait + 3'h0: + if (RUN) begin + STATE <= 3'h1; + end + + // STATE: Initialize + 3'h1: + if (SYNC) begin + SSn <= ~SLAVE_SELECT; + ENA <= 1'b1; + if (CPHA) begin + case (DATA_LENGTH[1:0]) + 2'h0: begin + CYCLE_CTR <= 6'h8; + TX_SR[31:24] <= TX[7:0]; + end + 2'h1: begin + CYCLE_CTR <= 6'h10; + TX_SR[31:16] <= TX[15:0]; + end + 2'h2: begin + CYCLE_CTR <= 6'h18; + TX_SR[31:8] <= TX[23:0]; + end + 2'h3: begin + CYCLE_CTR <= 6'h20; + TX_SR <= TX; + end + endcase + BUSY <= 1'b1; + STATE <= 3'h2; + end + end + + // STATE: Shift + 3'h2: + if (SYNC) begin + if (~CPHA) begin + SSn <= ~SLAVE_SELECT; + end + MOSI <= TX_SR[31]; + RX_SR <= {RX_SR[30:0], MISO}; + TX_SR <= {TX_SR[30:0], 1'b0}; + CYCLE_CTR <= CYCLE_CTR - 1'b1; + if (CYCLE_CTR == 0) begin + STATE <= 3'h3; + end + end + + // STATE: Latch + 3'h3: + if (SYNC) begin + RX_SR[0] <= MISO; + if (CYCLE_CTR == 0) begin + STATE <= 3'h4; + ENA <= 1'b0; + end else begin + STATE <= 3'h2; + end + end + + // STATE: Clear / Idle + 3'h4: + if (SYNC) begin + SSn <= 8'hFF; + BUSY <= 1'b0; + STATE <= 3'h0; + case (DATA_LENGTH[1:0]) + 2'h0: RX <= {24'h0, RX_SR[7:0]}; // 1 Byte received + 2'h1: RX <= {16'h0, RX_SR[15:0]}; // 2 Bytes received + 2'h2: RX <= {8'h0, RX_SR[23:0]}; // 3 Bytes received + 2'h3: RX <= RX_SR; // 4 Bytes received + endcase + end + endcase + end +end + +// SPI SCLK generation +always @(posedge CLK or negedge RESETn) begin + if (~RESETn) begin + T1 <= 1'b0; + Q1 <= 1'b0; + end else if (SYNC) begin + T1 <= ~T1 & ENA; + Q1 <= T1; + end +end + +assign SCLK = ((Q1 & ~CPHA) | (T1 & CPHA)) ^ CPOL; + +endmodule \ No newline at end of file