From 8f9d0cd001789cd551f648ed4088ceb65189e955 Mon Sep 17 00:00:00 2001 From: musabe24 Date: Thu, 29 Feb 2024 16:33:57 +0100 Subject: [PATCH] =?UTF-8?q?L=C3=B6sung=20vom=20Drive=20kopiert=20und=20mit?= =?UTF-8?q?=20ChatGPT=20korrigieren=20lassen.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- labor_4/Aufgabe_6-4/src/sr_fsm.v | 47 ++- labor_4/Aufgabe_6-5/src/down_counter.v | 10 +- labor_4/res/spi_master/sim/modelsim.ini | 325 ++++++++++++++++++ labor_4/res/spi_master/sim/vsim.wlf | Bin 0 -> 172032 bytes labor_4/res/spi_master/sim/work/_info | 24 ++ labor_4/res/spi_master/sim/work/_vmake | 3 + .../sim/work/spi_master_tb/_primary.dat | Bin 0 -> 1979 bytes .../sim/work/spi_master_tb/_primary.dbs | Bin 0 -> 2317 bytes .../sim/work/spi_master_tb/_primary.vhd | 4 + .../sim/work/spi_master_tb/verilog.prw | Bin 0 -> 1438 bytes .../sim/work/spi_master_tb/verilog.psm | Bin 0 -> 19464 bytes labor_4/res/spi_master/src/spi_master.v | 203 +++++++++++ .../res/spi_master/src/spi_master_template.v | 86 ----- labor_4_drive/sim/modelsim.ini | 324 +++++++++++++++++ labor_4_drive/sim/sim.do | 19 + labor_4_drive/sim/spi_master_tb.v | 96 ++++++ labor_4_drive/sim/vsim.wlf | Bin 0 -> 40960 bytes labor_4_drive/sim/wave.do | 43 +++ labor_4_drive/sim/work/_info | 43 +++ labor_4_drive/sim/work/_vmake | 3 + .../sim/work/spi_master/_primary.dat | Bin 0 -> 3076 bytes .../sim/work/spi_master/_primary.dbs | Bin 0 -> 2985 bytes .../sim/work/spi_master/_primary.vhd | 23 ++ labor_4_drive/sim/work/spi_master/verilog.prw | Bin 0 -> 1385 bytes labor_4_drive/sim/work/spi_master/verilog.psm | Bin 0 -> 29216 bytes .../sim/work/spi_master_tb/_primary.dat | Bin 0 -> 1979 bytes .../sim/work/spi_master_tb/_primary.dbs | Bin 0 -> 2317 bytes .../sim/work/spi_master_tb/_primary.vhd | 4 + .../sim/work/spi_master_tb/verilog.prw | Bin 0 -> 1438 bytes .../sim/work/spi_master_tb/verilog.psm | Bin 0 -> 19464 bytes labor_4_drive/src/spi_master.v | 163 +++++++++ 31 files changed, 1313 insertions(+), 107 deletions(-) create mode 100644 labor_4/res/spi_master/sim/modelsim.ini create mode 100644 labor_4/res/spi_master/sim/vsim.wlf create mode 100644 labor_4/res/spi_master/sim/work/_info create mode 100644 labor_4/res/spi_master/sim/work/_vmake create mode 100644 labor_4/res/spi_master/sim/work/spi_master_tb/_primary.dat create mode 100644 labor_4/res/spi_master/sim/work/spi_master_tb/_primary.dbs create mode 100644 labor_4/res/spi_master/sim/work/spi_master_tb/_primary.vhd create mode 100644 labor_4/res/spi_master/sim/work/spi_master_tb/verilog.prw create mode 100644 labor_4/res/spi_master/sim/work/spi_master_tb/verilog.psm create mode 100644 labor_4/res/spi_master/src/spi_master.v delete mode 100644 labor_4/res/spi_master/src/spi_master_template.v create mode 100644 labor_4_drive/sim/modelsim.ini create mode 100644 labor_4_drive/sim/sim.do create mode 100644 labor_4_drive/sim/spi_master_tb.v create mode 100644 labor_4_drive/sim/vsim.wlf create mode 100644 labor_4_drive/sim/wave.do create mode 100644 labor_4_drive/sim/work/_info create mode 100644 labor_4_drive/sim/work/_vmake create mode 100644 labor_4_drive/sim/work/spi_master/_primary.dat create mode 100644 labor_4_drive/sim/work/spi_master/_primary.dbs create mode 100644 labor_4_drive/sim/work/spi_master/_primary.vhd create mode 100644 labor_4_drive/sim/work/spi_master/verilog.prw create mode 100644 labor_4_drive/sim/work/spi_master/verilog.psm create mode 100644 labor_4_drive/sim/work/spi_master_tb/_primary.dat create mode 100644 labor_4_drive/sim/work/spi_master_tb/_primary.dbs create mode 100644 labor_4_drive/sim/work/spi_master_tb/_primary.vhd create mode 100644 labor_4_drive/sim/work/spi_master_tb/verilog.prw create mode 100644 labor_4_drive/sim/work/spi_master_tb/verilog.psm create mode 100644 labor_4_drive/src/spi_master.v diff --git a/labor_4/Aufgabe_6-4/src/sr_fsm.v b/labor_4/Aufgabe_6-4/src/sr_fsm.v index 82a9882..e9299c9 100644 --- a/labor_4/Aufgabe_6-4/src/sr_fsm.v +++ b/labor_4/Aufgabe_6-4/src/sr_fsm.v @@ -3,13 +3,14 @@ module sr_fsm ( input reset, input run, input Sync, - input CYCLE_CTR, input MISO, output MOSI, output [7:0] SSn, output ENA ); +reg CYCLE_CTR; //= Anzahl der zu verschickende Daten + //Definition der States parameter STATE_WAIT = 3'h0; parameter STATE_INIT = 3'h1; @@ -36,51 +37,65 @@ always @(STATE) begin case (STATE) STATE_WAIT: if (run == 1'b1) begin - NEXT_STATE = STATE_INIT; + NEXT_STATE <= STATE_INIT; end else begin - NEXT_STATE = STATE_WAIT; + NEXT_STATE <= STATE_WAIT; end STATE_INIT: if (Sync == 1'b1) begin - NEXT_STATE = STATE_SHIFT; + NEXT_STATE <= STATE_SHIFT; end else begin - NEXT_STATE = STATE_INIT; + NEXT_STATE <= STATE_INIT; end STATE_SHIFT: - CYCLE_CTR = CYCLE_CTR - 1; //CYCLE_CTR dekrementieren - //Schieberegister schieben?? - if (Sync == 1'b1) begin - NEXT_STATE = STATE_LATCH; + NEXT_STATE <= STATE_LATCH; end else begin - NEXT_STATE = STATE_SHIFT; + NEXT_STATE <= STATE_SHIFT; end STATE_LATCH: if (Sync == 1'b1 && CYCLE_CTR != 6'h0) begin - NEXT_STATE = STATE_SHIFT; + NEXT_STATE <= STATE_SHIFT; end else if (Sync == 1'b1 && CYCLE_CTR == 6'h0) begin - NEXT_STATE = STATE_CLEAR; + NEXT_STATE <= STATE_CLEAR; end else begin - NEXT_STATE = STATE_LATCH; + NEXT_STATE <= STATE_LATCH; end STATE_CLEAR: if (Sync == 1'b1) begin - NEXT_STATE = STATE_WAIT; + NEXT_STATE <= STATE_WAIT; end else begin - NEXT_STATE = STATE_CLEAR; + NEXT_STATE <= STATE_CLEAR; end - default: NEXT_STATE = STATE; + default: NEXT_STATE <= STATE_WAIT; + endcase +end + +always @(STATE) begin + case (STATE) + STATE_WAIT: + + STATE_INIT: + + STATE_SHIFT: + CYCLE_CTR <= CYCLE_CTR - 1; + + STATE_LATCH: + + STATE_CLEAR: + + default: endcase end diff --git a/labor_4/Aufgabe_6-5/src/down_counter.v b/labor_4/Aufgabe_6-5/src/down_counter.v index 959fe45..2d31e6b 100644 --- a/labor_4/Aufgabe_6-5/src/down_counter.v +++ b/labor_4/Aufgabe_6-5/src/down_counter.v @@ -1,13 +1,13 @@ -module down_counter #( - parameter CLOCK_DIVIDER = 5 -) +module down_counter ( + input [7:0] CLK_DIVIDER; input CLK, input RESETn, - output reg [$clog2(CLOCK_DIVIDER)-1 : 0] Q, output wire SYNC ); +output reg [$clog2(CLK_DIVIDER)-1 : 0] Q, + always @(posedge CLK or negedge RESETn) begin if(~RESETn) begin Q <= 1'd0; @@ -17,7 +17,7 @@ always @(posedge CLK or negedge RESETn) begin Q <= Q - 1'd1; end else if(Q == 1'd0) begin - Q <= CLOCK_DIVIDER; + Q <= CLK_DIVIDER; end end end diff --git a/labor_4/res/spi_master/sim/modelsim.ini b/labor_4/res/spi_master/sim/modelsim.ini new file mode 100644 index 0000000..81610e2 --- /dev/null +++ b/labor_4/res/spi_master/sim/modelsim.ini @@ -0,0 +1,325 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + +work = work +spi_master = libs/spi_master +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both diff --git a/labor_4/res/spi_master/sim/vsim.wlf b/labor_4/res/spi_master/sim/vsim.wlf new file mode 100644 index 0000000000000000000000000000000000000000..62012edfd2b22923490bfeb8ecd9b41f37b6f3d2 GIT binary patch literal 172032 zcmeI5U2GKB702)0o!QyNfU$8x0yv(9C4dRo#z{yV2sU1~CVWM#jX)xDoUl=8Fd$4w zqN@Z12qOcs!n& z&8&?F+x%8uv%bvE?EL1Q|2_AdJ7-s25-*CKLWrb#3i-_!deuJ(^-Qa$_2^Mg>u>AP zD#Y&f4Tqi^AAQOkxNxdC)|ekC92h$C`1V7E$GacuK2X`L^1FELtwFu3b4S-HU1)08 zN$a-|ruEA{nDv4O1Rwwb2tWV=5P$##AOHafKmY;|fB*y_009U<00Izz00bZa0SG_< z0ylv`xh%e?c4IxQEPpD$P9^78X-3|ZjZ(C{A(M#)neCN^5PCM>t7jA1rdOowPo#|O z*Phg}&6+$Qi^+G=Ms~s|ZYifkA}PPGOOa^qlqe} zDq(bepr3lv=+e&&>iXV{-ePDy*Z!mTZc+E+tEZj+ zmtv35FO8obdsgg`s!iXM5Z(PfCr8g*EQ$-GC%d|LbdHPjT_?xRohqJ@V&ll@c=4oo z{`A@Ioug;YrHf-H6T5a4#S6tf34QzdbJ~TA!g#Rre(`YUo(j`BFlR8BN-&8U2JNR`wq}Fp}SY?6v**fuqLDa$7$6 zzM*dwdSl^W-?4#-k;1^if&L+_{je-H%j^2jGg5yfwKCr~B>F}U4jlgK(BOXK>(T zE{>YoefcfI*en|I_lm|%Vs$Pjl1=w)*dQ9RqVbB{EWdS+Sa-Qqw5=B#FRv4u*NSa} zcZ-fpM}Cdib*D(??huB2rFpez%&c!}5^Gk8b&XA;ZKc?_;)+PhZ#0O8%gfY%iq)5e zd@m)|=a#=K-rJHY6k6Ica-G~P#Ow0WwD^kr^F*Zyf4t@$tv$0d*}iZ1&xI34 zyVjj-KeWH_^&>`m;{HVY^1_M3SNlhX1_~`N=8O+ppLji!en9_c=I&g}uhQ4e6@{U` zp;gB>>3x~qS$Rc>%nzlPzf>?|Ju*%<)Xd zS&%ZrocI$05P$##AOHafKmY;|fB*y_009U<00Izz00bZa0SG_<0uX?}Eg@j#^{3_k z#Utu(>uI%V`9_fvSG8sP5{6#Z#8KI%<#HcrI}%2FO3yW4(+Ua0*rVm-6>VeENNc%g zswq*uU%j0N1Rwwb2tWV=5P$##AOHafKmY;|fB*y_009U<00Izz00bZa0SG_<0x=P= z^88cz|Co-+VITkj2tWV=5P$##AOHafKmY;|fB*y_009U<00Izz00bZa0SG_<0uZ>l z1d?iZRt*6AQT|`swX%AsKddzYsr8j+A$D7v*w1}oudFwf?f-ROSvybKZPi!S&aKCN z@~;c+$33xDX?`}j_Ycmw@BN~B?qaVo)%N++t0{PUgI?WmwmY_YRn|sly|DHuvi7oz zR=IbVvrTKlEKi!(C(XZ1nsQ!$N~R3@NjV3-F=>7=X=)|w!~R}llZ2jTX;XS+RE}7+^gUGCPWu$dgO6F%J zGpXp56qkBFW=Ba;H2*beF0b`A>w^iKi}!;~nm5$@YrWIDIG*=(SeMOI*RQ^}b<*zZ$2goA|fkL1VC7Rsged3c-)8D;eZ8lWtq6(e`*#$jCH!FFVeBaT^=}h?q?$Pq z|Bj-xgdZ%v(^7e>C3mSfr!UX5-qgOQD>1Fy|1V8J{@)&2$p0%{A^#sd6qEl~He$y$ zYkCW_5vlO^)EvRX-xfX=hrfrjsxI}J^-_abuhk&`Z>I|aW*Xt$mE3DUash(AsU7`< ze&Pm2&=YHt?>CY~9X<1(4mt=ECz{1d1grsTz#6KPcl^PC;U9%SAy5buf;F4BW_CpW zzco1NK>mL&Y0;Y514r-O;7F8~@Bm79&LPTv{oB+y68Zlxy(hT_z0f;e{nsE$ON}Ef z8md)3w5afKdn0w?Vx_$2K6ETACh$7{{OioV9EcJ z|M$5;tZA@KDy@8jO8!65E6Sg@{iFJ~RTp4dj>YkzyfNkArGPc_g8m&vX;}zMQ&5pb zqayS`WxHIhAeT2j*<@k8Dyb%93fm$*x z|No>YU(ftf#q+K80I72MtvA)bl_^CG%elxUkxR0=o4?;iX$kDx^xZ(7u)?Rnr@*I} zH=hFCT_CzU+?rU6)}eK19a`tk74iSjL^KgiL=(}(nK36~E#%FEVsQ8j_zd_A_zd_A z_zd_AN(a1#U=5GtNbMmK`&d-=;pYEU@|F7kw)Y?MwFZ@PDfL%bn2pyEUzze)t0~7+ z>Vq2PQCCug&+Fprfm|)FR!A|(7&{^AKDXFke3vTL5z8&F6h|qenI)7yDVfy&pXpDB zk6FyYU=?*N^{XBIiWqmre#ill0}7wD`<27rf|j5qXi2yYVISBB_OU?hgZlsFlKEN5 zOir4zWK#cMO`+T@UOm1I_5Y*JKEua9D~=XVj)|+q)v6J9kEavHS}Q*$!;1Bs+yHg` z7fkj4lzLX{|6ldw|LgZnW(KdR{~xR`;o499n)r2apYeNP{ucTbb86<)^^aSu-9$^G zD+jD#MV;MnmBl`=59|Z`aCCsR6s)DF#~Pe|<7Ob3*G3;vUunw0&u4 z`*5qE{=YLwS!PX*HruqxtyJvW<>2@5{Vj|Oj0;O+TyXj}x%r^kK6Z|sW9N?Bua;M;zbeaYMhUJKS1V{H5^Jsen7-X5)^l>pD^dTy zDonLJgm5_|_dYXL0xRak%!y~??Vu%SNz@rmJuW-_ihf1E!Y{!u!7sUu{1WQ_Q~$qe z@P2Q}-x5APP*Far_YlsI`u}r{ z@9Fvf`u!j3{|DVoP>(SXe<1!4)q|j4MW3a^3Rcu44j<9659|Z`z&;!u;J)A>Pd7v3ok_5W@0^+G9G zUC}!^wx)-$f>p%XkfUYvt4f^F<=`jdZy^>F-6Mn*tcc}@d(YSh_JMt1A6|Ff?{h?H zK}*mQv;-|dOWgS!nusPYDNS_q|0?x8{r-O|74G(XzrPS}2~=NK- z9P^}K&FnLNGX559ka*6Lisw|8ma=xs?$&4`n#kHl|ETA0VH~`T$3g1 z)%yQWdh-AEuY02Y|6H^F#C>PZSHs6iSivf)w^ff1OTVID(XY_m+c+NNUGQyn1@Z~x z6C$o@Wvq>^9I%2FwSdAS4cG_vfqh^fjtnE&o43{ePACA&0LJ;J4tnR3*qi7mU)v7{(YD+Zcvk1&&(S z;O%aM)c>DW!U~@Tp9Y_%>f8sH+hLtgrGt?7n8^X3pE+?*WCS1ccK0zIWxzhLkMNv^ t(@Wfu)!%}ape4kN!fgoqz&@}K?8AF|j(;4D(t?(tCAOBh`G1xA{y#wnNGkvU literal 0 HcmV?d00001 diff --git a/labor_4/res/spi_master/sim/work/_info b/labor_4/res/spi_master/sim/work/_info new file mode 100644 index 0000000..110cef9 --- /dev/null +++ b/labor_4/res/spi_master/sim/work/_info @@ -0,0 +1,24 @@ +m255 +K3 +13 +cModel Technology +Z0 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_4\res\spi_master\sim +vspi_master_tb +!i10b 1 +!s100 WzH7KW]Xga2>VXnFzWQ6=2 +I_fR75FEMWcWvX)jFaDxR9gK~?lL=2 z3+K{EZy?3+V5+JWXM+2-`CNfK??swyc2~{&0y2{GRpeE${7O|P?u6~z>Ujdsyq^M* zmq(N5E#JO4&1MxF!?7#jtKGsu(mU5$MuD^|Y+qW>SAJ&klw&sG)o$NGHt&3Ec?%}R z50T=_5-@u%bze}f*Nak>6nmx>qT?2Q+C@|2Nbv2Aju@ZX0!4uL#S-44?AS4R8<*In6TvWyI^N+Ir@ ztsOHM7zCI&bj+OdK&pE0fm8{u7Z=FQy>??I+n&VagCOy<4IuG}!V&@^xeBL`F)`fm zbP zY;gw5lfd%F!SZt?47hYTh!2}oY7091C?1?>LWQUWZwEH`*L_h_Q}O9F?# zpyDL?OW`ln{V5>#6|>0&6b&4Q|dos>z<w7OEV+mDm3@zbL#Fm(I%YV6WnlNTp>BCcJKZe|VLzXl9+d&hqG-Nn1twuAU;AU+R*uMXmKBlsF1J|}{&3F31h z_*x)7FM_WP;tL@7Iv~CAU;2WuMgt$A@~L$z7T?M2;z$(_(mYU2!d}6 z;)@-AcjfMj-E*tC9=RM>ii)rOBG%&1Gwbami%UWkeY;*Jr;29nez8+@=YEE$7n`jA zd@6Umu4s6uP*I@sb{^kZzNNhpE7g_dE`M)j)6VT`X$=bDF|_(R^LUU^N=X-w_P^XU zfgy~U*R8jRc!y4iQ5Un7ym0yKRHtIOMQwVwOV_XYzd?UfKx4+<^AV0moVj0ruUB+R z)IYOPty+Bh0=`QH&iQALMNL*z&%bvydNQk`?!9N3v+b^^A5D!~z&TN7OPIxGt4VSP zj5&@noxODXVcg~7!+9N-nU-$J6VANMd1c2Xhv=r-+b_;ZziG|i_^8O^!1XWblh3c~ z{;`#7@`~czJsok(5-b~{4yUaFcWcBu&hHcD zcy4j__CqOOxy=_VPl)&J{Qb~;=d3%e%LCn(^51&0>l;tI`<^TZ-(dfwr1V(rXAF)y z%%_`LZhek+&N{#5^>2rtr_Oe+X^-iAw#StFvfu6H7mjTd)a{-BeVKtf-`km=PaJ1X pxyu;)=c})fu!G(DD{Lllsvk49#H3E!Y|Q;A#p#=oH-k6}4* literal 0 HcmV?d00001 diff --git a/labor_4/res/spi_master/sim/work/spi_master_tb/_primary.dbs b/labor_4/res/spi_master/sim/work/spi_master_tb/_primary.dbs new file mode 100644 index 0000000000000000000000000000000000000000..f9cdbd90384a97b8f6a12b118bd6907cbdbc2434 GIT binary patch literal 2317 zcmZ{l4@^~69LLXn_rMc^m->(kg1#rndmsi0g=9(z(%37NObpV9LdGjc16JZ&lWAFv z)m)%BF^M+Upho}3AKR+s^f?=5wPe1TtF@OabG51IW@gy$d++17?z_F;c7FH#?&th| z=XcIMzjKw=35WC#WS%coNT;X1z5NyO#~wkVsHAMv+|-0n<4M6x6w0(IbrUajiV=wd zZmOLWTB5)h-AvHUIG8g?85AzMX;8dW(KRT>sYwx2698&5n~5+Tq>z9nZkskSqbA^{ zQ%s==xalThY65QREK-hP09#0bJ{dQVVq2fP%#6(Xh;X50%4Y1fu14|NJ-VZ zLd+FT>dCZ-DRQwt7>$`BGMyB*ROCYII|7SDW{@%v(#C{%LS!Z>10hKSV>FKucH7uW z>X69!qzo_20}u9cF`5pB4TeZJDZ>l<15X5o$ShJ=(f=f$9UFNG#aLG^Bg?w-7+Kb} zh>>Mo`HU>kf4#YXpW zKuhxXGqNPVl946(az>WqD;QaluOt*B`3GVmTNNQXI6f$98G60R2dQhsf<_jY4q|&q zf5^4yQ*$KEA$?01AyA>RnvoWb9%h8%HF>RLgyJ=!M;OhGM(Y`&u1#Jwj8NAmw1E-o z+Jqiugt|7NT1KdA6RKn6jz*6$S`dvkGD69l0&ZfI9gQAmv@jagGs=lZPcZUCA$3gz zr3){54Wx{3F2sl5PxNf9PW^ge@47kh1;4Fwwk}yv|A~LM>rhA4zOvI>4!bK(bxj6d zY-vqKF6Dit zw%q*jo#v5!JF9oLl()QjED(C$-u}(9Dx5ERyQRawmX9N`rjSNN*?r7z1P$19r)|1ZNat;-IYsx`|aJ!OTYE)+1kHj zOE}}#z^Q|G)?{9Do^Uq?);xQBy#M8*CkuzhZ`4la%)aUI6($_33pSLNzh3sm8|zy| zXqT&}b@AHx;*G!Lm%R0HN6Fax{k_B8+Yemmnm9DMYu45LpFhyD>w--^*_E!i=Tdf$ zS9GSGt{?7R~llU^AZf5E6s)Vger0Gwe%P>Q%AY|033DH4y^^!pgyhHN{vHW2Mm)p#1L7~lkA@$Kv!{pcCO;ML zp6=EUJHq-tXDmd%JHc2!%1@NfzU3L=#kq_K10f^g4|$Pitl!*iiT|-FH-x*-kBs-V z3@H|fBgE&vt8{Wp`6OQ@glRHmpFF!br&vb5Abdl|ygcq3P(Atvw(m5(;&;#Hw{zlW z$&zEVl@v!>$T8w^oyduQ!`C;yzU@1kWE0BgX>vpOCA)m->vg`zb%Vaz_-fntdNJeu z_Iq`CZ&rS2kDlr4*?pH^Z(h!?y7~M3;JmKs>)L&%>0(OxtK4@8`?(#S^A&z*er0@= z?Xyg}yUTta?wjv47BZxJ{*NENbDkIP&0(Lln0(j!iWNEv&8Tq9D3l zch#tBp(^_7n(4+=yF@F;Dp!gqP|7q=tZ=Ok%4=AmsS^(9u);5U4;9p`2qRX6F)N}N z6&3d0GZ|4A2i&ea4#BUT1L-w@O+Zx;Y0xDU1=Ix&<#p*J6w$9#98GrvbUTP?!wn4p T&ky8xIuO!|TlzQtI~L*}#1cyD literal 0 HcmV?d00001 diff --git a/labor_4/res/spi_master/sim/work/spi_master_tb/verilog.psm b/labor_4/res/spi_master/sim/work/spi_master_tb/verilog.psm new file mode 100644 index 0000000000000000000000000000000000000000..268fe0f0281a0c766ba55d31874b0525256899cb GIT binary patch literal 19464 zcmcIsU5s7VRla9te0=RD?HPO8nAWt@jG;EPbgq9A2U0rzna0MB?RdtiU0TLTZHOU1 zZsOK11UiLKSu~X_)JPV}Ly#iXEs^j84@N4|JVe3>BrL&$9|}Z>LV(g12*p6?@O^84 zYkSYR=gc|RF7x2!wf0`$T5GSp*V^aYJF|6U%T(4``Emz8L!jTzJDp+B4}l+%e1&KZ zx*qaXpzi=(4f+Mpw}`((^iI*Yf_@O=Zv%a5sM9Gx_pRu3MnQiYbdBg*(9f^xbjCn2 zz4La_cZl94x(@XFi;Ii!@ON*B{-@~oME^td4bguW{WsBn75%R0e~W%c^xLBUBKj@S ze-`~G(SH5lN|FhVQavyivZ>Mu+82E>$XQpXq_Q|~x}9^F z-^R|a{Rek3o_%xMCQ0XDkks*=I=)l4bFrlz`p@-W4a#-$xRLfn#?{rhQ*3*izp_N# zzSE|0pXYSf{(ZKtyZ1i4mvQc%K732->~?R!zc%YUvwz3Kv^PB$_R;?7UAB+fuD9D8 z$HKL-SGUe6H@2?jb!I-8AE&-vPF?QQ<#lxTj@ccypY~55AbntV&n>O9`#BH8ZQ_3L z;BGsoZP(TDFSW#UUVJ}aZE5E%$Vb&V88788n-6(=kK|6vd2zYZ@_3m) zTodOH!4CZzK^#WGr*-xYaNI}Z*l5fb_Z!bQrsJod*2U?0aq4mUIdEF`+vQHn<7Iwk z=E=%^*%arUh=y^VYZ>PZ3Xh!!)z>Ecw+jDaOZ*29&R9M3ecu-UN=y8mM`n)QivQPJ z;y<`|=HRX1-)M? zIt0htoUfT<2duxt>f7)2h_&P`=&EJ!~1UkJ`U?%&Nrr; ze-o#kIL&-Ke(IB_NY8xWtkI`WPTXtz5R~?~57|$e_Q%7@$ER?>s`fwgnD(1x?B65% z_qhEw=irF!zj*uhx5@stLF~`U{?*&Jzg70P4q~6rFFX%#+`j!SvcF{z`-f$J9M8$O zng7kQzj+Y*56S-i+qd77{oWw<56S+y+qZAed!3ULlY`hlDElwBwSRVEBjb$s=1mjZ z$=}nN*v@(~q4Byphc>l|^Cz}%vwG$8E9#~0ahoPMfBV+X1nZj5uYVrV{4Go8d*8Te zfAbRiH=oa?-&?9*@m#GqCYR!r-z#hib@9H=#J#pYk4)G;o$O3(HvUxLH;YF)tbg1K>e`%d{oX?+C{`9|J3GZUWAC z!2*!y1dapND9Au`T=T#4)sZpcxc=XmpKDihofj9oJ;^hk6WXp=E@%3Y0Jn`m1iFXDx#akyH#O68PjUY$Qf*g3*mWCJZ(?j{o z;EBfoQoM2TAWQJx4Dz1g0FTe>@GHh|>j8hmd#s_niw#5kXMK_(ezAzUiu55#G4ckvczA$?;xJ}2|Vqe=&$j>=Q$z%1>rv@yglN#iw9YP z&-jRMIKa1a1iZIt-eu{Zm%igoi3eGNcZcu{$MKT&wRHu4xNi^T*M$GP@aCY1x@GmL zYJCgg8xHUlcU%wK7r@e=*vTNh3vY6*}l6yWTg=6}#ueucN+r9zrI^mv|{>7Sj z@DPJ_?)FR%c$P=#Yyaf0NdL<<`rD;%de9GjxX8bV1Ic|!+%xEd#7p}iwgcm~{WO9; zSfzIwddy3zXLS#H%wGY$SLNS(!v4zN8P4D8Kdq7fd5!!pB)=}|I0bNd{>t+8l22*B z`Fvd3ZGKsfhgOsOx%K(D)SJBQ|A%ViJ8R^;kkHSvUA#Q4w2KcHD(&KBSEc+DlKXyi z{~xQF@A=$=Jkc*^k^8(YeV6j+IP1l8KOM)uVE)s6L16ADp34o`7aXO%KSn;e51lX5 z&uO3X^R(2zKan2an?N4Vm-RuM52zXbbBg~O__SVmp8eeZrHyxcrjK)Sq=ajA8Mx}_ z`DNi=E#XdSzd7!8;hH{hXG^$NUx2Ii$-g1oR~vA@Azaf3?o0{S>I-mn9`i2#!#sbz zgzM+V{e4ZirVrf1C0y&Pz=fN(zFUQR#q@6WsWR^03D@+2`%nqjo*#gVv>NVl;r>Ah z*Za)t!ZSVK9V+4BvCi&sNQdD)FTBg9chgVD`%YAr7 zc&~s@_m$&)*W}%v=>aeBMeg-5*ei0cgCU+G_xcystH{0Xy(T+e??V2I-0R$RjeC6y z`?<)yuC2E|P~=|ELZ2*huVbNa7x_*kmir{!D~jCfR=B?ux!0@Er;FU{ROnMh?)543 z!6Ns%6#7t+dp&}?A(({p z#qLAM(_PZH&o425oO+P^d2=ef{7b4UhcJ(Q*YuFTYsMG3>%X9R&xd*WXJp54a6eF8 zihjLYA~+;jqmsS*)T8qZ8-2- zbv63seox2`eNQNk---WmfBC)C{obJYUN@+auDkG}-yaYD^h^(af8F>ZKG*wtKNsdj zzYPa|t8PcX-0vTuU97jh*A&M$$Zua)_xndRzs_&rMZb>+e|n||zrB9DzWaSX%!_^- z4*XVMh<>@>?~@<;9#$ORivMxFy??sj8#UkSy!7+G()l_eKW!fTJX7+==EEQLlW5QV z*(7{@A1sdVl0OtMzwXbEY5rxiQ{>W*{yb*#ZqMeyA2tX+NBa4<`S6GJgSa3@-Jc&P zkG$%8X>t6c@(0Ihi9hex{8vEPXQUtfdEDgPp3Q?lrvo4TvH9>v{VdvZe?B05eLpUa zpOQbmAAEg&Li1lVJ4G)2=+A{1W3KH=i5D$37jte>BwhevtK(b>*vyuSstmCh)xS+zz5QF1?F2dS2Ju&jrn6 z-J-o41L{pmkN2`FKamE@tJ~Y7dE2EoKcL=}^e)xtd7pH9<@ab;OM1*B_lNBZ><@kq zb~M=^#zW5gTNiT9X8svB_RZaUKrxc_#P1h>$Y^2jGqLY;8wdTY>I8=Qv&L|N&wEyi zzZrwX*ZO8##BT+qy;-A0Zu5X^;}!UZ3w+*(QheeNUwO~AiD!K#{!!uEJmA`R1-{_| zpZAs&{~qBf&)L1=?-zc!j}*Dh1Fnr%;2SRRdA~^UiA(>dKab~oNo40;@68mVYJ9?9&l|O^!JnVjVWsk7x?V!DL&VM_~VAt z&G@}`@*BiIX0*s{9&l~E0^e|f&pw^v|FrP9VYxmZ7C$CF^y4D8dBC;t3Vg!_KKpKp zPaK?sv#KZA1;Z^+Jxv~Ic|8mVchp)|PJ9CKyzL-Go%YXNzNU4S zoX6|tyj2;#TM~Ge?<5a>@%isbU-;4AbC`fgBR?+Q?HUf&$@w>Jyg%+c;Q;%Fy+=sm z*oFC3aY!CMcf<_iE8^HKeGtZ58^>vkr*UW>M86FuiQ^5MUmu6PZ%E>prhTlZ*H_Pn z4PjA$MYCZ<50cL-LByv4(G$?BK2|b{HFWr0rH4r0hImApyw7YdDC*`5QJ~AIIIn-dP%E|M2HB{XSLx zMb&={^Jk6ZqpsJ5ka`c1R>UuPjNkZ*`0f2ei}+8&P8xq9-s3f#B>tv)JrVqm@n1kk zw7*Vk8v1Z5eFZ{+tihL%uCPJr1%9;`fWH#98LYo-lrvX z{%3(hKfK<09FoWSV0=X!AD2GJviWH0SB8T)+>fSyW$)XPI6hGmhvYF1<16C$xt4J> z^((_k;%Mqu_TCP0c%Aq6VfsDUzB(uQsOx#1o0I=uZ#|Ea$Ngx0Mf}HG#^2QE3ui(m3l*Yo%vsfl0mn1ACd;(zo96u;pN5I@f|?<=1F%j$Fbz39I9 zB_Fl-CCUE(r2O}~?D?0xcL@iO_W|Q8;y=+c{-*w5IEdf z#+U04hLgn6)F149Ruac4+OOyjlE*lVuZZIpr4O=f98LYfa1ck^{$TIpk~n^;CJxEN z_goRF@fC4A-ZGB!n3v{bO1%4RI7u8${oy{^MI2rqyg%sgCG^z?$wyt!>*Eu|K_0y> zdwq~R=F#|y_@9(M$g+8C>JNs4_}!1D{$TGXE8^GRiRg=8@=@3G_@AnYU-H-=jIW5F z_j|72?Z$671H^xSSnrts1@#C0eT=^NB_I8;^t`TqO8$FY_WVm8`-AZn@joqnkY)4V z)E^87@w*>Q{b4HDi}&tl$XC==$zy*oz9J6p&o+5%>JNs4I2M4{ra$bU-J~9UntVkZ zlK1?)8($H}XQU6ZY(C~Op4OxC^Mm0eaWwUZoxxtr$64}-!|R*xE6L-zGQJ{?bJ7P{ zHjbwLU^s}w{peTI4#$TX%`Tqcsg&y7j literal 0 HcmV?d00001 diff --git a/labor_4/res/spi_master/src/spi_master.v b/labor_4/res/spi_master/src/spi_master.v new file mode 100644 index 0000000..68f72f8 --- /dev/null +++ b/labor_4/res/spi_master/src/spi_master.v @@ -0,0 +1,203 @@ +// module spi_master +// Author: M. Walz + +module spi_master( + //module inputs + // --- Definition of control inputs --- + input wire RESETn, + input wire CLK, + input wire [7:0] CLK_DIVIDER, + input wire [7:0] SLAVE_SELECT, + input wire [1:0] DATA_LENGTH, + input wire [1:0] MODE, + input wire MISO, + input wire [31:0] TX, + input wire RUN, + //module outputs + output reg [31:0] RX, + output SCLK, + output reg MOSI, + output reg [7:0] SSn, + output reg BUSY, + // module test outputs + output wire SYNC_TEST, + output wire [2:0] STATE_TEST, + output wire ENA_TEST + ); + + + + +// --- Definition of internal varibles --- + reg [31:0]TX_SR, RX_SR; + reg [7:0] CLK_DIVIDER_REG; + reg [5:0] CYCLE_CTR; + reg [2:0] STATE; + reg ENA; // Enables operation of SCLK generator + reg T1, Q1; // Used for SLCK generation + wire CPOL, CPHA; // SPI Mode + wire SYNC; // SYNC Signal + +// --- Implementation --- + +// assignments of test signals + assign STATE_TEST = STATE; + assign ENA_TEST = ENA; + assign SYNC_TEST = SYNC; + +// assignments MODE to control wires + assign CPOL = MODE [1]; + assign CPHA = MODE [0]; + +// Clockdivider for generation of SYNC signal + +always @ (posedge CLK or negedge RESETn) begin +end + +//Definition der States +parameter STATE_WAIT = 3'h0; +parameter STATE_INIT = 3'h1; +parameter STATE_SHIFT = 3'h2; +parameter STATE_LATCH = 3'h3; +parameter STATE_CLEAR = 3'h4; + +reg [2:0] NEXT_STATE; + +// SPI-interface control logic + +//Bei jedem Takt wird der State auf den nächsten State gesetzt, wenn ein Reset anliegt wird der State 'Wait' vorgegeben. +always @(posedge CLK) begin + if(reset) begin + STATE = STATE_WAIT; + end + else begin + STATE = NEXT_STATE; + end +end + +always @ (posedge CLK or negedge RESETn) begin + if (~RESETn) begin + NEXT_STATE = STATE_WAIT; + TX_SR[31:0] = 32'h0; + RX_SR[31:0] <= 32'h0; + CYCLE_CTR[5:0] <= 5'h0; + SSn[7:0] <= 8'hFF; + ENA <= 1'b0; + MOSI <= 1'b0; + RX <= 32'b0; + BUSY <= 1'b0; + end + else case (STATE) + STATE_WAIT: + if (RUN == 1'b1) begin + NEXT_STATE <= STATE_INIT; + end + else begin + NEXT_STATE <= STATE_WAIT; + end + + STATE_INIT: + if (SYNC == 1'b1) begin + NEXT_STATE <= STATE_SHIFT; + if(CPHA) begin + SSn [7:0] <= (~SLAVE_SELECT); + end + ENA <= 1'b1; + case (DATA_LENGTH[1:0]) begin + 2'h0: + CYCLE_CTR[5:0] <= 6'h8; + TX_SR[31:24] <= TX[7:0]; + end + endcase + end + else begin + NEXT_STATE <= STATE_INIT; + end + + STATE_SHIFT: + if (SYNC == 1'b1) begin + NEXT_STATE <= STATE_LATCH; + end + else begin + NEXT_STATE <= STATE_SHIFT; + end + + STATE_LATCH: + if (SYNC == 1'b1 && CYCLE_CTR != 6'h0) begin + NEXT_STATE <= STATE_SHIFT; + end + else if (SYNC == 1'b1 && CYCLE_CTR == 6'h0) begin + NEXT_STATE <= STATE_CLEAR; + end + else begin + NEXT_STATE <= STATE_LATCH; + end + + STATE_CLEAR: + if (SYNC == 1'b1) begin + NEXT_STATE <= STATE_WAIT; + end + else begin + NEXT_STATE <= STATE_CLEAR; + end + + default: NEXT_STATE <= STATE_WAIT; + + // When transfering data from RX to RX_SR, ignore previously received bytes + case (DATA_LENGTH[1:0]) + 2'h0 : RX[31:0] <= {24'h0, RX_SR[ 7:0]}; // 1 Byte received + 2'h1 : RX[31:0] <= {16'h0, RX_SR[15:0]}; // 2 Bytes received // 2 Bytes received + 2'h2 : RX[31:0] <= {8'h0, RX_SR[23:0]}; // 2 Bytes received// 3 Bytes received + 2'h3 : RX_SR[ 31:0]; // 4 Bytes received + endcase + + endcase +end + +always @(STATE) begin + case (STATE) + STATE_WAIT: + + STATE_INIT: + + STATE_SHIFT: + CYCLE_CTR <= CYCLE_CTR - 1; + + STATE_LATCH: + + STATE_CLEAR: + + default: + endcase +end + +// SPI SCLK generation + +//SCLK_X Variablen +reg SCLK_0; +reg SCLK_1; +reg SCLK_2; +reg SCLK_3; + +//D-FlipFlops +always @(posedge CLK or negedge RESETn) begin + if(~RESETn) begin + T1 <= 1'b0; + Q1 <= 1'b0; + end + else if (SYNC) begin + T1 <= ENA && ~T1; + Q1 <= T1; + end +end + +//EXOR +always @(*) begin + SCLK_1 = CPHA && T1; + SCLK_0 = Q1 && ~CPHA; + SCLK_2 = SCLK_0 || SCLK_1; + SCLK_3 = SCLK_2 ^ CPOL; + SCLK = SCLK_3; +end + +endmodule diff --git a/labor_4/res/spi_master/src/spi_master_template.v b/labor_4/res/spi_master/src/spi_master_template.v deleted file mode 100644 index 0c86962..0000000 --- a/labor_4/res/spi_master/src/spi_master_template.v +++ /dev/null @@ -1,86 +0,0 @@ -// module spi_master -// Author: M. Walz - -module spi_master( - //module inputs - // --- Definition of control inputs --- - input wire RESETn, - input wire CLK, - input wire [7:0] CLK_DIVIDER, - input wire [7:0] SLAVE_SELECT, - input wire [1:0] DATA_LENGTH, - input wire [1:0] MODE, - input wire MISO, - input wire [31:0] TX, - input wire RUN, - //module outputs - output reg [31:0] RX, - output SCLK, - output reg MOSI, - output reg [7:0] SSn, - output reg BUSY, - // module test outputs - output wire SYNC_TEST, - output wire [2:0] STATE_TEST, - output wire ENA_TEST - ); - - - - -// --- Definition of internal varibles --- - reg [31:0]TX_SR, RX_SR; - reg [7:0] CLK_DIVIDER_REG; - reg [5:0] CYCLE_CTR; - reg [2:0] STATE; - reg ENA; // Enables operation of SCLK generator - reg T1, Q1; // Used for SLCK generation - wire CPOL, CPHA; // SPI Mode - wire SYNC; // SYNC Signal - -// --- Implementation --- - -// assignments of test signals - assign STATE_TEST = STATE; - assign ENA_TEST = ENA; - assign SYNC_TEST = SYNC; - -// assignments MODE to control wires - assign CPOL = MODE [1]; - assign CPHA = MODE [0]; - -// Clockdivider for generation of SYNC signal - -always @ (posedge CLK or negedge RESETn) begin -end - -// SPI-interface control logic - -always @ (posedge CLK or negedge RESETn) begin - if (~RESETn) begin - end - else case (STATE) - // STATE: Wait - - // STATE: Initialize - - // STATE: Shift - - // STATE: Latch - - // STATE: - - // When transfering data from RX to RX_SR, ignore previously received bytes - case (DATA_LENGTH[1:0]) - 2'h0 : RX[31:0] <= {24'h0, RX_SR[ 7:0]}; // 1 Byte received - 2'h1 : // 2 Bytes received - 2'h2 : // 3 Bytes received - 2'h3 : // 4 Bytes received - endcase - - endcase -end - -// SPI SCLK generation - -endmodule diff --git a/labor_4_drive/sim/modelsim.ini b/labor_4_drive/sim/modelsim.ini new file mode 100644 index 0000000..b0f61a8 --- /dev/null +++ b/labor_4_drive/sim/modelsim.ini @@ -0,0 +1,324 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both diff --git a/labor_4_drive/sim/sim.do b/labor_4_drive/sim/sim.do new file mode 100644 index 0000000..2491ad7 --- /dev/null +++ b/labor_4_drive/sim/sim.do @@ -0,0 +1,19 @@ +#remove working directory +file delete -force work + +#Creating the work lib +vlib work +vmap work work + + +#Top level testbench +vlog spi_master_tb.v \ + ../src/spi_master.v + +#Simulate +vsim -c -t ps spi_master_tb + +#get wave +do wave.do + +run 25 us \ No newline at end of file diff --git a/labor_4_drive/sim/spi_master_tb.v b/labor_4_drive/sim/spi_master_tb.v new file mode 100644 index 0000000..172ebdf --- /dev/null +++ b/labor_4_drive/sim/spi_master_tb.v @@ -0,0 +1,96 @@ +`timescale 1ns/1ps + +module spi_master_tb; +// top level testbench, no inputs or outputs + + reg RESETn_TB, RUN_TB, CLOCK_50_TB; + reg [7:0] CLK_DIVIDER_TB, SLAVE_SELECT_TB; + reg [1:0] DATA_LENGTH_TB, MODE_TB; + reg [31:0] TX_TB; + +//DUT module outputs + wire [31:0] RX_TB; + wire [7:0] SSn_TB; + wire SCLK_TB, MOSI_TB, BUSY_TB, MISO_TB; + +//DUT test signals + wire [2:0] STATE_TEST_TB; + wire SYNC_TEST_TB, ENA_TEST_TB; + + assign MISO_TB = 1'b0; + + initial begin + // Reset + CLOCK_50_TB <= 1'b0; + RESETn_TB <= 1'b1; + + TX_TB <= 32'h0; + CLK_DIVIDER_TB <= 8'h0; + SLAVE_SELECT_TB <= 8'h0; + DATA_LENGTH_TB <= 2'b00; + MODE_TB <= 2'b00; + RUN_TB <= 1'b0; + + #20 RESETn_TB <= 1'b0; + #80 RESETn_TB <= 1'b1; + + // spi_master setup: 8 Bit Daten, Mode 0 + + TX_TB <= 32'h000000AA; + CLK_DIVIDER_TB <= 8'h1; + SLAVE_SELECT_TB <= 8'h1; + DATA_LENGTH_TB <= 2'b00; + MODE_TB <= 2'b00; + + #100 RUN_TB <= 1'b1; + #100 RUN_TB <= 1'b0; + + #5000 + + // spi_master setup: 16 Bit Daten, Mode 3 + TX_TB <= 32'h000084A8; + CLK_DIVIDER_TB <= 8'h4; + SLAVE_SELECT_TB <= 8'h1; + DATA_LENGTH_TB <= 2'b01; + MODE_TB <= 2'b11; + + #100 RUN_TB <= 1'b1; + #100 RUN_TB <= 1'b0; + + #7000 + + // spi_master setup: 8 Bit Daten, Mode 2 + TX_TB <= 32'h000084A8; + CLK_DIVIDER_TB <= 8'h4; + SLAVE_SELECT_TB <= 8'h2; + DATA_LENGTH_TB <= 2'b00; + MODE_TB <= 2'b10; + + #100 RUN_TB <= 1'b1; + #100 RUN_TB <= 1'b0; + + end + + always begin + #10 CLOCK_50_TB <= ~CLOCK_50_TB; + end + + spi_master spi_master_test( + .RESETn(RESETn_TB), + .CLK(CLOCK_50_TB), + .RUN(RUN_TB), + .MODE(MODE_TB), + .DATA_LENGTH(DATA_LENGTH_TB), + .CLK_DIVIDER(CLK_DIVIDER_TB), + .SLAVE_SELECT(SLAVE_SELECT_TB), + .TX(TX_TB), + .SCLK(SCLK_TB), + .MISO(MISO_TB), + .MOSI(MOSI_TB), + .SSn(SSn_TB), + .RX(RX_TB), + .BUSY(BUSY_TB), + .SYNC_TEST(SYNC_TEST_TB), + .STATE_TEST(STATE_TEST_TB), + .ENA_TEST(ENA_TEST_TB)); +endmodule \ No newline at end of file diff --git a/labor_4_drive/sim/vsim.wlf b/labor_4_drive/sim/vsim.wlf new file mode 100644 index 0000000000000000000000000000000000000000..dfabca40ca3f82c9bf8e509bbc008389e3bbece0 GIT binary patch literal 40960 zcmeI)PfQe790%~aILrv43+H>R8q}LuylhRpjo5pL6r|&QMy_q+E z-kW@qIsN8M{VZLe9wJhmB=+w4L1&{lsXJMT0VgZ{N;DDqzIKnDEtigm(#x~q@qF3k}0 zF!En#s^VthK_-br*c=pLg|}T{ETy<)_?@?S*vHu@v(=lL46jMMW7|cF%03Z{6knW0 z=;~HR^ssX@ZxEZ}!NF&r7_cAKU5ZRR5VIf3gqR-@;x%3PB~L#3T_g=nCfx@f>xbpp z>BcphaDv&+qah#w0SG_<0uX=z1Rwwb2tWV=5P$##AOHafKmY;|fB*y_009U<00Izr zPT-#v{j|NU9(UH`JNdN!&z$xC;#_%d;WP~}=a?8!s5h0IDb26gv|O4=^hV=lT1w0; zEY8~Vj9QDOvOPnqb7y*cO7n}Fy)dKnMQu874=AF0X^}6lkUS9IM~C7Ail@80LbHo! zS5D5&+uE7Z0)^u#O2#J2_HsE!V-wcUaQae$Vna(yW@)8FvFzfB(tNBy_QFzZ(i)$j z!ffAixpZitPSse9J|Kq4=&9W7fNNiF<4wV9zDnEJG2_%XG*t=uP!bhIW2dx zUwuk5^{E>|6VgX@`*=w6?bNH8U#EQ9N*B%)3%+6ACHJ_PFcepQBG=>!tK?2)$5W%l z{mD2V@v=(_El4lFs*7n(wW;iA(acO<%b4lByv({x^}ZCHBs^AjXfnN4w9?shs=y;T zX8YI^@vY88zpK_9D$r0do6fya7|F=Tp0?WBH7Uo&%`|Vxv12CJ63wpfE^DGN<$2X$ zEo#`*{nROBVsMQGM4oqM*e-R{tfqX3?=?F}wv*f3L!LIOHw;p}yIWew9VX8PYiIB6 zrr>%LH8)c0dXU<8QP)TV#q^jNpuQcX8n2LKSA6y4(Hp&93e-{1@1v~)%B?|nIyc16HyzU1&*2ePzZQ+g%F8EW?a5n4wyhMh%PY#o z&DLC1``cR3=!~?Nj=7cHi}Ro4)FA2w1*64>boGHbv-gLoE-z z>AiE^`@VNd|AOy+IH0F!I+aZqQ-yqnulnv*r5*%zU3WfZx$Q*Nb1x#g5P$##AOHaf zKmY;|fB*y_009U<00Izz00bZa0SG_<0uX=z1pbFWrLO;<`aktM{YqAjannOC+TvBi ziWJ+N@~oK~#seNzWW*&5-y?1*QVwu~ZSYoAYTP*a_ZoeXa&AXJ00Izz00bZa0SG_< z0uX=z1Rwwb2tWV=5P$##AOHafKmY;|fB*y_@R9^7b^d?r|1W7yOalQ3KmY;|fB*y_ u009U<00Izz00bZa0SG_<0uX=z1Rwwb2tWV=5P-mo6;PewD*pg@8h-(|BJ<1u literal 0 HcmV?d00001 diff --git a/labor_4_drive/sim/wave.do b/labor_4_drive/sim/wave.do new file mode 100644 index 0000000..43bd9d7 --- /dev/null +++ b/labor_4_drive/sim/wave.do @@ -0,0 +1,43 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /spi_master_tb/RESETn_TB +add wave -noupdate /spi_master_tb/RUN_TB +add wave -noupdate /spi_master_tb/CLOCK_50_TB +add wave -noupdate -radix unsigned /spi_master_tb/CLK_DIVIDER_TB +add wave -noupdate /spi_master_tb/SLAVE_SELECT_TB +add wave -noupdate /spi_master_tb/DATA_LENGTH_TB +add wave -noupdate -radix unsigned /spi_master_tb/MODE_TB +add wave -noupdate -radix hexadecimal /spi_master_tb/TX_TB +add wave -noupdate -radix hexadecimal /spi_master_tb/RX_TB +add wave -noupdate -divider {SPI Interface} +add wave -noupdate /spi_master_tb/SSn_TB +add wave -noupdate /spi_master_tb/SCLK_TB +add wave -noupdate /spi_master_tb/MOSI_TB +add wave -noupdate /spi_master_tb/BUSY_TB +add wave -noupdate /spi_master_tb/MISO_TB +add wave -noupdate -divider {SPI Master intern} +add wave -noupdate /spi_master_tb/SYNC_TEST_TB +add wave -noupdate -radix unsigned -childformat {{{/spi_master_tb/STATE_TEST_TB[2]} -radix unsigned} {{/spi_master_tb/STATE_TEST_TB[1]} -radix unsigned} {{/spi_master_tb/STATE_TEST_TB[0]} -radix unsigned}} -subitemconfig {{/spi_master_tb/STATE_TEST_TB[2]} {-height 15 -radix unsigned} {/spi_master_tb/STATE_TEST_TB[1]} {-height 15 -radix unsigned} {/spi_master_tb/STATE_TEST_TB[0]} {-height 15 -radix unsigned}} /spi_master_tb/STATE_TEST_TB +add wave -noupdate /spi_master_tb/ENA_TEST_TB +add wave -noupdate /spi_master_tb/spi_master_test/BUSY +add wave -noupdate -radix hexadecimal /spi_master_tb/spi_master_test/TX_SR +add wave -noupdate -radix hexadecimal /spi_master_tb/spi_master_test/RX_SR +add wave -noupdate -radix unsigned /spi_master_tb/spi_master_test/CYCLE_CTR +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {24527614 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 232 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {26250 ns} diff --git a/labor_4_drive/sim/work/_info b/labor_4_drive/sim/work/_info new file mode 100644 index 0000000..44e8f7f --- /dev/null +++ b/labor_4_drive/sim/work/_info @@ -0,0 +1,43 @@ +m255 +K3 +13 +cModel Technology +Z0 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_4_drive\sim +vspi_master +!i10b 1 +!s100 eeKKVXnFzWQ6=2 +I_fR75FEdKM^V8k~m4G zjS@nXnjs;Y$|=`I*+_2N?&8e*mEWnet8?a$@BL;yYdz0e>;2aIB7(Tmy#-B*q30e8 zpX~JtH_-Q9+hQC~AVW4l;5WPz(btINFc8A`z$B3cwOn)XO3OxtD4Jy>psU7bLPb&h zpc^P_5vafq(G|@RquLV75e&1l5LuiWN_>fUVpi$0Z`U1hVO&fST~4?_O%$&^5(B5I z~UzMOtqQ6~;QP zMyBhT;C;jSN!FrJMcJ^eJ{x4^XOVLPc)Lq!NMhX8YV5Gg%qjI)*Seb*LO>FduU&cp zK2WA%jyrt4XdnJzO3_CvQK9L6+7l%h+Mux?fB0R|U-*HPmX8S_hx^k1fe4?V?rx== ztYd10PK6E12e*GuBz{=C$-psU?mlnxbNCpy0+@;;FS1^UQMkQBX>*F-6raYH56B(MZKT zu)or$o76ijPh8M3AhKBbyp^8C`gD-3bVd`YgYiKL1;xY$ikV7Ty)VJu@BEqrFYA)&ijr3;qTNkmzyn!X** zKC_Vu@K7g!57v{0cCa%&G@IzS)B+S!Vr>RR-;;hmJ&2rac`#REMEsOA@K#g>-fFs} zeFxZ&J=jf_xYSyd2aY^#G7JjvYz3X{$R(GGDI+i#7qxsRdU0tS5<11)$Wdc3=L*y9 zaa!lBO#oNCKj1>Nkw^`w2+Q{eP~uR=piNU)bQ>aER=f^9Nfvbw)5y^`j`C}5`>*l{ zpga*_IAaKA)zx_>U;*azRZ&e+u5+)?z0^a>|((G zYr7n#lTsI=VGyS!w#X^FJOv7x2WH}^&edGE+`a687}@@|vSH7xgq z-W>Le`$%Y=Gl0CV0jN2Q%z3WM@jhHKVaiprxHM!lnto4RF7G$zS;Iw1x8{YkKd?%V zM1B_qMY1G8(p?Za-H7Ek(pH$dMS^HYzHNOm+D{>0XPecE-bVAIz>%}0{ZY6;(9(mC zf@$772s=Lo^wxBcm}N6|ZKbL9c!hJuCZN|Wc;mb7YNp>}9pVcx6Yq`w1ar-tc_qLK z*XZ_%vvxz<;ro0g0FW;PWQ2eJmw?uH1+>2*0KS?p1Tg=H0QI{9I-dpVKkR?C zYHsjSr)M&Uz#xtP{OGiNF~&|0H2;b-=mxWhoF2*&@Ogy#i=K3_;T`Fq)(m4Uv^}eM z!7ZmsHIhE_epVdHUIMVj2LPLmX>o>idEUoML{0H(7UDxPqv%%!}nrs=c+tZchToFc{nYrY0-T%Si!%avqjG`3z&S+m*=yDl+7 zRz+y15ou<^1tP|zAl((D>ImF*PdqDcV*;)>u;#d!>m>=lz;3y;Pq&O;O1DojDCy1) zP*ThZQrITjBNOlW@A37#{qgu=T2(NBJp};n=qHyZE8|dQ2*A3d+OMZh~Qa3 zS~DKgr_v~eVAy1_Y1AP7X}tZz#zKHNTRl3Nq=42X==xjq!EzO_oQ*E}3d@mSrd03Y z*$i^-hz2=l$dk|tEcN9<-}ZtKmnu&Hae5{ojv1kq-o`qjSQU{A8% zJ_U2zRr4x9xIocQbE^{%xIJqu0vw^1z<2O0c^X-vAY)6ovla;-2Qqyy$1ReKjqfS! zNxiqbz-a!ML+c9;Q2*aK!1Vo?gZi1HUL9*0(e`J-i1FQ@a|Sn09K789TV+h30arU; z!UzG;DNBsi=fu}7MvB+*CeMh{#5BzGk4H(iiVsPBb@3{Ln+Y^<`DTJIUcQ40xS8P1 zaQ|X6z=uFQL><)cQTz2wtd55B_G;xkXXk5%p~_pIj1?(Ogk+EEK2Wi*sM@LQP$94# zuHtyx@L$y#9TkB(57u>}8Rc`%H#yS5Dw`e$R5&w;`DHY_=OuStmCKV2QAC@K?O_cQ zxm;DrlD*sP<55sr#xKMy=U5~=YohEgWgo} zF}8Zs{NDJL@3yRF`VTM{b9W0i%^$nkW-xQ$gF3cp^Ih7Nf3*5LQD`NRF%;q^F_TEH z_OpH5L^}`K6%`D{#io47U$Rxg$+YHm{Od7?;uW<|r)CK^w{K<6I2w)hsA&42P*t9R z8{Q%}4C3s#^4uPCWw41}R*30wJ(87!St7B1CJ(?o?+XSS%? z={>9>W*;Sk-YaTKSVhu&gf*P|Jeo{cL#v?4gf*OW7I2kJSVPV8REozIur^{u(+Gy7 z5CdjouV@aefP#dPMTk#jvVdob$M#`^*N&!<>k9E>Hd2n}z{+)nkww^>%3|TVLY|Qz zZ5>9gD@2seU0lJ+b%l{dNQ9ct!gYmg;8A$KMy@Lq74{w8y8|oN6-Jg`N9FL)b%jjA z6>1YrqbROm<+{Siq72AfJtTf5bAT6lDh07u1R74YS`r=QMMZW#BlcU!!i_jGSsLl^ zRpgQmtZ-CH$GG*r;y(g7EvGAS{oQEe=-+!eeYetR5C*Y%JMUauhDnUjLs|6Xa z@;O09Mb!v0BCHi;?CW_!Muhc(jI|mB8CJUl83pi)Aj4{}AR`;E3o_E%D9CX5CL?{` zgGS9aMMuriQA<>0zs-nG^E(jS(7an8G7`=jBV>CJ5gIARQ|Ist!ShRi~gx zEBg>5HtuF&V-%0O9(Rc>353r+sYqjOr9TJ?pP~PJ=V65xLdu8+2rJP4TcKn~MczRU ztbl@qkwsZ7?H(3hbTt0{iy8ehHs+rH=+;>FoM}U^b@n?O=MVgldpNdyVO#5luEnL> zCVs2jvqV)jUV8b}>Vm}1Z+GX04ytd!eVV>+zdkwojg`ztQqU`(NXQXU5Ck+df`%a&}79@OPt! zw{H4$=h+*JGp8TzX#Mp_bxZp3nyZCF-!yzy)t%K`G5(sqSZa(Q0rIugW6+wWj{@w{&2HsF)w(K&V*nCdp>SZMZ~n ujBG2%yX-iKlF*0eiEwrfaaT({6269raE?&=9EHd5Khli?MTBlAEdLv1ZTMUO literal 0 HcmV?d00001 diff --git a/labor_4_drive/sim/work/spi_master/_primary.vhd b/labor_4_drive/sim/work/spi_master/_primary.vhd new file mode 100644 index 0000000..b145e7b --- /dev/null +++ b/labor_4_drive/sim/work/spi_master/_primary.vhd @@ -0,0 +1,23 @@ +library verilog; +use verilog.vl_types.all; +entity spi_master is + port( + RESETn : in vl_logic; + CLK : in vl_logic; + CLK_DIVIDER : in vl_logic_vector(7 downto 0); + SLAVE_SELECT : in vl_logic_vector(7 downto 0); + DATA_LENGTH : in vl_logic_vector(1 downto 0); + MODE : in vl_logic_vector(1 downto 0); + MISO : in vl_logic; + TX : in vl_logic_vector(31 downto 0); + RUN : in vl_logic; + RX : out vl_logic_vector(31 downto 0); + SCLK : out vl_logic; + MOSI : out vl_logic; + SSn : out vl_logic_vector(7 downto 0); + BUSY : out vl_logic; + SYNC_TEST : out vl_logic; + STATE_TEST : out vl_logic_vector(2 downto 0); + ENA_TEST : out vl_logic + ); +end spi_master; diff --git a/labor_4_drive/sim/work/spi_master/verilog.prw b/labor_4_drive/sim/work/spi_master/verilog.prw new file mode 100644 index 0000000000000000000000000000000000000000..9842fcbdd520ad186af8799471e938e6c7a394c2 GIT binary patch literal 1385 zcmZux+iu!G5M6ROV7dcEfI<{B$OA&}Zm8ibGw21|Wt6g9jde@6bGAJNb2 znb}2mR1>?|U>FyA}s<8Ot}8StW`)H(1H@h9Ln;AhWw)aC2T^N;F6eR%!3 zdf72^3a*d5h-0m~5y!W)k@TT}oR{9sCgKD1bwnR}eR_AD zIQ}{j{@MB213$TuzVoaQ-}1@bFP+@TJx1e)G3Sr6T;e>t68$^8oTFdMdd$;G|IaQS z_&C3ximsR>53I{7S9g-7eqO1}Ym}7IcQwhTth*|&C9ix`cxTM#v64CEs**X~j*A)V z6p-(k|HG&AROXabu1>B}_rArG_}G{-hnTKdoqzk0;| zg^xX7U{I0|L$RiHu+YO`N$Yyi^Qf)ggvM=H4Ji`V&BEv<)t2hj z!URI&NH&{*upkBNHV1EL#T)3nv2ot@im!&2)(spvZL^|qK$|UX4Q*ql{7K-755s85 zI_YGn%6h< kTT-=^7j60{zls>Is%ZzQL%bal8>f$1-{SvM{W(+WFa2LTNdN!< literal 0 HcmV?d00001 diff --git a/labor_4_drive/sim/work/spi_master/verilog.psm b/labor_4_drive/sim/work/spi_master/verilog.psm new file mode 100644 index 0000000000000000000000000000000000000000..9472b7f6a6cdd1c0014313695bfd5ed44d3fc51e GIT binary patch literal 29216 zcmb_k3z%JHb-ibj+)R+i1)@ZaFisGoM$LtQQG-k#^N55HG6N=vCOkr-B1VW3ElO%_ z8x@sWXrrQyHmy;y#+J6&Vw<+KVoTe!r7dl-(w4TdMMXtLMW<`6f9;b$XYQSQXYBnx zX0!Ld_u8-jb6t&s=YWVbkKCib{n*n+?_?ec^GOdHog?tX^I?!W4uPbV` zCxJc%{IRCTnH~@NY{*Xl{c2CG)&TwTtXl0v(1Cibc9QAIpsS9r)#idiz4m0&r6 z+el}FF694!t{)s7oLQ^iHg;`oa0V!))O#vu59mzPOOylTGddIeV(>p4@4XG>k{#4b zN`3OAE7zQl{?t3-qTJA%bsPKD4KC5C|0Gbx8UB#=IP<{t(0I^dSK?<|9yHI3@rFET zb-c^uDql=1#kU`{n|w#tEWd>KgPT&{)(oy3BVPk8Nb#A0_&fD4 z^181}zr>xa&g?(Ot952SC=Xh#TgZb}$E*CRF0tAN3}oIKyyElN6>0M4f|Qur5~s(f6mix_T^YN zu`dO!#u4(M)$uAnI(n_h;D=r@0sD6P?rH&`r&)r@68Qr*cCH-s~ z8yqDas|}9!cpkE@o%VU&f4F`g?9yMmb99Drs`~?Ag&(w9*N_LTj#v57vE@3?29YrH z9Yws1~;X9*ZSJZv3xy7oG+w8g_Q5R zfm@|UC>24>=z@&BN;RK-4S8>1IAx@B2}&94C*b zU0&6Db=0dJPP;l+@6E?~9!?dfdLNFu=Qw$N+T~TfXGY!I;k3)EdVh?%Pr$i+!C5>P zgqi}#HM=3i9dmmcAlP`_DQu*CY}&kTP10`X@DfBAy5jeoZEw0;K52G6OUT2Ju> z91!E^FKI zdL5MdiW~l;Pj}jGKz5D#I{V*l`4x_1%yGybaqzy9=dZYc%kzzSJ!tz>_eNRgD((j3 z${x7xOBt`?2X6F>c&yh_$2$N&tk>iA7x7+ZT-gJc>oAX3@dKCZgz-|JxM|)s)R$Jc zn~f`b;HLfd$UIP-z)kP5dg?bC_jK7c>Wdw3^!F;`$qsn7EAv;}!0U6IF|W4S&f_T# z=<)fU`P^^68ppia3_0`JV|mo+8sjJr_;)=@|B45=4dXs)`##w<>I;n<`D{0y?10Dn zO_yUc?e75_VpFC5@| zeV6eoAK<6=06q1?#$P16iS^!XJlO%yd6#&KA9%4p#eBcnb{^L`$3CCpcvr!I^GM^E z?~w<7X(D;d_gjpk`2qjD|K{~le!%s*u5Yt_I^QPdbF1-W2RzrI%t!eFFYYJ1jrRcj zvY#>Ecbkv6W4?2}a{dS>;su`jT;Fdz?zcJKEp6~_H=gna-qWC$=dXGKU;8}f<00ce zWW1PPA~<5-9yZ=#``g@+@4nV| z8~?EJM$GSTgTLSS!T~7x3Me z`a$DATEV}o4gLY+3n%IWJnzHx2aWew1@B-RygQAjIs=c-0eL-CAK>epMLnJ{{(RXr z>V3wI{q`>7$u9DTz0QBw&&U68KFqT{`^uu<_>yKSTEh18ufPh&O_xGce>v+%6m^Wk0sXIZolpD)>&_d^J3IK@ZM_?<7yC;)zw8(N#{Hz~cc1any`fQ${k$FCPU9VF zlgB~hrF#O_du9H??5MizGS2;`)%YGXUb-i=@9*Q*OXoSxWuF_72g)VCb8*mc9^Bfd z&itMh*HP$y$?K2%z*6i3+%LEfr2V7&=Ve;uxWUKs@)E`4=RWwywMqI*LD|31uhNJ! z5)#`&Dvwlcu?cj-|Kj}@1PD%*!4A;-uX)(@tn~n9?604@0phI ztZ+PWkBWGnO&sXYcRaQ)5vOp#Kc`KclEbgR2V2HD z;yB}ZAmV(kv-!9wv`*Rcg z#e0yji+kd3+wDSLtXnnCc6PT!oNeslIWhc2etT@^?=?;E7w-wfuKL`~d|Soo=k2l& z)#vG5ZS4FUUD`!G4@7=#>>|FPVRx79{QZ~-`GtPausdiwfA6KV<2>d3*SyF4=ie=y zn9YCjkn?`h3puqpzjglAdTzjDiFob5MbW<>JT!~5C<}$UmO@ zpmLJ@z#s1wxj&!#rN1S{cO8qf&EF|My+yiDH0siWAB}^4Hd|lxCqMAVdqeK;4B}<^ zonw3!fcd@1Jog3i>AujYOAmfD-ol^!z#s1gxj&!JH(+~FJ(n7vl=v@B{0hmjFLGmH zA6}B=LmJQIFHQ3PWuUYtML$+Zp6Q)ydyQxEbl+&yg^xU>*CHR~fqZy>$n){}Ugq;M z#}oOSXTOqXeg~`f%x^G1nD}AI5vTM)CC9lC{o?yM{(cwasE^KR_~QXe|3joW zcVb`rl;^GGJRXne%_+{oG7=y1Ve+syU;ni2jZZ@T`a__|r{q}>^5IuFsB7?h5qbXm z1gHz=IIm;w=kxLW$UM2PEXGgxx#5^ZixE=P(SC~6=5GgOU0T!O;>t6>-{59ss%wLfB33ax-DSP-ApVe77kgv5pi0UxiItyot zb#9=}tOM)p`)^ri?(3{`!=b3!}T?!knJ3lXJ z;pBDYMK$l!D-%B~Ir8U1!+62{4)lWH!K&`BO7gX`3w=;d9Ow^uJlR8@o|77N$x#pK zfmY9B<$-+oJe2R(n~0n3*E+|LU+mY*Qe5TzU~`J2+^;V;&wg+pxFYexk|Vy&py5hCK3!=ak69 z@-h$cE%JD+?Lj8Z<6(^FdF(YGeuaZPg5TF6kLAf`tmWB(W5B9Ciq z4>D;UhcKS!vD19`6%O(UK7Jn%xIyDSvjPI{qp{9kPab*1b5-PFdD#!~E%Lb5_Ti`9 zec=%(JZMKg;ucPp z$BiBGSe5*h{dgmJ&K zd@J5Wiu>Fhpzxdc?A~en;?36EZ@pgfwVtc{KxfuwY<(su?x$P(L9YQ_0E+K>Zap3J z0Z`)1EhbXo&MCI_VVv>lIU&~Zr*5|h-yb1RN%bO^->L$KLpMT2sAk=Gnz8=PS-e=dfycY-ueeU+2!2EjAXZmgR zVSiZPb@<7AqyIOOM?L3)vc7LK-!T97#IKedb(KD-N=w z^tUVVBa#DmoIE1>=_K!814_MjBz|}oDfB#E{7jNhIJYcs$`1PCvwq1Q@^{)EWYT^e z!g$`V>bWHx^sC!*OV3r=y!%Eu=HHe0)smzB(g&5iGM^r6ajzevJ^al{w0L*I>mLB+ zJb91#RXLySXD@)9&kLUaSHBQE_pimE+`qVy#J`|R|-KIXIKP2oddd{!6XLGJq;iRx0A`rq{_ zZ#Fm%4e?oAM5Fvx+naB@&N}r=I8*4C zp5wEA-In4g`}IqSACjDXK*JdCFIzAAwa0prXL=t@@}B*bep%iWKJ>+BbrIeq{qn!Z zG-<#1K9cK>{dzUy$olmm@-5bv){{Kb+neM)4^{eQc~kh%7oXKdc$4(Y|BlwA{o;E~?vL!( z75JI=>tp0w^vm*QU(zqcXK_KS{69_#d-K!omvE-guPc-P@?P|-DUPyV`^-mQel776 zo@*>`${uwVpXDhW$ba4TAk4dMo)2I=-}iZLl8@&Y;ULf8JH3aYKYqARvVT|OXWqY0 zkVpOFJ`nr1<>fs@e3lo{xDNN*-hA75qzijeWyYH4y-SbDSi5-J>x39*TDWc z6FmFzY0~U|e}{RVbBMF}OyXBdj(I74P{}LzvHdOXW7pCi{$?dw{6@kn?|+{)&wZNy z4kUh9a`=%xsO0cha2ydY1wFQfzc-}u(%IYzIfQY}lhE5~KAs;`2W?n?X$$q_&2AM5}5Bp=c^r1iZI<9U6zn~(iOINAQv>Alu<$=?mf zC0hI;DeAa5;T8wYFERf|=5I0o$B7@39C_f^CpWRqe`38`t#^<0B+vBzG|2~q19|l0 z&n%Z+CjVlR4=YZ{We<9<DNBy4o?~{B;D;zAI5lI&%Ng3d0IHAXYie#uiupXmG8m-g?v^| zt^@K>pD!nVSbB(C5kbWUPs~g1X$5(7` zzU@8kFck8-?KdCy9pRvE!FO~2xoR5sp9KsQ=iZI@$vVtTw0MXVb)E~#dH8SU8|ME# z@v9|Ay&obEDtYDpv$;jx-$woHeEpAvSDp);SMYxS@e|HJ%bT)?fALvggadh< z_IO?Z5%qpl_rHT&%40m& zsLxH{^7;5x@-6P;mgC<{k$xdQ%bTFUDgMXy=BGU$g)@cuxGVWD>-N8nBkmFLTw!_B z@fG4*gDU|fcfw%9OMyvr}wnnH%73o*e|Y=ci?B4QpM*&kYc59M9<$A!sx{H=sH;rYVy^7riGTh#g6wg;KC&WA9b&!3&<<9R|jsB`e0 zo-f{={FUqAG4d_m6IfoZ1Mw~L_>S#CCe7o1jOTgmG9U9^IN3Vr^q$~7$zPercgeSy z_m-D=h;Na{_iPU`X&#;Cy>O;5?{7~2%HM-Lp5o{q0OdLJeew_JIl?zXzcn_mB7DC)d%*i55Q~#X7nLl>UF1_#w%$UdFBW zg!OK<-jA#&d8YT{B%g4Pw!A5P=!?(#BD}ysUjZ{|U+%?tKEJk^kLM4?jlKlm>3ajL zE8l0cj;z!B@H4Md4JTz@Cq7VsACjDL!y)$x{=*p5i#qXyrJm%O-pnMQP$$cq!iT>2 ztWLs%e3tDQE&R6Kw>#BII8&?>=GPX^GuG+-$$vSY_y?YOon||K$(4V4U(WBD=XIK6 zJ;^gY{(&>}Ce+FDrtqOJKC6@PAb*nW8SPI}C*e%7PFRmyxDHt-t}o7~-bD4i&Ad*> zRqAnko4hS=@_V1W?~2dz77pYm{6FO_oGIkZY^Ua|Z}F7G4@r*rw12_klq4UJJ>)Te`1g6h z8XMNe;d6H$TY-gadi_dq$EE%MNnsfjWNu`x<;- zEh|0u@Ar7|Jo8bvMTsAhTzRB@`T0pcAbZH?xo$5= z@?qIQErXZ=5<>_{Oo)0ds3d|zVkuzvz-6gDW39s@8_7`fN|cNUgUTsN1W0J zl|1|X$QtOkdhY&^{l)Xf(u6nReS_uY{Z@Ro{{u#KeX;G$x4j=c3WfY0b(i_Lrwa%5 z4gLUdC;L044=4ZSJ^dwZ^02(jLwt)oUfN|Id|t`(I9SO;I9VQdcF5xb*z-Qfe(`*| z9Y1+4MSqs1xXSla=bGob=X`is;#W(Kc_4jI$+PEA`iZ}1#{ZU|kKq64Z+4=^dB%5t zih;zBNDf@E>icr*-3^{`tVsN@^r7eRVx{H5OAq6#Y=6M^gXZrvKV&=0lRoT*lYB^W z@WwAjESDe1ZC|W5j_e?p9_Y)hFZ<93JwM4OtOv`RvJ1Uz9?1{nYiy4+Sf^>P2jOJ% zsMC7*X!2LSx40n1(I0(WYd-pQVVgWHZ^|C|h|lsA4&>{)%(K&a5l)t8r}e_R^27O@ z-{mw?Jl#Jmb{BfCDEJw7(gI@Ipet;rpDKdKsNtTX7im= z#UQ5T7nYLC&fi%X*6*L1%PRgN`G%PrE5odnmmJypHe?mB|GV6^jYBg|enV1e^-H_9D?OC!C36vKn5s#cr{?%U>b1@gQXX|mZ}HSY_^NX}Q0SHbctRh_sKwr{KF2|V+D z3PfHWO`f-W`{Fd4Rcs8$u7t043kON>Tx%Hx(yp+5X+2;0nZ;9%*@RcSeFxdR^R4AA zm=r%miZ4sR?77r^LAhQpZlQguTv5WB?ec677cwyH6J4&kEQkrHzH-@4U$C|rOBF@R z3l_gQc80G@)J$C}UW~IhUg*hFMux?<$(h1`AMQ8=@<4SvNY`H(@e^EkWsk`+GPEj% zxOcX8%wS*;VB*j*bIt>)>b(b2CAeN(AUF5gjg@SB5|a;t#LqT>#3u?%2#Dk=oIb|H zaKn>#&%$I!1+bg|SWX-$r*gxWbI;1;Kn{@j0 z$v3ja87xl%%O3~J&yg_T(v|tn#K;g~$h#*Xd9eae*;yB``)5lDu;jAb;N{$-iRv#2 z9R7leljJXjzfkw5fZSKij_!U5nES!|7YDij0nq)G3X>c=gc%sLJDQys7(yg@ zmoNk~gM71=1>~DRY3T{9x$HN%Irpe0dxB$W0@#Hi2)-tW z&xPP?f%v=#zBY(2fZ*$Z_`(RjE{HFP;Ol|-{0P22h|h=M8-Vyi2)-eRFN)wBf%qZ_ zzA=a|cKF?uyDxUnt>${D&hMJZp&XU=*S z$U9M~r10h;_Vo*u6xuB!l4W_PHt(MA^;!1u&ol$Ky`5XSHzp-Mv^+XpB_)1K`7Wjt zCm3piQuwOSn_^DQ^aPSJRK1S>!%`~ zK9iE<4+RN`9p5s6!O%@_|G94=1>#=&?>-GJF!uR-_gZ=d$IkD^LPMPG|D4&LW){Hn z|J-3_HZ_w4OgAnD7`U$6*Zr8st%>QT9YtKPB149EVs~Sptq7XHAI@oe{vAW|Us^<6>>@aRA+Y{TKiM literal 0 HcmV?d00001 diff --git a/labor_4_drive/sim/work/spi_master_tb/_primary.dbs b/labor_4_drive/sim/work/spi_master_tb/_primary.dbs new file mode 100644 index 0000000000000000000000000000000000000000..95dbc807d2580a186d9ce97034b88ccf37867d4c GIT binary patch literal 2317 zcmZ{le^69a6vyw|cgb}Z7BO%Y6cCr+Q6MXrGn9m)qmKNN6+v+sCL){4@{dFr$!0Wz z(FrFT9e*U?jFMzwvC|(qI~CO203h@j_RDI05)?Srj?L{Ujus3lSpLVbu7Oq)<9OsSa|)F@`y z1l-g~q|j^vb2M|ZW`@DElF}($G*hP-RMFKb=BeQU(#>nlfSPp)gNI2dJ>Z7Y*q^R3NO9CeTv^0x8q9 zt`M=}Vd}~00aK*md@vg;L*xunI8u=Yt(^!g5*bHIM@SnB;t7#6N$ChlA{e7tjBwie zQBsFQ#*@;$uns)fD}m8OFdQ&MCX&*-U^$3o zh4zpo=u>lq$B-V^LjMrDjpyaumwMkrnbs$diwj8-v1T^qbA8KJHX$ioPA zZ9uCTp{@<6iV^DCfYvZd3`W(AW(T7hMkskhz_pC#1fz9~T*0W8QF1U^&nP7bsVf6$ zhDb%vOGr#9ReZQUIf_d;DxSAER$(PxglpS68K!*c_>Udma% z<)4c_SBv}Z)P|9tt8d*XE%E=B@Vl?Ozsr+%Joi>*lx6eLLceeQykoi6x6k$MY$&Zg zv}Nbv*NU3ni=X2D;lQOUwY^Q}Pki>taMad2cm3DiDzKF; zy?yzM=7!FD={;{QD*SX)3u^Aa2fT0YfmZz7=2BDe-9ii#Xb?5&r6zF?L*Riwr2g7a zkV-WolXQ5$E4e<@r|FAd>_ VK(ol30jB+;X+#Lz4cbRF`CnwGS9bsa literal 0 HcmV?d00001 diff --git a/labor_4_drive/sim/work/spi_master_tb/_primary.vhd b/labor_4_drive/sim/work/spi_master_tb/_primary.vhd new file mode 100644 index 0000000..16696cf --- /dev/null +++ b/labor_4_drive/sim/work/spi_master_tb/_primary.vhd @@ -0,0 +1,4 @@ +library verilog; +use verilog.vl_types.all; +entity spi_master_tb is +end spi_master_tb; diff --git a/labor_4_drive/sim/work/spi_master_tb/verilog.prw b/labor_4_drive/sim/work/spi_master_tb/verilog.prw new file mode 100644 index 0000000000000000000000000000000000000000..722640c1af857903e288abd0c128847f3f07d3f6 GIT binary patch literal 1438 zcmah}&1%~~5MIYgd+enTFtC^AP|!-NzoTP|#zcw1Rzq*9^#_Kgn8XmM(PQKZ+6U?* zb!N1&HZ+cW@W;&e&3v=N*!tA_J`(T$2>hHN{vHW2Mm)p#1L7~lkA@$Kv!{pcCO;ML zp6=EUJHq-tXDmd%JHc2!%1@NfzU3L=#kq_K10f^g4|$Pitl!*iiT|-FH-x*-kBs-V z3@H|fBgE&vt8{Wp`6OQ@glRHmpFF!br&vb5Abdl|ygcq3P(Atvw(m5(;&;#Hw{zlW z$&zEVl@v!>$T8w^oyduQ!`C;yzU@1kWE0BgX>vpOCA)m->vg`zb%Vaz_-fntdNJeu z_Iq`CZ&rS2kDlr4*?pH^Z(h!?y7~M3;JmKs>)L&%>0(OxtK4@8`?(#S^A&z*er0@= z?Xyg}yUTta?wjv47BZxJ{*NENbDkIP&0(Lln0(j!iWNEv&8Tq9D3l zch#tBp(^_7n(4+=yF@F;Dp!gqP|7q=tZ=Ok%4=AmsS^(9u);5U4;9p`2qRX6F)N}N z6&3d0GZ|4A2i&ea4#BUT1L-w@O+Zx;Y0xDU1=Ix&<#p*J6w$9#98GrvbUTP?!wn4p T&ky8xIuO!|TlzQtI~L*}#1cyD literal 0 HcmV?d00001 diff --git a/labor_4_drive/sim/work/spi_master_tb/verilog.psm b/labor_4_drive/sim/work/spi_master_tb/verilog.psm new file mode 100644 index 0000000000000000000000000000000000000000..268fe0f0281a0c766ba55d31874b0525256899cb GIT binary patch literal 19464 zcmcIsU5s7VRla9te0=RD?HPO8nAWt@jG;EPbgq9A2U0rzna0MB?RdtiU0TLTZHOU1 zZsOK11UiLKSu~X_)JPV}Ly#iXEs^j84@N4|JVe3>BrL&$9|}Z>LV(g12*p6?@O^84 zYkSYR=gc|RF7x2!wf0`$T5GSp*V^aYJF|6U%T(4``Emz8L!jTzJDp+B4}l+%e1&KZ zx*qaXpzi=(4f+Mpw}`((^iI*Yf_@O=Zv%a5sM9Gx_pRu3MnQiYbdBg*(9f^xbjCn2 zz4La_cZl94x(@XFi;Ii!@ON*B{-@~oME^td4bguW{WsBn75%R0e~W%c^xLBUBKj@S ze-`~G(SH5lN|FhVQavyivZ>Mu+82E>$XQpXq_Q|~x}9^F z-^R|a{Rek3o_%xMCQ0XDkks*=I=)l4bFrlz`p@-W4a#-$xRLfn#?{rhQ*3*izp_N# zzSE|0pXYSf{(ZKtyZ1i4mvQc%K732->~?R!zc%YUvwz3Kv^PB$_R;?7UAB+fuD9D8 z$HKL-SGUe6H@2?jb!I-8AE&-vPF?QQ<#lxTj@ccypY~55AbntV&n>O9`#BH8ZQ_3L z;BGsoZP(TDFSW#UUVJ}aZE5E%$Vb&V88788n-6(=kK|6vd2zYZ@_3m) zTodOH!4CZzK^#WGr*-xYaNI}Z*l5fb_Z!bQrsJod*2U?0aq4mUIdEF`+vQHn<7Iwk z=E=%^*%arUh=y^VYZ>PZ3Xh!!)z>Ecw+jDaOZ*29&R9M3ecu-UN=y8mM`n)QivQPJ z;y<`|=HRX1-)M? zIt0htoUfT<2duxt>f7)2h_&P`=&EJ!~1UkJ`U?%&Nrr; ze-o#kIL&-Ke(IB_NY8xWtkI`WPTXtz5R~?~57|$e_Q%7@$ER?>s`fwgnD(1x?B65% z_qhEw=irF!zj*uhx5@stLF~`U{?*&Jzg70P4q~6rFFX%#+`j!SvcF{z`-f$J9M8$O zng7kQzj+Y*56S-i+qd77{oWw<56S+y+qZAed!3ULlY`hlDElwBwSRVEBjb$s=1mjZ z$=}nN*v@(~q4Byphc>l|^Cz}%vwG$8E9#~0ahoPMfBV+X1nZj5uYVrV{4Go8d*8Te zfAbRiH=oa?-&?9*@m#GqCYR!r-z#hib@9H=#J#pYk4)G;o$O3(HvUxLH;YF)tbg1K>e`%d{oX?+C{`9|J3GZUWAC z!2*!y1dapND9Au`T=T#4)sZpcxc=XmpKDihofj9oJ;^hk6WXp=E@%3Y0Jn`m1iFXDx#akyH#O68PjUY$Qf*g3*mWCJZ(?j{o z;EBfoQoM2TAWQJx4Dz1g0FTe>@GHh|>j8hmd#s_niw#5kXMK_(ezAzUiu55#G4ckvczA$?;xJ}2|Vqe=&$j>=Q$z%1>rv@yglN#iw9YP z&-jRMIKa1a1iZIt-eu{Zm%igoi3eGNcZcu{$MKT&wRHu4xNi^T*M$GP@aCY1x@GmL zYJCgg8xHUlcU%wK7r@e=*vTNh3vY6*}l6yWTg=6}#ueucN+r9zrI^mv|{>7Sj z@DPJ_?)FR%c$P=#Yyaf0NdL<<`rD;%de9GjxX8bV1Ic|!+%xEd#7p}iwgcm~{WO9; zSfzIwddy3zXLS#H%wGY$SLNS(!v4zN8P4D8Kdq7fd5!!pB)=}|I0bNd{>t+8l22*B z`Fvd3ZGKsfhgOsOx%K(D)SJBQ|A%ViJ8R^;kkHSvUA#Q4w2KcHD(&KBSEc+DlKXyi z{~xQF@A=$=Jkc*^k^8(YeV6j+IP1l8KOM)uVE)s6L16ADp34o`7aXO%KSn;e51lX5 z&uO3X^R(2zKan2an?N4Vm-RuM52zXbbBg~O__SVmp8eeZrHyxcrjK)Sq=ajA8Mx}_ z`DNi=E#XdSzd7!8;hH{hXG^$NUx2Ii$-g1oR~vA@Azaf3?o0{S>I-mn9`i2#!#sbz zgzM+V{e4ZirVrf1C0y&Pz=fN(zFUQR#q@6WsWR^03D@+2`%nqjo*#gVv>NVl;r>Ah z*Za)t!ZSVK9V+4BvCi&sNQdD)FTBg9chgVD`%YAr7 zc&~s@_m$&)*W}%v=>aeBMeg-5*ei0cgCU+G_xcystH{0Xy(T+e??V2I-0R$RjeC6y z`?<)yuC2E|P~=|ELZ2*huVbNa7x_*kmir{!D~jCfR=B?ux!0@Er;FU{ROnMh?)543 z!6Ns%6#7t+dp&}?A(({p z#qLAM(_PZH&o425oO+P^d2=ef{7b4UhcJ(Q*YuFTYsMG3>%X9R&xd*WXJp54a6eF8 zihjLYA~+;jqmsS*)T8qZ8-2- zbv63seox2`eNQNk---WmfBC)C{obJYUN@+auDkG}-yaYD^h^(af8F>ZKG*wtKNsdj zzYPa|t8PcX-0vTuU97jh*A&M$$Zua)_xndRzs_&rMZb>+e|n||zrB9DzWaSX%!_^- z4*XVMh<>@>?~@<;9#$ORivMxFy??sj8#UkSy!7+G()l_eKW!fTJX7+==EEQLlW5QV z*(7{@A1sdVl0OtMzwXbEY5rxiQ{>W*{yb*#ZqMeyA2tX+NBa4<`S6GJgSa3@-Jc&P zkG$%8X>t6c@(0Ihi9hex{8vEPXQUtfdEDgPp3Q?lrvo4TvH9>v{VdvZe?B05eLpUa zpOQbmAAEg&Li1lVJ4G)2=+A{1W3KH=i5D$37jte>BwhevtK(b>*vyuSstmCh)xS+zz5QF1?F2dS2Ju&jrn6 z-J-o41L{pmkN2`FKamE@tJ~Y7dE2EoKcL=}^e)xtd7pH9<@ab;OM1*B_lNBZ><@kq zb~M=^#zW5gTNiT9X8svB_RZaUKrxc_#P1h>$Y^2jGqLY;8wdTY>I8=Qv&L|N&wEyi zzZrwX*ZO8##BT+qy;-A0Zu5X^;}!UZ3w+*(QheeNUwO~AiD!K#{!!uEJmA`R1-{_| zpZAs&{~qBf&)L1=?-zc!j}*Dh1Fnr%;2SRRdA~^UiA(>dKab~oNo40;@68mVYJ9?9&l|O^!JnVjVWsk7x?V!DL&VM_~VAt z&G@}`@*BiIX0*s{9&l~E0^e|f&pw^v|FrP9VYxmZ7C$CF^y4D8dBC;t3Vg!_KKpKp zPaK?sv#KZA1;Z^+Jxv~Ic|8mVchp)|PJ9CKyzL-Go%YXNzNU4S zoX6|tyj2;#TM~Ge?<5a>@%isbU-;4AbC`fgBR?+Q?HUf&$@w>Jyg%+c;Q;%Fy+=sm z*oFC3aY!CMcf<_iE8^HKeGtZ58^>vkr*UW>M86FuiQ^5MUmu6PZ%E>prhTlZ*H_Pn z4PjA$MYCZ<50cL-LByv4(G$?BK2|b{HFWr0rH4r0hImApyw7YdDC*`5QJ~AIIIn-dP%E|M2HB{XSLx zMb&={^Jk6ZqpsJ5ka`c1R>UuPjNkZ*`0f2ei}+8&P8xq9-s3f#B>tv)JrVqm@n1kk zw7*Vk8v1Z5eFZ{+tihL%uCPJr1%9;`fWH#98LYo-lrvX z{%3(hKfK<09FoWSV0=X!AD2GJviWH0SB8T)+>fSyW$)XPI6hGmhvYF1<16C$xt4J> z^((_k;%Mqu_TCP0c%Aq6VfsDUzB(uQsOx#1o0I=uZ#|Ea$Ngx0Mf}HG#^2QE3ui(m3l*Yo%vsfl0mn1ACd;(zo96u;pN5I@f|?<=1F%j$Fbz39I9 zB_Fl-CCUE(r2O}~?D?0xcL@iO_W|Q8;y=+c{-*w5IEdf z#+U04hLgn6)F149Ruac4+OOyjlE*lVuZZIpr4O=f98LYfa1ck^{$TIpk~n^;CJxEN z_goRF@fC4A-ZGB!n3v{bO1%4RI7u8${oy{^MI2rqyg%sgCG^z?$wyt!>*Eu|K_0y> zdwq~R=F#|y_@9(M$g+8C>JNs4_}!1D{$TGXE8^GRiRg=8@=@3G_@AnYU-H-=jIW5F z_j|72?Z$671H^xSSnrts1@#C0eT=^NB_I8;^t`TqO8$FY_WVm8`-AZn@joqnkY)4V z)E^87@w*>Q{b4HDi}&tl$XC==$zy*oz9J6p&o+5%>JNs4I2M4{ra$bU-J~9UntVkZ zlK1?)8($H}XQU6ZY(C~Op4OxC^Mm0eaWwUZoxxtr$64}-!|R*xE6L-zGQJ{?bJ7P{ zHjbwLU^s}w{peTI4#$TX%`Tqcsg&y7j literal 0 HcmV?d00001 diff --git a/labor_4_drive/src/spi_master.v b/labor_4_drive/src/spi_master.v new file mode 100644 index 0000000..4a63d20 --- /dev/null +++ b/labor_4_drive/src/spi_master.v @@ -0,0 +1,163 @@ +module spi_master( + // module inputs + // --- Definition of control inputs --- + input wire RESETn, + input wire CLK, + input wire [7:0] CLK_DIVIDER, + input wire [7:0] SLAVE_SELECT, + input wire [1:0] DATA_LENGTH, + input wire [1:0] MODE, + input wire MISO, + input wire [31:0] TX, + input wire RUN, + // module outputs + output reg [31:0] RX, + output SCLK, + output reg MOSI, + output reg [7:0] SSn, + output reg BUSY, + // module test outputs + output wire SYNC_TEST, + output wire [2:0] STATE_TEST, + output wire ENA_TEST +); + // --- Definition of internal variables --- + reg [31:0] TX_SR, RX_SR; + reg [7:0] CLK_DIVIDER_REG; + reg [5:0] CYCLE_CTR; + reg [2:0] STATE; + reg ENA; // Enables operation of SCLK generator + reg T1, Q1; // Used for SCLK generation + wire CPOL, CPHA; // SPI Mode + wire SYNC; // SYNC Signal + + // --- Implementation --- + // assignments of test signals + assign STATE_TEST = STATE; + assign ENA_TEST = ENA; + assign SYNC_TEST = SYNC; + + // assignments MODE to control wires + assign CPOL = MODE[1]; + assign CPHA = MODE[0]; + + // Clock divider for generation of SYNC signal + always @(posedge CLK or negedge RESETn) begin + if (~RESETn) begin + CLK_DIVIDER_REG <= 8'h0; + end else if (CLK_DIVIDER_REG == 8'h0) begin + CLK_DIVIDER_REG <= CLK_DIVIDER; + end else if (CLK_DIVIDER > 8'h0) begin + CLK_DIVIDER_REG <= CLK_DIVIDER_REG - 1'b1; + end + end + +assign SYNC = (CLK_DIVIDER_REG == 8'h0); + +// SPI-interface control logic +always @(posedge CLK or negedge RESETn) begin + if (~RESETn) begin + STATE <= 3'b000; + TX_SR <= 32'h0; + RX_SR <= 32'h0; + CYCLE_CTR <= 6'h0; + SSn <= 8'hFF; + ENA <= 1'b0; + MOSI <= 1'b0; + RX <= 32'b0; + BUSY <= 1'b0; + end else begin + case (STATE) + // STATE: Wait + 3'h0: + if (RUN) begin + STATE <= 3'h1; + end + + // STATE: Initialize + 3'h1: + if (SYNC) begin + SSn <= ~SLAVE_SELECT; + ENA <= 1'b1; + if (CPHA) begin + case (DATA_LENGTH[1:0]) + 2'h0: begin + CYCLE_CTR <= 6'h8; + TX_SR[31:24] <= TX[7:0]; + end + 2'h1: begin + CYCLE_CTR <= 6'h10; + TX_SR[31:16] <= TX[15:0]; + end + 2'h2: begin + CYCLE_CTR <= 6'h18; + TX_SR[31:8] <= TX[23:0]; + end + 2'h3: begin + CYCLE_CTR <= 6'h20; + TX_SR <= TX; + end + endcase + BUSY <= 1'b1; + STATE <= 3'h2; + end + end + + // STATE: Shift + 3'h2: + if (SYNC) begin + if (~CPHA) begin + SSn <= ~SLAVE_SELECT; + end + MOSI <= TX_SR[31]; + RX_SR <= {RX_SR[30:0], MISO}; + TX_SR <= {TX_SR[30:0], 1'b0}; + CYCLE_CTR <= CYCLE_CTR - 1'b1; + if (CYCLE_CTR == 0) begin + STATE <= 3'h3; + end + end + + // STATE: Latch + 3'h3: + if (SYNC) begin + RX_SR[0] <= MISO; + if (CYCLE_CTR == 0) begin + STATE <= 3'h4; + ENA <= 1'b0; + end else begin + STATE <= 3'h2; + end + end + + // STATE: Clear / Idle + 3'h4: + if (SYNC) begin + SSn <= 8'hFF; + BUSY <= 1'b0; + STATE <= 3'h0; + case (DATA_LENGTH[1:0]) + 2'h0: RX <= {24'h0, RX_SR[7:0]}; // 1 Byte received + 2'h1: RX <= {16'h0, RX_SR[15:0]}; // 2 Bytes received + 2'h2: RX <= {8'h0, RX_SR[23:0]}; // 3 Bytes received + 2'h3: RX <= RX_SR; // 4 Bytes received + endcase + end + endcase + end +end + +// SPI SCLK generation +always @(posedge CLK or negedge RESETn) begin + if (~RESETn) begin + T1 <= 1'b0; + Q1 <= 1'b0; + end else if (SYNC) begin + T1 <= ~T1 & ENA; + Q1 <= T1; + end +end + +assign SCLK = ((Q1 & ~CPHA) | (T1 & CPHA)) ^ CPOL; + +endmodule \ No newline at end of file