Erste Lösungsvariante ffür 6.3 erstellt
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1709148267302 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1709148267302 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 28 20:24:27 2024 " "Processing started: Wed Feb 28 20:24:27 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1709148267302 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1709148267302 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sclk_gen -c sclk_gen " "Command: quartus_map --read_settings_files=on --write_settings_files=off sclk_gen -c sclk_gen" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1709148267302 ""}
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{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1709148267633 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/erdem/desktop/labor_eds/labor_4/aufgabe_6-3/src/sclk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/erdem/desktop/labor_eds/labor_4/aufgabe_6-3/src/sclk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 SCLK_gen " "Found entity 1: SCLK_gen" { } { { "../src/sclk_gen.v" "" { Text "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/src/sclk_gen.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1709148267664 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1709148267664 ""}
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{ "Warning" "WSGN_FILE_IS_MISSING" "../src/d_ff.v " "Can't analyze file -- file ../src/d_ff.v is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1709148267680 ""}
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{ "Error" "ESGN_TOP_ENTITY_IS_MISSING" "sclk_gen " "Top-level design entity \"sclk_gen\" is undefined" { } { } 0 12007 "Top-level design entity \"%1!s!\" is undefined" 0 0 "Quartus II" 0 -1 1709148267711 ""}
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{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 2 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was unsuccessful. 1 error, 2 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "373 " "Peak virtual memory: 373 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1709148267758 ""} { "Error" "EQEXE_END_BANNER_TIME" "Wed Feb 28 20:24:27 2024 " "Processing ended: Wed Feb 28 20:24:27 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1709148267758 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1709148267758 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1709148267758 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1709148267758 ""}
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{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 2 s " "Quartus II Full Compilation was unsuccessful. 3 errors, 2 warnings" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1709148268356 ""}
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1709148352099 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1709148352099 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 28 20:25:51 2024 " "Processing started: Wed Feb 28 20:25:51 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1709148352099 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1709148352099 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off sclk_gen -c sclk_gen " "Command: quartus_asm --read_settings_files=off --write_settings_files=off sclk_gen -c sclk_gen" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1709148352099 ""}
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{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1709148352831 ""}
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{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1709148352862 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "379 " "Peak virtual memory: 379 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1709148353177 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 28 20:25:53 2024 " "Processing ended: Wed Feb 28 20:25:53 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1709148353177 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1709148353177 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1709148353177 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1709148353177 ""}
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<?xml version="1.0" ?>
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<LOG_ROOT>
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<PROJECT NAME="sclk_gen">
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</PROJECT>
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</LOG_ROOT>
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v1
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IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
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IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
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IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
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IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
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IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
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IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
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IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
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IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
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IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
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IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
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IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
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IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
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IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
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IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
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IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
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IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
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IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
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IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
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IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
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IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
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IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
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IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
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IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
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IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
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IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
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IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
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IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
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IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
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IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
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IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
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IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
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IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
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IO_RULES_MATRIX,Total Pass,0;0;0;0;0;7;0;0;7;7;0;1;0;0;6;0;1;6;0;0;0;1;0;0;0;0;0;7;0;0,
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IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
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IO_RULES_MATRIX,Total Inapplicable,7;7;7;7;7;0;7;7;0;0;7;6;7;7;1;7;6;1;7;7;7;6;7;7;7;7;7;0;7;7,
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IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
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IO_RULES_MATRIX,SCLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
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IO_RULES_MATRIX,CPHA,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
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IO_RULES_MATRIX,CPOL,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
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IO_RULES_MATRIX,CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
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IO_RULES_MATRIX,RESETn,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
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IO_RULES_MATRIX,SYNC,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
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IO_RULES_MATRIX,ENA,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
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IO_RULES_SUMMARY,Total I/O Rules,30,
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IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
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IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
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IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
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IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,
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Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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Version_Index = 302049280
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Creation_Time = Wed Feb 28 19:17:51 2024
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|sclk_gen
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ENA => T1.IN1
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SYNC => Q1.ENA
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SYNC => T1.ENA
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RESETn => Q1.ACLR
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RESETn => T1.ACLR
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CPHA => SCLK_1.IN1
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CPHA => SCLK_0.IN1
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CLK => Q1.CLK
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CLK => T1.CLK
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CPOL => SCLK_3.IN1
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SCLK <= SCLK_3.DB_MAX_OUTPUT_PORT_TYPE
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<TABLE>
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<TR bgcolor="#C0C0C0">
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<TH>Hierarchy</TH>
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<TH>Input</TH>
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<TH>Constant Input</TH>
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<TH>Unused Input</TH>
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<TH>Floating Input</TH>
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<TH>Output</TH>
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<TH>Constant Output</TH>
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<TH>Unused Output</TH>
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<TH>Floating Output</TH>
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<TH>Bidir</TH>
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<TH>Constant Bidir</TH>
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<TH>Unused Bidir</TH>
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<TH>Input only Bidir</TH>
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<TH>Output only Bidir</TH>
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</TR>
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</TABLE>
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Legal Partition Candidates ;
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+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
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; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
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+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
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v1
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1709148343874 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1709148343874 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 28 20:25:43 2024 " "Processing started: Wed Feb 28 20:25:43 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1709148343874 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1709148343874 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sclk_gen -c sclk_gen " "Command: quartus_map --read_settings_files=on --write_settings_files=off sclk_gen -c sclk_gen" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1709148343874 ""}
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{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1709148344189 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/erdem/desktop/labor_eds/labor_4/aufgabe_6-3/src/sclk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/erdem/desktop/labor_eds/labor_4/aufgabe_6-3/src/sclk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 sclk_gen " "Found entity 1: sclk_gen" { } { { "../src/sclk_gen.v" "" { Text "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/src/sclk_gen.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1709148344236 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1709148344236 ""}
|
||||
{ "Warning" "WSGN_FILE_IS_MISSING" "../src/d_ff.v " "Can't analyze file -- file ../src/d_ff.v is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1709148344236 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "sclk_gen " "Elaborating entity \"sclk_gen\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1709148344267 ""}
|
||||
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1709148344755 ""}
|
||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1709148344961 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1709148344961 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "10 " "Implemented 10 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1709148344977 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1709148344977 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3 " "Implemented 3 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1709148344977 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1709148344977 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "390 " "Peak virtual memory: 390 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1709148344993 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 28 20:25:44 2024 " "Processing ended: Wed Feb 28 20:25:44 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1709148344993 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1709148344993 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1709148344993 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1709148344993 ""}
|
||||
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|
||||
v1
|
||||
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|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1709148362091 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 32-bit " "Running Quartus II 32-bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1709148362091 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 28 20:26:01 2024 " "Processing started: Wed Feb 28 20:26:01 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1709148362091 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1709148362091 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp sclk_gen -c sclk_gen --netlist_type=sgate " "Command: quartus_rpp sclk_gen -c sclk_gen --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1709148362091 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "245 " "Peak virtual memory: 245 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1709148362123 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 28 20:26:02 2024 " "Processing ended: Wed Feb 28 20:26:02 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1709148362123 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1709148362123 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1709148362123 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1709148362123 ""}
|
||||
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|
||||
DONE
|
||||
@@ -0,0 +1,41 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1709148354172 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354172 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 28 20:25:53 2024 " "Processing started: Wed Feb 28 20:25:53 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1709148354172 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1709148354172 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta sclk_gen -c sclk_gen " "Command: quartus_sta sclk_gen -c sclk_gen" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1709148354172 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1709148354251 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1709148354392 ""}
|
||||
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1709148354424 ""}
|
||||
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1709148354424 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "sclk_gen.sdc " "Synopsys Design Constraints File file not found: 'sclk_gen.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1709148354675 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1709148354675 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK CLK " "create_clock -period 1.000 -name CLK CLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354690 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354690 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1709148354769 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354769 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1709148354769 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1709148354785 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.092 " "Worst-case setup slack is 0.092" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.092 0.000 CLK " " 0.092 0.000 CLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.359 " "Worst-case hold slack is 0.359" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.359 0.000 CLK " " 0.359 0.000 CLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148354785 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148354785 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1709148354800 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1709148354800 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354800 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354800 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -5.000 CLK " " -3.000 -5.000 CLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354800 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148354800 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1709148354816 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1709148354832 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1709148355036 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.186 " "Worst-case setup slack is 0.186" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 CLK " " 0.186 0.000 CLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.318 " "Worst-case hold slack is 0.318" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.318 0.000 CLK " " 0.318 0.000 CLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148355067 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148355067 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1709148355067 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1709148355067 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -5.000 CLK " " -3.000 -5.000 CLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}
|
||||
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1709148355099 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.506 " "Worst-case setup slack is 0.506" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.506 0.000 CLK " " 0.506 0.000 CLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.193 0.000 CLK " " 0.193 0.000 CLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148355287 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148355287 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1709148355287 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1709148355287 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -5.052 CLK " " -3.000 -5.052 CLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355287 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355287 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1709148355776 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1709148355776 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "376 " "Peak virtual memory: 376 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1709148355823 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 28 20:25:55 2024 " "Processing ended: Wed Feb 28 20:25:55 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1709148355823 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1709148355823 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1709148355823 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1709148355823 ""}
|
||||
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BIN
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@@ -0,0 +1,6 @@
|
||||
start_full_compilation:s:00:00:13
|
||||
start_analysis_synthesis:s:00:00:02-start_full_compilation
|
||||
start_analysis_elaboration:s-start_full_compilation
|
||||
start_fitter:s:00:00:06-start_full_compilation
|
||||
start_assembler:s:00:00:02-start_full_compilation
|
||||
start_timing_analyzer:s:00:00:03-start_full_compilation
|
||||
Binary file not shown.
@@ -0,0 +1,11 @@
|
||||
This folder contains data for incremental compilation.
|
||||
|
||||
The compiled_partitions sub-folder contains previous compilation results for each partition.
|
||||
As long as this folder is preserved, incremental compilation results from earlier compiles
|
||||
can be re-used. To perform a clean compilation from source files for all partitions, both
|
||||
the db and incremental_db folder should be removed.
|
||||
|
||||
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
|
||||
As long as this folder is preserved, imported partitions will be automatically re-imported
|
||||
when the db or incremental_db/compiled_partitions folders are removed.
|
||||
|
||||
@@ -0,0 +1,3 @@
|
||||
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Version_Index = 302049280
|
||||
Creation_Time = Wed Feb 28 19:18:03 2024
|
||||
BIN
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BIN
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BIN
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BIN
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BIN
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+1
@@ -0,0 +1 @@
|
||||
v1
|
||||
BIN
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BIN
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BIN
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BIN
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+1
@@ -0,0 +1 @@
|
||||
6d99a1516c2e2beefe1f386eab1dd580
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,116 @@
|
||||
Assembler report for sclk_gen
|
||||
Wed Feb 28 20:25:53 2024
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Assembler Summary
|
||||
3. Assembler Settings
|
||||
4. Assembler Generated Files
|
||||
5. Assembler Device Options: C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/output_files/sclk_gen.sof
|
||||
6. Assembler Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Wed Feb 28 20:25:53 2024 ;
|
||||
; Revision Name ; sclk_gen ;
|
||||
; Top-level Entity Name ; sclk_gen ;
|
||||
; Family ; Cyclone IV GX ;
|
||||
; Device ; EP4CGX15BF14C6 ;
|
||||
+-----------------------+---------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------+
|
||||
; Assembler Settings ;
|
||||
+-----------------------------------------------------------------------------+----------+---------------+
|
||||
; Option ; Setting ; Default Value ;
|
||||
+-----------------------------------------------------------------------------+----------+---------------+
|
||||
; Use smart compilation ; Off ; Off ;
|
||||
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
|
||||
; Enable compact report table ; Off ; Off ;
|
||||
; Generate compressed bitstreams ; On ; On ;
|
||||
; Compression mode ; Off ; Off ;
|
||||
; Clock source for configuration device ; Internal ; Internal ;
|
||||
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
|
||||
; Divide clock frequency by ; 1 ; 1 ;
|
||||
; Auto user code ; On ; On ;
|
||||
; Use configuration device ; Off ; Off ;
|
||||
; Configuration device ; Auto ; Auto ;
|
||||
; Configuration device auto user code ; Off ; Off ;
|
||||
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
|
||||
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
|
||||
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
|
||||
; Hexadecimal Output File start address ; 0 ; 0 ;
|
||||
; Hexadecimal Output File count direction ; Up ; Up ;
|
||||
; Release clears before tri-states ; Off ; Off ;
|
||||
; Auto-restart configuration after error ; On ; On ;
|
||||
; Enable OCT_DONE ; Off ; Off ;
|
||||
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
|
||||
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
|
||||
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
|
||||
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
|
||||
+-----------------------------------------------------------------------------+----------+---------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------+
|
||||
; Assembler Generated Files ;
|
||||
+----------------------------------------------------------------------------------------+
|
||||
; File Name ;
|
||||
+----------------------------------------------------------------------------------------+
|
||||
; C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/output_files/sclk_gen.sof ;
|
||||
+----------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------+
|
||||
; Assembler Device Options: C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/output_files/sclk_gen.sof ;
|
||||
+----------------+-------------------------------------------------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+-------------------------------------------------------------------------------------------------+
|
||||
; Device ; EP4CGX15BF14C6 ;
|
||||
; JTAG usercode ; 0x000BB9A9 ;
|
||||
; Checksum ; 0x000BB9A9 ;
|
||||
+----------------+-------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------+
|
||||
; Assembler Messages ;
|
||||
+--------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit Assembler
|
||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Info: Processing started: Wed Feb 28 20:25:51 2024
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off sclk_gen -c sclk_gen
|
||||
Info (115031): Writing out detailed assembly data for power analysis
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 379 megabytes
|
||||
Info: Processing ended: Wed Feb 28 20:25:53 2024
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
|
||||
|
||||
@@ -0,0 +1 @@
|
||||
Wed Feb 28 20:26:02 2024
|
||||
@@ -0,0 +1,951 @@
|
||||
Fitter report for sclk_gen
|
||||
Wed Feb 28 20:25:50 2024
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Fitter Summary
|
||||
3. Fitter Settings
|
||||
4. Parallel Compilation
|
||||
5. I/O Assignment Warnings
|
||||
6. Incremental Compilation Preservation Summary
|
||||
7. Incremental Compilation Partition Settings
|
||||
8. Incremental Compilation Placement Preservation
|
||||
9. Pin-Out File
|
||||
10. Fitter Resource Usage Summary
|
||||
11. Fitter Partition Statistics
|
||||
12. Input Pins
|
||||
13. Output Pins
|
||||
14. Dual Purpose and Dedicated Pins
|
||||
15. I/O Bank Usage
|
||||
16. All Package Pins
|
||||
17. Fitter Resource Utilization by Entity
|
||||
18. Delay Chain Summary
|
||||
19. Pad To Core Delay Chain Fanout
|
||||
20. Control Signals
|
||||
21. Global & Other Fast Signals
|
||||
22. Non-Global High Fan-Out Signals
|
||||
23. Other Routing Usage Summary
|
||||
24. LAB Logic Elements
|
||||
25. LAB-wide Signals
|
||||
26. LAB Signals Sourced
|
||||
27. LAB Signals Sourced Out
|
||||
28. LAB Distinct Inputs
|
||||
29. I/O Rules Summary
|
||||
30. I/O Rules Details
|
||||
31. I/O Rules Matrix
|
||||
32. Fitter Device Options
|
||||
33. Operating Settings and Conditions
|
||||
34. Fitter Messages
|
||||
35. Fitter Suppressed Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+------------------------------------+-------------------------------------------------+
|
||||
; Fitter Status ; Successful - Wed Feb 28 20:25:50 2024 ;
|
||||
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Revision Name ; sclk_gen ;
|
||||
; Top-level Entity Name ; sclk_gen ;
|
||||
; Family ; Cyclone IV GX ;
|
||||
; Device ; EP4CGX15BF14C6 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 2 / 14,400 ( < 1 % ) ;
|
||||
; Total combinational functions ; 2 / 14,400 ( < 1 % ) ;
|
||||
; Dedicated logic registers ; 2 / 14,400 ( < 1 % ) ;
|
||||
; Total registers ; 2 ;
|
||||
; Total pins ; 7 / 81 ( 9 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 0 / 552,960 ( 0 % ) ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 ;
|
||||
; Total GXB Receiver Channel PCS ; 0 / 2 ( 0 % ) ;
|
||||
; Total GXB Receiver Channel PMA ; 0 / 2 ( 0 % ) ;
|
||||
; Total GXB Transmitter Channel PCS ; 0 / 2 ( 0 % ) ;
|
||||
; Total GXB Transmitter Channel PMA ; 0 / 2 ( 0 % ) ;
|
||||
; Total PLLs ; 0 / 3 ( 0 % ) ;
|
||||
+------------------------------------+-------------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Fitter Settings ;
|
||||
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
|
||||
; Option ; Setting ; Default Value ;
|
||||
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
|
||||
; Device ; auto ; ;
|
||||
; Fit Attempts to Skip ; 0 ; 0.0 ;
|
||||
; Use smart compilation ; Off ; Off ;
|
||||
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
|
||||
; Enable compact report table ; Off ; Off ;
|
||||
; Auto Merge PLLs ; On ; On ;
|
||||
; Router Timing Optimization Level ; Normal ; Normal ;
|
||||
; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
|
||||
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
|
||||
; Router Effort Multiplier ; 1.0 ; 1.0 ;
|
||||
; Optimize Hold Timing ; All Paths ; All Paths ;
|
||||
; Optimize Multi-Corner Timing ; On ; On ;
|
||||
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
|
||||
; SSN Optimization ; Off ; Off ;
|
||||
; Optimize Timing ; Normal compilation ; Normal compilation ;
|
||||
; Optimize Timing for ECOs ; Off ; Off ;
|
||||
; Regenerate full fit report during ECO compiles ; Off ; Off ;
|
||||
; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
|
||||
; Limit to One Fitting Attempt ; Off ; Off ;
|
||||
; Final Placement Optimizations ; Automatically ; Automatically ;
|
||||
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
|
||||
; Fitter Initial Placement Seed ; 1 ; 1 ;
|
||||
; PCI I/O ; Off ; Off ;
|
||||
; Weak Pull-Up Resistor ; Off ; Off ;
|
||||
; Enable Bus-Hold Circuitry ; Off ; Off ;
|
||||
; Auto Packed Registers ; Auto ; Auto ;
|
||||
; Auto Delay Chains ; On ; On ;
|
||||
; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
|
||||
; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
|
||||
; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
|
||||
; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
|
||||
; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
|
||||
; Perform Register Duplication for Performance ; Off ; Off ;
|
||||
; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
|
||||
; Perform Register Retiming for Performance ; Off ; Off ;
|
||||
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
|
||||
; Fitter Effort ; Auto Fit ; Auto Fit ;
|
||||
; Physical Synthesis Effort Level ; Normal ; Normal ;
|
||||
; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
|
||||
; Auto Register Duplication ; Auto ; Auto ;
|
||||
; Auto Global Clock ; On ; On ;
|
||||
; Auto Global Register Control Signals ; On ; On ;
|
||||
; Generate GXB Reconfig MIF ; Off ; Off ;
|
||||
; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
|
||||
; Synchronizer Identification ; Off ; Off ;
|
||||
; Enable Beneficial Skew Optimization ; On ; On ;
|
||||
; Optimize Design for Metastability ; On ; On ;
|
||||
; Active Serial clock source ; FREQ_40MHz ; FREQ_40MHz ;
|
||||
; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
|
||||
; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
|
||||
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
|
||||
|
||||
|
||||
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
|
||||
+-------------------------------------+
|
||||
; Parallel Compilation ;
|
||||
+----------------------------+--------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+--------+
|
||||
; Number detected on machine ; 4 ;
|
||||
; Maximum allowed ; 1 ;
|
||||
+----------------------------+--------+
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; I/O Assignment Warnings ;
|
||||
+----------+-------------------------------+
|
||||
; Pin Name ; Reason ;
|
||||
+----------+-------------------------------+
|
||||
; SCLK ; Incomplete set of assignments ;
|
||||
; CPHA ; Incomplete set of assignments ;
|
||||
; CPOL ; Incomplete set of assignments ;
|
||||
; CLK ; Incomplete set of assignments ;
|
||||
; RESETn ; Incomplete set of assignments ;
|
||||
; SYNC ; Incomplete set of assignments ;
|
||||
; ENA ; Incomplete set of assignments ;
|
||||
+----------+-------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------+
|
||||
; Incremental Compilation Preservation Summary ;
|
||||
+---------------------+------------------------+
|
||||
; Type ; Value ;
|
||||
+---------------------+------------------------+
|
||||
; Placement (by node) ; ;
|
||||
; -- Requested ; 0 / 31 ( 0.00 % ) ;
|
||||
; -- Achieved ; 0 / 31 ( 0.00 % ) ;
|
||||
; ; ;
|
||||
; Routing (by net) ; ;
|
||||
; -- Requested ; 0 / 0 ( 0.00 % ) ;
|
||||
; -- Achieved ; 0 / 0 ( 0.00 % ) ;
|
||||
+---------------------+------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Incremental Compilation Partition Settings ;
|
||||
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
|
||||
; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
|
||||
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
|
||||
; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
|
||||
; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
|
||||
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------+
|
||||
; Incremental Compilation Placement Preservation ;
|
||||
+--------------------------------+---------+-------------------+-------------------------+-------------------+
|
||||
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
|
||||
+--------------------------------+---------+-------------------+-------------------------+-------------------+
|
||||
; Top ; 21 ; 0 ; N/A ; Source File ;
|
||||
; hard_block:auto_generated_inst ; 10 ; 0 ; N/A ; Source File ;
|
||||
+--------------------------------+---------+-------------------+-------------------------+-------------------+
|
||||
|
||||
|
||||
+--------------+
|
||||
; Pin-Out File ;
|
||||
+--------------+
|
||||
The pin-out file can be found in C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/output_files/sclk_gen.pin.
|
||||
|
||||
|
||||
+--------------------------------------------------------------------+
|
||||
; Fitter Resource Usage Summary ;
|
||||
+---------------------------------------------+----------------------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+----------------------+
|
||||
; Total logic elements ; 2 / 14,400 ( < 1 % ) ;
|
||||
; -- Combinational with no register ; 0 ;
|
||||
; -- Register only ; 0 ;
|
||||
; -- Combinational with a register ; 2 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 1 ;
|
||||
; -- 3 input functions ; 0 ;
|
||||
; -- <=2 input functions ; 1 ;
|
||||
; -- Register only ; 0 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 2 ;
|
||||
; -- arithmetic mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers* ; 2 / 14,733 ( < 1 % ) ;
|
||||
; -- Dedicated logic registers ; 2 / 14,400 ( < 1 % ) ;
|
||||
; -- I/O registers ; 0 / 333 ( 0 % ) ;
|
||||
; ; ;
|
||||
; Total LABs: partially or completely used ; 1 / 900 ( < 1 % ) ;
|
||||
; Virtual pins ; 0 ;
|
||||
; I/O pins ; 7 / 81 ( 9 % ) ;
|
||||
; -- Clock pins ; 1 / 6 ( 17 % ) ;
|
||||
; -- Dedicated input pins ; 0 / 12 ( 0 % ) ;
|
||||
; ; ;
|
||||
; Global signals ; 2 ;
|
||||
; M9Ks ; 0 / 60 ( 0 % ) ;
|
||||
; Total block memory bits ; 0 / 552,960 ( 0 % ) ;
|
||||
; Total block memory implementation bits ; 0 / 552,960 ( 0 % ) ;
|
||||
; PLLs ; 0 / 3 ( 0 % ) ;
|
||||
; Global clocks ; 2 / 20 ( 10 % ) ;
|
||||
; JTAGs ; 0 / 1 ( 0 % ) ;
|
||||
; CRC blocks ; 0 / 1 ( 0 % ) ;
|
||||
; ASMI blocks ; 0 / 1 ( 0 % ) ;
|
||||
; GXB Receiver channel PCSs ; 0 / 2 ( 0 % ) ;
|
||||
; GXB Receiver channel PMAs ; 0 / 2 ( 0 % ) ;
|
||||
; GXB Transmitter channel PCSs ; 0 / 2 ( 0 % ) ;
|
||||
; GXB Transmitter channel PMAs ; 0 / 2 ( 0 % ) ;
|
||||
; Impedance control blocks ; 0 / 3 ( 0 % ) ;
|
||||
; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
|
||||
; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ;
|
||||
; Maximum fan-out ; 3 ;
|
||||
; Highest non-global fan-out ; 3 ;
|
||||
; Total fan-out ; 29 ;
|
||||
; Average fan-out ; 0.97 ;
|
||||
+---------------------------------------------+----------------------+
|
||||
* Register count does not include registers inside RAM blocks or DSP blocks.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------+
|
||||
; Fitter Partition Statistics ;
|
||||
+---------------------------------------------+---------------------+--------------------------------+
|
||||
; Statistic ; Top ; hard_block:auto_generated_inst ;
|
||||
+---------------------------------------------+---------------------+--------------------------------+
|
||||
; Difficulty Clustering Region ; Low ; Low ;
|
||||
; ; ; ;
|
||||
; Total logic elements ; 2 / 14400 ( < 1 % ) ; 0 / 14400 ( 0 % ) ;
|
||||
; -- Combinational with no register ; 0 ; 0 ;
|
||||
; -- Register only ; 0 ; 0 ;
|
||||
; -- Combinational with a register ; 2 ; 0 ;
|
||||
; ; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ; ;
|
||||
; -- 4 input functions ; 1 ; 0 ;
|
||||
; -- 3 input functions ; 0 ; 0 ;
|
||||
; -- <=2 input functions ; 1 ; 0 ;
|
||||
; -- Register only ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Logic elements by mode ; ; ;
|
||||
; -- normal mode ; 2 ; 0 ;
|
||||
; -- arithmetic mode ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Total registers ; 2 ; 0 ;
|
||||
; -- Dedicated logic registers ; 2 / 14400 ( < 1 % ) ; 0 / 14400 ( 0 % ) ;
|
||||
; ; ; ;
|
||||
; Total LABs: partially or completely used ; 1 / 900 ( < 1 % ) ; 0 / 900 ( 0 % ) ;
|
||||
; ; ; ;
|
||||
; Virtual pins ; 0 ; 0 ;
|
||||
; I/O pins ; 7 ; 0 ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 ; 0 ;
|
||||
; Total memory bits ; 0 ; 0 ;
|
||||
; Total RAM block bits ; 0 ; 0 ;
|
||||
; Clock control block ; 2 / 23 ( 8 % ) ; 0 / 23 ( 0 % ) ;
|
||||
; ; ; ;
|
||||
; Connections ; ; ;
|
||||
; -- Input Connections ; 0 ; 0 ;
|
||||
; -- Registered Input Connections ; 0 ; 0 ;
|
||||
; -- Output Connections ; 0 ; 0 ;
|
||||
; -- Registered Output Connections ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Internal Connections ; ; ;
|
||||
; -- Total Connections ; 24 ; 5 ;
|
||||
; -- Registered Connections ; 4 ; 0 ;
|
||||
; ; ; ;
|
||||
; External Connections ; ; ;
|
||||
; -- Top ; 0 ; 0 ;
|
||||
; -- hard_block:auto_generated_inst ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Partition Interface ; ; ;
|
||||
; -- Input Ports ; 6 ; 0 ;
|
||||
; -- Output Ports ; 1 ; 0 ;
|
||||
; -- Bidir Ports ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Registered Ports ; ; ;
|
||||
; -- Registered Input Ports ; 0 ; 0 ;
|
||||
; -- Registered Output Ports ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Port Connectivity ; ; ;
|
||||
; -- Input Ports driven by GND ; 0 ; 0 ;
|
||||
; -- Output Ports driven by GND ; 0 ; 0 ;
|
||||
; -- Input Ports driven by VCC ; 0 ; 0 ;
|
||||
; -- Output Ports driven by VCC ; 0 ; 0 ;
|
||||
; -- Input Ports with no Source ; 0 ; 0 ;
|
||||
; -- Output Ports with no Source ; 0 ; 0 ;
|
||||
; -- Input Ports with no Fanout ; 0 ; 0 ;
|
||||
; -- Output Ports with no Fanout ; 0 ; 0 ;
|
||||
+---------------------------------------------+---------------------+--------------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Input Pins ;
|
||||
+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+
|
||||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ;
|
||||
+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+
|
||||
; CLK ; J7 ; 3A ; 16 ; 0 ; 14 ; 2 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ;
|
||||
; CPHA ; M6 ; 3 ; 12 ; 0 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ;
|
||||
; CPOL ; N4 ; 3 ; 10 ; 0 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ;
|
||||
; ENA ; L4 ; 3 ; 8 ; 0 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ;
|
||||
; RESETn ; J6 ; 3A ; 16 ; 0 ; 21 ; 2 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ;
|
||||
; SYNC ; N6 ; 3 ; 12 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ;
|
||||
+--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Output Pins ;
|
||||
+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
|
||||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
|
||||
+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
|
||||
; SCLK ; M4 ; 3 ; 8 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
|
||||
+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------+
|
||||
; Dual Purpose and Dedicated Pins ;
|
||||
+----------+-----------------------+--------------------------+------------------+---------------------------+
|
||||
; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
|
||||
+----------+-----------------------+--------------------------+------------------+---------------------------+
|
||||
; L3 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
|
||||
; N3 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
|
||||
; K5 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
|
||||
; J5 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
|
||||
; K6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
|
||||
; N4 ; DIFFIO_B1p, CRC_ERROR ; Use as regular IO ; CPOL ; Dual Purpose Pin ;
|
||||
; N5 ; DIFFIO_B1n, NCEO ; Use as programming pin ; ~ALTERA_NCEO~ ; Dual Purpose Pin ;
|
||||
; M6 ; DIFFIO_B2p, INIT_DONE ; Use as regular IO ; CPHA ; Dual Purpose Pin ;
|
||||
; A5 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
|
||||
; B5 ; ASDO ; As input tri-stated ; ~ALTERA_ASDO~ ; Dual Purpose Pin ;
|
||||
; C5 ; NCSO ; As input tri-stated ; ~ALTERA_NCSO~ ; Dual Purpose Pin ;
|
||||
; A4 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
|
||||
; D5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
|
||||
; C4 ; nCE ; - ; - ; Dedicated Programming Pin ;
|
||||
+----------+-----------------------+--------------------------+------------------+---------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------+
|
||||
; I/O Bank Usage ;
|
||||
+----------+-----------------+---------------+--------------+------------------+
|
||||
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCCLKIN Voltage ;
|
||||
+----------+-----------------+---------------+--------------+------------------+
|
||||
; QL0 ; 0 / 8 ( 0 % ) ; -- ; -- ; -- ;
|
||||
; 3 ; 6 / 8 ( 75 % ) ; 2.5V ; -- ; -- ;
|
||||
; 3A ; 2 / 2 ( 100 % ) ; -- ; -- ; 2.5V ;
|
||||
; 4 ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; -- ;
|
||||
; 5 ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; -- ;
|
||||
; 6 ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; -- ;
|
||||
; 7 ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; -- ;
|
||||
; 8A ; 0 / 2 ( 0 % ) ; -- ; -- ; 2.5V ;
|
||||
; 8 ; 0 / 5 ( 0 % ) ; 2.5V ; -- ; -- ;
|
||||
; 9 ; 4 / 4 ( 100 % ) ; 2.5V ; -- ; -- ;
|
||||
+----------+-----------------+---------------+--------------+------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; All Package Pins ;
|
||||
+----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
|
||||
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
|
||||
+----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
|
||||
; A1 ; 99 ; 9 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
|
||||
; A2 ; 98 ; 9 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
|
||||
; A3 ; 96 ; 9 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
|
||||
; A4 ; 93 ; 9 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Column I/O ; N ; no ; On ;
|
||||
; A5 ; 90 ; 9 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Column I/O ; N ; no ; On ;
|
||||
; A6 ; 89 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; A7 ; 87 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; A8 ; 88 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; A9 ; 81 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
|
||||
; A10 ; 82 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
|
||||
; A11 ; 79 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; A12 ; 80 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; A13 ; 73 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; B1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; B3 ; 97 ; 9 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
|
||||
; B4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; B5 ; 91 ; 9 ; ~ALTERA_ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Column I/O ; N ; no ; On ;
|
||||
; B6 ; 86 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; B7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; B8 ; 77 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; B10 ; 76 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
|
||||
; B11 ; 75 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; B13 ; 74 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; C1 ; 9 ; QL0 ; GXB_NC ; ; ; ; -- ; ; -- ; -- ;
|
||||
; C2 ; 8 ; QL0 ; GXB_NC ; ; ; ; -- ; ; -- ; -- ;
|
||||
; C3 ; ; 9 ; VCCIO9 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; C4 ; 95 ; 9 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
|
||||
; C5 ; 92 ; 9 ; ~ALTERA_NCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Column I/O ; N ; no ; On ;
|
||||
; C6 ; 85 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
|
||||
; C7 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; C8 ; 78 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; C9 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; C10 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; C11 ; 69 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; C12 ; 70 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; C13 ; 71 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; D1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; D2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; D3 ; ; ; VCCD_PLL ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; D4 ; ; -- ; VCCA ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; D5 ; 94 ; 9 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
|
||||
; D6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; D7 ; ; 8A ; VCC_CLKIN8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; D8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; D9 ; ; -- ; VCCA ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; D10 ; 65 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; D11 ; 68 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; D12 ; 67 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; D13 ; 72 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; E1 ; 11 ; QL0 ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ;
|
||||
; E2 ; 10 ; QL0 ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ;
|
||||
; E3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; E4 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; E5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; E6 ; 83 ; 8A ; GXB_GND* ; ; ; ; Column I/O ; ; -- ; -- ;
|
||||
; E7 ; 84 ; 8A ; GXB_GND* ; ; ; ; Column I/O ; ; -- ; -- ;
|
||||
; E8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; E9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; E10 ; 66 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; E11 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; E12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; E13 ; 63 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
|
||||
; F1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; F3 ; ; -- ; VCCL_GXB ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; F4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; F5 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; F7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; F8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; F9 ; 64 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; F10 ; 62 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; F11 ; 61 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; F12 ; 58 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
|
||||
; F13 ; 57 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
|
||||
; G1 ; 13 ; QL0 ; GXB_NC ; ; ; ; -- ; ; -- ; -- ;
|
||||
; G2 ; 12 ; QL0 ; GXB_NC ; ; ; ; -- ; ; -- ; -- ;
|
||||
; G3 ; ; -- ; VCCH_GXB ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; G4 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; G5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; G6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; G7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; G8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; G9 ; 60 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; G10 ; 59 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; G11 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; G12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; G13 ; 55 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
|
||||
; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; H3 ; ; -- ; VCCL_GXB ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; H4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; H5 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; H6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; H7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; H9 ; ; -- ; VCCA ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; H10 ; 52 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; H11 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; H12 ; 51 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
|
||||
; H13 ; 56 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
|
||||
; J1 ; 15 ; QL0 ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ;
|
||||
; J2 ; 14 ; QL0 ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ;
|
||||
; J3 ; ; -- ; VCCA_GXB ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; J4 ; ; ; VCCD_PLL ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; J5 ; 19 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
|
||||
; J6 ; 29 ; 3A ; RESETn ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; J7 ; 30 ; 3A ; CLK ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; J8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; J10 ; ; ; VCCD_PLL ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; J11 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; J12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; J13 ; 53 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; K4 ; ; -- ; VCCA ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; K5 ; 18 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
|
||||
; K6 ; 20 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
|
||||
; K7 ; ; 3A ; VCC_CLKIN3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; K8 ; 35 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
|
||||
; K9 ; 36 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; K10 ; 43 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; K11 ; 48 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; K12 ; 47 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; K13 ; 54 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; L1 ; ; ; RREF ; ; ; ; -- ; ; -- ; -- ;
|
||||
; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; L3 ; 16 ; 3 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
|
||||
; L4 ; 21 ; 3 ; ENA ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; L5 ; 27 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; L6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; L7 ; 28 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
|
||||
; L8 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; L9 ; 37 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; L10 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; L11 ; 44 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; L12 ; 50 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; L13 ; 49 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; M2 ; ; -- ; VCCA_GXB ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; M3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
|
||||
; M4 ; 22 ; 3 ; SCLK ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; M6 ; 25 ; 3 ; CPHA ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; M7 ; 31 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
|
||||
; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; M9 ; 38 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; M11 ; 41 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; M13 ; 46 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; N1 ; ; -- ; VCCL_GXB ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; N2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
|
||||
; N3 ; 17 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
|
||||
; N4 ; 23 ; 3 ; CPOL ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; N5 ; 24 ; 3 ; ~ALTERA_NCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; N6 ; 26 ; 3 ; SYNC ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; N7 ; 32 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
|
||||
; N8 ; 33 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; N9 ; 34 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; N10 ; 39 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; N11 ; 40 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; N12 ; 42 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; N13 ; 45 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
+----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
|
||||
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Fitter Resource Utilization by Entity ;
|
||||
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
|
||||
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
|
||||
; |sclk_gen ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |sclk_gen ; work ;
|
||||
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------+
|
||||
; Delay Chain Summary ;
|
||||
+--------+----------+---------------+---------------+-----------------------+-----+------+
|
||||
; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
|
||||
+--------+----------+---------------+---------------+-----------------------+-----+------+
|
||||
; SCLK ; Output ; -- ; -- ; -- ; -- ; -- ;
|
||||
; CPHA ; Input ; -- ; (6) 1313 ps ; -- ; -- ; -- ;
|
||||
; CPOL ; Input ; -- ; (6) 1313 ps ; -- ; -- ; -- ;
|
||||
; CLK ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ;
|
||||
; RESETn ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ;
|
||||
; SYNC ; Input ; (6) 1313 ps ; -- ; -- ; -- ; -- ;
|
||||
; ENA ; Input ; (6) 1313 ps ; -- ; -- ; -- ; -- ;
|
||||
+--------+----------+---------------+---------------+-----------------------+-----+------+
|
||||
|
||||
|
||||
+---------------------------------------------------+
|
||||
; Pad To Core Delay Chain Fanout ;
|
||||
+---------------------+-------------------+---------+
|
||||
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
|
||||
+---------------------+-------------------+---------+
|
||||
; CPHA ; ; ;
|
||||
; - SCLK_3~0 ; 1 ; 6 ;
|
||||
; CPOL ; ; ;
|
||||
; - SCLK_3~0 ; 1 ; 6 ;
|
||||
; CLK ; ; ;
|
||||
; RESETn ; ; ;
|
||||
; SYNC ; ; ;
|
||||
; - Q1 ; 0 ; 6 ;
|
||||
; - T1 ; 0 ; 6 ;
|
||||
; ENA ; ; ;
|
||||
; - T1~0 ; 0 ; 6 ;
|
||||
+---------------------+-------------------+---------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------+
|
||||
; Control Signals ;
|
||||
+--------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
|
||||
+--------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
||||
; CLK ; PIN_J7 ; 2 ; Clock ; yes ; Global Clock ; GCLK17 ; -- ;
|
||||
; RESETn ; PIN_J6 ; 2 ; Async. clear ; yes ; Global Clock ; GCLK19 ; -- ;
|
||||
; SYNC ; PIN_N6 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
||||
+--------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Global & Other Fast Signals ;
|
||||
+--------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
|
||||
; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
|
||||
+--------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
|
||||
; CLK ; PIN_J7 ; 2 ; 0 ; Global Clock ; GCLK17 ; -- ;
|
||||
; RESETn ; PIN_J6 ; 2 ; 0 ; Global Clock ; GCLK19 ; -- ;
|
||||
+--------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
|
||||
|
||||
|
||||
+---------------------------------+
|
||||
; Non-Global High Fan-Out Signals ;
|
||||
+------------+--------------------+
|
||||
; Name ; Fan-Out ;
|
||||
+------------+--------------------+
|
||||
; T1 ; 3 ;
|
||||
; SYNC~input ; 2 ;
|
||||
; ENA~input ; 1 ;
|
||||
; CPOL~input ; 1 ;
|
||||
; CPHA~input ; 1 ;
|
||||
; T1~0 ; 1 ;
|
||||
; SCLK_3~0 ; 1 ;
|
||||
; Q1 ; 1 ;
|
||||
+------------+--------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------+
|
||||
; Other Routing Usage Summary ;
|
||||
+-----------------------------------+----------------------+
|
||||
; Other Routing Resource Type ; Usage ;
|
||||
+-----------------------------------+----------------------+
|
||||
; Block interconnects ; 5 / 42,960 ( < 1 % ) ;
|
||||
; C16 interconnects ; 0 / 1,518 ( 0 % ) ;
|
||||
; C4 interconnects ; 5 / 26,928 ( < 1 % ) ;
|
||||
; GXB block output buffers ; 0 / 1,200 ( 0 % ) ;
|
||||
; Global clocks ; 2 / 20 ( 10 % ) ;
|
||||
; Interquad Reference Clock Outputs ; 0 / 1 ( 0 % ) ;
|
||||
; Interquad TXRX Clocks ; 0 / 8 ( 0 % ) ;
|
||||
; Interquad TXRX PCSRX outputs ; 0 / 4 ( 0 % ) ;
|
||||
; Interquad TXRX PCSTX outputs ; 0 / 4 ( 0 % ) ;
|
||||
; Local interconnects ; 1 / 14,400 ( < 1 % ) ;
|
||||
; R24 interconnects ; 0 / 1,710 ( 0 % ) ;
|
||||
; R4 interconnects ; 2 / 37,740 ( < 1 % ) ;
|
||||
+-----------------------------------+----------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------+
|
||||
; LAB Logic Elements ;
|
||||
+--------------------------------------------+-----------------------------+
|
||||
; Number of Logic Elements (Average = 2.00) ; Number of LABs (Total = 1) ;
|
||||
+--------------------------------------------+-----------------------------+
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 1 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 0 ;
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 0 ;
|
||||
; 13 ; 0 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 0 ;
|
||||
; 16 ; 0 ;
|
||||
+--------------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------+
|
||||
; LAB-wide Signals ;
|
||||
+------------------------------------+-----------------------------+
|
||||
; LAB-wide Signals (Average = 3.00) ; Number of LABs (Total = 1) ;
|
||||
+------------------------------------+-----------------------------+
|
||||
; 1 Async. clear ; 1 ;
|
||||
; 1 Clock ; 1 ;
|
||||
; 1 Clock enable ; 1 ;
|
||||
+------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
; Number of Signals Sourced (Average = 4.00) ; Number of LABs (Total = 1) ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 1 ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced Out ;
|
||||
+-------------------------------------------------+-----------------------------+
|
||||
; Number of Signals Sourced Out (Average = 1.00) ; Number of LABs (Total = 1) ;
|
||||
+-------------------------------------------------+-----------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 1 ;
|
||||
+-------------------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; LAB Distinct Inputs ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
; Number of Distinct Inputs (Average = 6.00) ; Number of LABs (Total = 1) ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 1 ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; I/O Rules Summary ;
|
||||
+----------------------------------+-------+
|
||||
; I/O Rules Statistic ; Total ;
|
||||
+----------------------------------+-------+
|
||||
; Total I/O Rules ; 30 ;
|
||||
; Number of I/O Rules Passed ; 9 ;
|
||||
; Number of I/O Rules Failed ; 0 ;
|
||||
; Number of I/O Rules Unchecked ; 0 ;
|
||||
; Number of I/O Rules Inapplicable ; 21 ;
|
||||
+----------------------------------+-------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; I/O Rules Details ;
|
||||
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
|
||||
; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
|
||||
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
|
||||
; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
|
||||
; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
|
||||
; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
|
||||
; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
|
||||
; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
|
||||
; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
|
||||
; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
|
||||
; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
|
||||
; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
|
||||
; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
|
||||
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; I/O Rules Matrix ;
|
||||
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
|
||||
; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ;
|
||||
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
|
||||
; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 7 ; 7 ; 0 ; 1 ; 0 ; 0 ; 6 ; 0 ; 1 ; 6 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ;
|
||||
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; Total Inapplicable ; 7 ; 7 ; 7 ; 7 ; 7 ; 0 ; 7 ; 7 ; 0 ; 0 ; 7 ; 6 ; 7 ; 7 ; 1 ; 7 ; 6 ; 1 ; 7 ; 7 ; 7 ; 6 ; 7 ; 7 ; 7 ; 7 ; 7 ; 0 ; 7 ; 7 ;
|
||||
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; SCLK ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
||||
; CPHA ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
||||
; CPOL ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
||||
; CLK ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
||||
; RESETn ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
||||
; SYNC ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
||||
; ENA ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
||||
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------+
|
||||
; Fitter Device Options ;
|
||||
+------------------------------------------------------------------+----------------------------+
|
||||
; Option ; Setting ;
|
||||
+------------------------------------------------------------------+----------------------------+
|
||||
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
|
||||
; Enable device-wide reset (DEV_CLRn) ; Off ;
|
||||
; Enable device-wide output enable (DEV_OE) ; Off ;
|
||||
; Enable INIT_DONE output ; Off ;
|
||||
; Configuration scheme ; Active Serial ;
|
||||
; Error detection CRC ; Off ;
|
||||
; Enable input tri-state on active configuration pins in user mode ; Off ;
|
||||
; Active Serial clock source ; 40 MHz Internal Oscillator ;
|
||||
; Configuration Voltage Level ; Auto ;
|
||||
; Force Configuration Voltage Level ; Off ;
|
||||
; nCEO ; As output driving ground ;
|
||||
; Data[0] ; As input tri-stated ;
|
||||
; Data[1]/ASDO ; As input tri-stated ;
|
||||
; Data[7..2] ; Unreserved ;
|
||||
; FLASH_nCE/nCSO ; As input tri-stated ;
|
||||
; DCLK ; As output driving ground ;
|
||||
; Base pin-out file on sameframe device ; Off ;
|
||||
+------------------------------------------------------------------+----------------------------+
|
||||
|
||||
|
||||
+------------------------------------+
|
||||
; Operating Settings and Conditions ;
|
||||
+---------------------------+--------+
|
||||
; Setting ; Value ;
|
||||
+---------------------------+--------+
|
||||
; Nominal Core Voltage ; 1.20 V ;
|
||||
; Low Junction Temperature ; 0 °C ;
|
||||
; High Junction Temperature ; 85 °C ;
|
||||
+---------------------------+--------+
|
||||
|
||||
|
||||
+-----------------+
|
||||
; Fitter Messages ;
|
||||
+-----------------+
|
||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||
Info (119004): Automatically selected device EP4CGX15BF14C6 for design sclk_gen
|
||||
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
|
||||
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
|
||||
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
|
||||
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
|
||||
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
|
||||
Info (176445): Device EP4CGX30BF14C6 is compatible
|
||||
Info (176445): Device EP4CGX22BF14C6 is compatible
|
||||
Info (169124): Fitter converted 5 user pins into dedicated programming pins
|
||||
Info (169125): Pin ~ALTERA_NCEO~ is reserved at location N5
|
||||
Info (169125): Pin ~ALTERA_DATA0~ is reserved at location A5
|
||||
Info (169125): Pin ~ALTERA_ASDO~ is reserved at location B5
|
||||
Info (169125): Pin ~ALTERA_NCSO~ is reserved at location C5
|
||||
Info (169125): Pin ~ALTERA_DCLK~ is reserved at location A4
|
||||
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
|
||||
Critical Warning (169085): No exact pin location assignment(s) for 7 pins of 7 total pins
|
||||
Info (169086): Pin SCLK not assigned to an exact location on the device
|
||||
Info (169086): Pin CPHA not assigned to an exact location on the device
|
||||
Info (169086): Pin CPOL not assigned to an exact location on the device
|
||||
Info (169086): Pin CLK not assigned to an exact location on the device
|
||||
Info (169086): Pin RESETn not assigned to an exact location on the device
|
||||
Info (169086): Pin SYNC not assigned to an exact location on the device
|
||||
Info (169086): Pin ENA not assigned to an exact location on the device
|
||||
Critical Warning (332012): Synopsys Design Constraints File file not found: 'sclk_gen.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
||||
Info (332144): No user constrained base clocks found in the design
|
||||
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
|
||||
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
||||
Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
|
||||
Info (176353): Automatically promoted node CLK~input (placed in PIN J7 (CLK13, DIFFCLK_7n, REFCLK0n))
|
||||
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17
|
||||
Info (176353): Automatically promoted node RESETn~input (placed in PIN J6 (CLK12, DIFFCLK_7p, REFCLK0p))
|
||||
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19
|
||||
Info (176233): Starting register packing
|
||||
Info (176235): Finished register packing
|
||||
Extra Info (176219): No registers were packed into other blocks
|
||||
Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
|
||||
Info (176211): Number of I/O pins in group: 5 (unused VREF, 2.5V VCCIO, 4 input, 1 output, 0 bidirectional)
|
||||
Info (176212): I/O standards used: 2.5 V.
|
||||
Info (176215): I/O bank details before I/O pin placement
|
||||
Info (176214): Statistics of I/O banks
|
||||
Info (176213): I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 0 pins available
|
||||
Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 7 pins available
|
||||
Info (176213): I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 0 pins available
|
||||
Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 14 pins available
|
||||
Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 12 pins available
|
||||
Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 12 pins available
|
||||
Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 14 pins available
|
||||
Info (176213): I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 2 pins available
|
||||
Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 5 pins available
|
||||
Info (176213): I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 0 pins available
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
|
||||
Info (170189): Fitter placement preparation operations beginning
|
||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
|
||||
Info (170191): Fitter placement operations beginning
|
||||
Info (170137): Fitter placement was successful
|
||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
|
||||
Info (170193): Fitter routing operations beginning
|
||||
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
|
||||
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
||||
Info (170201): Optimizations that may affect the design's routability were skipped
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds.
|
||||
Info (334003): Started post-fitting delay annotation
|
||||
Info (334004): Delay annotation completed successfully
|
||||
Info (334003): Started post-fitting delay annotation
|
||||
Info (334004): Delay annotation completed successfully
|
||||
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
|
||||
Warning (169177): 2 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV GX Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
|
||||
Info (169178): Pin CLK uses I/O standard 2.5 V at J7
|
||||
Info (169178): Pin RESETn uses I/O standard 2.5 V at J6
|
||||
Info (144001): Generated suppressed messages file C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/output_files/sclk_gen.fit.smsg
|
||||
Info: Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings
|
||||
Info: Peak virtual memory: 577 megabytes
|
||||
Info: Processing ended: Wed Feb 28 20:25:51 2024
|
||||
Info: Elapsed time: 00:00:06
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
+----------------------------+
|
||||
; Fitter Suppressed Messages ;
|
||||
+----------------------------+
|
||||
The suppressed messages can be found in C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/output_files/sclk_gen.fit.smsg.
|
||||
|
||||
|
||||
@@ -0,0 +1,6 @@
|
||||
Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
|
||||
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
|
||||
Extra Info (176236): Started Fast Input/Output/OE register processing
|
||||
Extra Info (176237): Finished Fast Input/Output/OE register processing
|
||||
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
|
||||
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
|
||||
@@ -0,0 +1,20 @@
|
||||
Fitter Status : Successful - Wed Feb 28 20:25:50 2024
|
||||
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Revision Name : sclk_gen
|
||||
Top-level Entity Name : sclk_gen
|
||||
Family : Cyclone IV GX
|
||||
Device : EP4CGX15BF14C6
|
||||
Timing Models : Final
|
||||
Total logic elements : 2 / 14,400 ( < 1 % )
|
||||
Total combinational functions : 2 / 14,400 ( < 1 % )
|
||||
Dedicated logic registers : 2 / 14,400 ( < 1 % )
|
||||
Total registers : 2
|
||||
Total pins : 7 / 81 ( 9 % )
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 0 / 552,960 ( 0 % )
|
||||
Embedded Multiplier 9-bit elements : 0
|
||||
Total GXB Receiver Channel PCS : 0 / 2 ( 0 % )
|
||||
Total GXB Receiver Channel PMA : 0 / 2 ( 0 % )
|
||||
Total GXB Transmitter Channel PCS : 0 / 2 ( 0 % )
|
||||
Total GXB Transmitter Channel PMA : 0 / 2 ( 0 % )
|
||||
Total PLLs : 0 / 3 ( 0 % )
|
||||
@@ -0,0 +1,124 @@
|
||||
Flow report for sclk_gen
|
||||
Wed Feb 28 20:25:55 2024
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Flow Summary
|
||||
3. Flow Settings
|
||||
4. Flow Non-Default Global Settings
|
||||
5. Flow Elapsed Time
|
||||
6. Flow OS Summary
|
||||
7. Flow Log
|
||||
8. Flow Messages
|
||||
9. Flow Suppressed Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+------------------------------------+-------------------------------------------------+
|
||||
; Flow Status ; Successful - Wed Feb 28 20:25:53 2024 ;
|
||||
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Revision Name ; sclk_gen ;
|
||||
; Top-level Entity Name ; sclk_gen ;
|
||||
; Family ; Cyclone IV GX ;
|
||||
; Total logic elements ; 2 / 14,400 ( < 1 % ) ;
|
||||
; Total combinational functions ; 2 / 14,400 ( < 1 % ) ;
|
||||
; Dedicated logic registers ; 2 / 14,400 ( < 1 % ) ;
|
||||
; Total registers ; 2 ;
|
||||
; Total pins ; 7 / 81 ( 9 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 0 / 552,960 ( 0 % ) ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 ;
|
||||
; Total GXB Receiver Channel PCS ; 0 / 2 ( 0 % ) ;
|
||||
; Total GXB Receiver Channel PMA ; 0 / 2 ( 0 % ) ;
|
||||
; Total GXB Transmitter Channel PCS ; 0 / 2 ( 0 % ) ;
|
||||
; Total GXB Transmitter Channel PMA ; 0 / 2 ( 0 % ) ;
|
||||
; Total PLLs ; 0 / 3 ( 0 % ) ;
|
||||
; Device ; EP4CGX15BF14C6 ;
|
||||
; Timing Models ; Final ;
|
||||
+------------------------------------+-------------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------+
|
||||
; Flow Settings ;
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 02/28/2024 20:25:44 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; sclk_gen ;
|
||||
+-------------------+---------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------+
|
||||
; Flow Non-Default Global Settings ;
|
||||
+-------------------------------------+---------------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+-------------------------------------+---------------------------------+---------------+-------------+------------+
|
||||
; COMPILER_SIGNATURE_ID ; 123953031732614.170914834401572 ; -- ; -- ; -- ;
|
||||
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
|
||||
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
|
||||
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
|
||||
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
||||
+-------------------------------------+---------------------------------+---------------+-------------+------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Flow Elapsed Time ;
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 381 MB ; 00:00:00 ;
|
||||
; Fitter ; 00:00:05 ; 1.0 ; 577 MB ; 00:00:01 ;
|
||||
; Assembler ; 00:00:02 ; 1.0 ; 378 MB ; 00:00:00 ;
|
||||
; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 376 MB ; 00:00:00 ;
|
||||
; Total ; 00:00:10 ; -- ; -- ; 00:00:01 ;
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------+
|
||||
; Flow OS Summary ;
|
||||
+---------------------------+------------------+-----------+------------+----------------+
|
||||
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
||||
+---------------------------+------------------+-----------+------------+----------------+
|
||||
; Analysis & Synthesis ; Surface ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
; Fitter ; Surface ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
; Assembler ; Surface ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
; TimeQuest Timing Analyzer ; Surface ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
+---------------------------+------------------+-----------+------------+----------------+
|
||||
|
||||
|
||||
------------
|
||||
; Flow Log ;
|
||||
------------
|
||||
quartus_map --read_settings_files=on --write_settings_files=off sclk_gen -c sclk_gen
|
||||
quartus_fit --read_settings_files=off --write_settings_files=off sclk_gen -c sclk_gen
|
||||
quartus_asm --read_settings_files=off --write_settings_files=off sclk_gen -c sclk_gen
|
||||
quartus_sta sclk_gen -c sclk_gen
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,8 @@
|
||||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="f306c100133e27e67630"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="EP4CGX15BF14C6" path="sclk_gen.sof" usercode="0xFFFFFFFF"/>
|
||||
</file_info>
|
||||
</sld_project_info>
|
||||
@@ -0,0 +1,245 @@
|
||||
Analysis & Synthesis report for sclk_gen
|
||||
Wed Feb 28 20:25:44 2024
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Analysis & Synthesis Summary
|
||||
3. Analysis & Synthesis Settings
|
||||
4. Parallel Compilation
|
||||
5. Analysis & Synthesis Source Files Read
|
||||
6. Analysis & Synthesis Resource Usage Summary
|
||||
7. Analysis & Synthesis Resource Utilization by Entity
|
||||
8. General Register Statistics
|
||||
9. Elapsed Time Per Partition
|
||||
10. Analysis & Synthesis Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+------------------------------------+-------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Wed Feb 28 20:25:44 2024 ;
|
||||
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Revision Name ; sclk_gen ;
|
||||
; Top-level Entity Name ; sclk_gen ;
|
||||
; Family ; Cyclone IV GX ;
|
||||
; Total logic elements ; 3 ;
|
||||
; Total combinational functions ; 2 ;
|
||||
; Dedicated logic registers ; 2 ;
|
||||
; Total registers ; 2 ;
|
||||
; Total pins ; 7 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 0 ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 ;
|
||||
; Total GXB Receiver Channel PCS ; 0 ;
|
||||
; Total GXB Receiver Channel PMA ; 0 ;
|
||||
; Total GXB Transmitter Channel PCS ; 0 ;
|
||||
; Total GXB Transmitter Channel PMA ; 0 ;
|
||||
; Total PLLs ; 0 ;
|
||||
+------------------------------------+-------------------------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Settings ;
|
||||
+----------------------------------------------------------------------------+--------------------+--------------------+
|
||||
; Option ; Setting ; Default Value ;
|
||||
+----------------------------------------------------------------------------+--------------------+--------------------+
|
||||
; Top-level entity name ; sclk_gen ; sclk_gen ;
|
||||
; Family name ; Cyclone IV GX ; Cyclone IV GX ;
|
||||
; Use smart compilation ; Off ; Off ;
|
||||
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
|
||||
; Enable compact report table ; Off ; Off ;
|
||||
; Restructure Multiplexers ; Auto ; Auto ;
|
||||
; Create Debugging Nodes for IP Cores ; Off ; Off ;
|
||||
; Preserve fewer node names ; On ; On ;
|
||||
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
|
||||
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
|
||||
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
|
||||
; State Machine Processing ; Auto ; Auto ;
|
||||
; Safe State Machine ; Off ; Off ;
|
||||
; Extract Verilog State Machines ; On ; On ;
|
||||
; Extract VHDL State Machines ; On ; On ;
|
||||
; Ignore Verilog initial constructs ; Off ; Off ;
|
||||
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
|
||||
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
|
||||
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
|
||||
; Infer RAMs from Raw Logic ; On ; On ;
|
||||
; Parallel Synthesis ; On ; On ;
|
||||
; DSP Block Balancing ; Auto ; Auto ;
|
||||
; NOT Gate Push-Back ; On ; On ;
|
||||
; Power-Up Don't Care ; On ; On ;
|
||||
; Remove Redundant Logic Cells ; Off ; Off ;
|
||||
; Remove Duplicate Registers ; On ; On ;
|
||||
; Ignore CARRY Buffers ; Off ; Off ;
|
||||
; Ignore CASCADE Buffers ; Off ; Off ;
|
||||
; Ignore GLOBAL Buffers ; Off ; Off ;
|
||||
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
|
||||
; Ignore LCELL Buffers ; Off ; Off ;
|
||||
; Ignore SOFT Buffers ; On ; On ;
|
||||
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
|
||||
; Optimization Technique ; Balanced ; Balanced ;
|
||||
; Carry Chain Length ; 70 ; 70 ;
|
||||
; Auto Carry Chains ; On ; On ;
|
||||
; Auto Open-Drain Pins ; On ; On ;
|
||||
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
|
||||
; Auto ROM Replacement ; On ; On ;
|
||||
; Auto RAM Replacement ; On ; On ;
|
||||
; Auto DSP Block Replacement ; On ; On ;
|
||||
; Auto Shift Register Replacement ; Auto ; Auto ;
|
||||
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
|
||||
; Auto Clock Enable Replacement ; On ; On ;
|
||||
; Strict RAM Replacement ; Off ; Off ;
|
||||
; Allow Synchronous Control Signals ; On ; On ;
|
||||
; Force Use of Synchronous Clear Signals ; Off ; Off ;
|
||||
; Auto RAM Block Balancing ; On ; On ;
|
||||
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
|
||||
; Auto Resource Sharing ; Off ; Off ;
|
||||
; Allow Any RAM Size For Recognition ; Off ; Off ;
|
||||
; Allow Any ROM Size For Recognition ; Off ; Off ;
|
||||
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
|
||||
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
|
||||
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
|
||||
; Timing-Driven Synthesis ; On ; On ;
|
||||
; Report Parameter Settings ; On ; On ;
|
||||
; Report Source Assignments ; On ; On ;
|
||||
; Report Connectivity Checks ; On ; On ;
|
||||
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
|
||||
; Synchronization Register Chain Length ; 2 ; 2 ;
|
||||
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
|
||||
; HDL message level ; Level2 ; Level2 ;
|
||||
; Suppress Register Optimization Related Messages ; Off ; Off ;
|
||||
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
|
||||
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
|
||||
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
|
||||
; Clock MUX Protection ; On ; On ;
|
||||
; Auto Gated Clock Conversion ; Off ; Off ;
|
||||
; Block Design Naming ; Auto ; Auto ;
|
||||
; SDC constraint protection ; Off ; Off ;
|
||||
; Synthesis Effort ; Auto ; Auto ;
|
||||
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
|
||||
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
|
||||
; Analysis & Synthesis Message Level ; Medium ; Medium ;
|
||||
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
|
||||
; Resource Aware Inference For Block RAM ; On ; On ;
|
||||
; Synthesis Seed ; 1 ; 1 ;
|
||||
+----------------------------------------------------------------------------+--------------------+--------------------+
|
||||
|
||||
|
||||
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
|
||||
+-------------------------------------+
|
||||
; Parallel Compilation ;
|
||||
+----------------------------+--------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+--------+
|
||||
; Number detected on machine ; 4 ;
|
||||
; Maximum allowed ; 1 ;
|
||||
+----------------------------+--------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------+---------+
|
||||
; ../src/sclk_gen.v ; yes ; User Verilog HDL File ; C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/src/sclk_gen.v ; ;
|
||||
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------+---------+
|
||||
|
||||
|
||||
+---------------------------------------------+
|
||||
; Analysis & Synthesis Resource Usage Summary ;
|
||||
+--------------------------+------------------+
|
||||
; Resource ; Usage ;
|
||||
+--------------------------+------------------+
|
||||
; I/O pins ; 7 ;
|
||||
; DSP block 9-bit elements ; 0 ;
|
||||
; Maximum fan-out node ; T1 ;
|
||||
; Maximum fan-out ; 3 ;
|
||||
; Total fan-out ; 22 ;
|
||||
; Average fan-out ; 1.22 ;
|
||||
+--------------------------+------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Resource Utilization by Entity ;
|
||||
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
|
||||
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
|
||||
; |sclk_gen ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; |sclk_gen ; work ;
|
||||
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
|
||||
+------------------------------------------------------+
|
||||
; General Register Statistics ;
|
||||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 2 ;
|
||||
; Number of registers using Synchronous Clear ; 0 ;
|
||||
; Number of registers using Synchronous Load ; 0 ;
|
||||
; Number of registers using Asynchronous Clear ; 2 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
; Number of registers using Clock Enable ; 2 ;
|
||||
; Number of registers using Preset ; 0 ;
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
|
||||
+-------------------------------+
|
||||
; Elapsed Time Per Partition ;
|
||||
+----------------+--------------+
|
||||
; Partition Name ; Elapsed Time ;
|
||||
+----------------+--------------+
|
||||
; Top ; 00:00:00 ;
|
||||
+----------------+--------------+
|
||||
|
||||
|
||||
+-------------------------------+
|
||||
; Analysis & Synthesis Messages ;
|
||||
+-------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit Analysis & Synthesis
|
||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Info: Processing started: Wed Feb 28 20:25:43 2024
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sclk_gen -c sclk_gen
|
||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file /users/erdem/desktop/labor_eds/labor_4/aufgabe_6-3/src/sclk_gen.v
|
||||
Info (12023): Found entity 1: sclk_gen
|
||||
Warning (12019): Can't analyze file -- file ../src/d_ff.v is missing
|
||||
Info (12127): Elaborating entity "sclk_gen" for the top level hierarchy
|
||||
Info (286030): Timing-Driven Synthesis is running
|
||||
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
|
||||
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
|
||||
Info (21057): Implemented 10 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 6 input pins
|
||||
Info (21059): Implemented 1 output pins
|
||||
Info (21061): Implemented 3 logic cells
|
||||
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 2 warnings
|
||||
Info: Peak virtual memory: 390 megabytes
|
||||
Info: Processing ended: Wed Feb 28 20:25:44 2024
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
|
||||
|
||||
@@ -0,0 +1,18 @@
|
||||
Analysis & Synthesis Status : Successful - Wed Feb 28 20:25:44 2024
|
||||
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Revision Name : sclk_gen
|
||||
Top-level Entity Name : sclk_gen
|
||||
Family : Cyclone IV GX
|
||||
Total logic elements : 3
|
||||
Total combinational functions : 2
|
||||
Dedicated logic registers : 2
|
||||
Total registers : 2
|
||||
Total pins : 7
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 0
|
||||
Embedded Multiplier 9-bit elements : 0
|
||||
Total GXB Receiver Channel PCS : 0
|
||||
Total GXB Receiver Channel PMA : 0
|
||||
Total GXB Transmitter Channel PCS : 0
|
||||
Total GXB Transmitter Channel PMA : 0
|
||||
Total PLLs : 0
|
||||
@@ -0,0 +1,246 @@
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
--
|
||||
-- This is a Quartus II output file. It is for reporting purposes only, and is
|
||||
-- not intended for use as a Quartus II input file. This file cannot be used
|
||||
-- to make Quartus II pin assignments - for instructions on how to make pin
|
||||
-- assignments, please see Quartus II help.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
-- NC : No Connect. This pin has no internal connection to the device.
|
||||
-- DNU : Do Not Use. This pin MUST NOT be connected.
|
||||
-- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V or 3.0V depending on the requirements of the configuration device.
|
||||
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
|
||||
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
|
||||
-- of its bank.
|
||||
-- Bank 3: 2.5V
|
||||
-- Bank 4: 2.5V
|
||||
-- Bank 5: 2.5V
|
||||
-- Bank 6: 2.5V
|
||||
-- Bank 7: 2.5V
|
||||
-- Bank 8: 2.5V
|
||||
-- Bank 9: 2.5V
|
||||
-- RREF : External reference resistor for the quad, MUST be connected to
|
||||
-- GND via a 2k Ohm resistor.
|
||||
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
|
||||
-- It can also be used to report unused dedicated pins. The connection
|
||||
-- on the board for unused dedicated pins depends on whether this will
|
||||
-- be used in a future design. One example is device migration. When
|
||||
-- using device migration, refer to the device pin-tables. If it is a
|
||||
-- GND pin in the pin table or if it will not be used in a future design
|
||||
-- for another purpose the it MUST be connected to GND. If it is an unused
|
||||
-- dedicated pin, then it can be connected to a valid signal on the board
|
||||
-- (low, high, or toggling) if that signal is required for a different
|
||||
-- revision of the design.
|
||||
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
|
||||
-- This pin should be connected to GND. It may also be connected to a
|
||||
-- valid signal on the board (low, high, or toggling) if that signal
|
||||
-- is required for a different revision of the design.
|
||||
-- GND* : Unused I/O pin. For transceiver I/O banks, connect each pin marked GND*
|
||||
-- either individually through a 10k Ohm resistor to GND or tie all pins
|
||||
-- together and connect through a single 10k Ohm resistor to GND.
|
||||
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
|
||||
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
|
||||
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
|
||||
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
|
||||
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
|
||||
-- GXB_GND* : Unused GXB Receiver or dedicated reference clock pin. This pin
|
||||
-- must be connected to GXB_GND through a 10k Ohm resistor.
|
||||
-- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin
|
||||
-- must not be connected.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
CHIP "sclk_gen" ASSIGNED TO AN: EP4CGX15BF14C6
|
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
TDO : A1 : output : : : 9 :
|
||||
TMS : A2 : input : : : 9 :
|
||||
TDI : A3 : input : : : 9 :
|
||||
~ALTERA_DCLK~ : A4 : output : 2.5 V : : 9 : N
|
||||
~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : input : 2.5 V : : 9 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
|
||||
GND+ : A9 : : : : 7 :
|
||||
GND+ : A10 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7 :
|
||||
GND : B1 : gnd : : : :
|
||||
GND : B2 : gnd : : : :
|
||||
TCK : B3 : input : : : 9 :
|
||||
GND : B4 : gnd : : : :
|
||||
~ALTERA_ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : input : 2.5 V : : 9 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
|
||||
GND : B7 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7 :
|
||||
GND : B9 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 :
|
||||
GND : B12 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 7 :
|
||||
GXB_NC : C1 : : : : QL0 :
|
||||
GXB_NC : C2 : : : : QL0 :
|
||||
VCCIO9 : C3 : power : : 2.5V : 9 :
|
||||
nCE : C4 : : : : 9 :
|
||||
~ALTERA_NCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : input : 2.5 V : : 9 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
|
||||
VCCIO8 : C7 : power : : 2.5V : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 7 :
|
||||
VCCIO7 : C9 : power : : 2.5V : 7 :
|
||||
VCCIO7 : C10 : power : : 2.5V : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 :
|
||||
GND : D1 : gnd : : : :
|
||||
GND : D2 : gnd : : : :
|
||||
VCCD_PLL : D3 : power : : 1.2V : :
|
||||
VCCA : D4 : power : : 2.5V : :
|
||||
nCONFIG : D5 : : : : 9 :
|
||||
GND : D6 : gnd : : : :
|
||||
VCC_CLKIN8A : D7 : power : : 2.5V : 8A :
|
||||
GND : D8 : gnd : : : :
|
||||
VCCA : D9 : power : : 2.5V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 :
|
||||
GXB_GND* : E1 : : : : QL0 :
|
||||
GXB_GND* : E2 : : : : QL0 :
|
||||
GND : E3 : gnd : : : :
|
||||
VCCINT : E4 : power : : 1.2V : :
|
||||
GND : E5 : gnd : : : :
|
||||
GXB_GND* : E6 : : : : 8A :
|
||||
GXB_GND* : E7 : : : : 8A :
|
||||
VCCINT : E8 : power : : 1.2V : :
|
||||
GND : E9 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 6 :
|
||||
VCCIO6 : E11 : power : : 2.5V : 6 :
|
||||
GND : E12 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 6 :
|
||||
GND : F1 : gnd : : : :
|
||||
GND : F2 : gnd : : : :
|
||||
VCCL_GXB : F3 : power : : 1.2V : :
|
||||
GND : F4 : gnd : : : :
|
||||
VCCINT : F5 : power : : 1.2V : :
|
||||
GND : F6 : gnd : : : :
|
||||
VCCINT : F7 : power : : 1.2V : :
|
||||
GND : F8 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 6 :
|
||||
GND+ : F12 : : : : 6 :
|
||||
GND+ : F13 : : : : 6 :
|
||||
GXB_NC : G1 : : : : QL0 :
|
||||
GXB_NC : G2 : : : : QL0 :
|
||||
VCCH_GXB : G3 : power : : 2.5V : :
|
||||
VCCINT : G4 : power : : 1.2V : :
|
||||
GND : G5 : gnd : : : :
|
||||
VCCINT : G6 : power : : 1.2V : :
|
||||
GND : G7 : gnd : : : :
|
||||
VCCINT : G8 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 6 :
|
||||
VCCIO6 : G11 : power : : 2.5V : 6 :
|
||||
GND : G12 : gnd : : : :
|
||||
GND+ : G13 : : : : 5 :
|
||||
GND : H1 : gnd : : : :
|
||||
GND : H2 : gnd : : : :
|
||||
VCCL_GXB : H3 : power : : 1.2V : :
|
||||
GND : H4 : gnd : : : :
|
||||
VCCINT : H5 : power : : 1.2V : :
|
||||
GND : H6 : gnd : : : :
|
||||
VCCINT : H7 : power : : 1.2V : :
|
||||
GND : H8 : gnd : : : :
|
||||
VCCA : H9 : power : : 2.5V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 5 :
|
||||
VCCIO5 : H11 : power : : 2.5V : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 5 :
|
||||
GND+ : H13 : : : : 5 :
|
||||
GXB_GND* : J1 : : : : QL0 :
|
||||
GXB_GND* : J2 : : : : QL0 :
|
||||
VCCA_GXB : J3 : power : : 2.5V : :
|
||||
VCCD_PLL : J4 : power : : 1.2V : :
|
||||
CONF_DONE : J5 : : : : 3 :
|
||||
RESETn : J6 : input : 2.5 V : : 3A : N
|
||||
CLK : J7 : input : 2.5 V : : 3A : N
|
||||
VCCINT : J8 : power : : 1.2V : :
|
||||
GND : J9 : gnd : : : :
|
||||
VCCD_PLL : J10 : power : : 1.2V : :
|
||||
VCCIO5 : J11 : power : : 2.5V : 5 :
|
||||
GND : J12 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 5 :
|
||||
GND : K1 : gnd : : : :
|
||||
GND : K2 : gnd : : : :
|
||||
GND : K3 : gnd : : : :
|
||||
VCCA : K4 : power : : 2.5V : :
|
||||
MSEL0 : K5 : : : : 3 :
|
||||
nSTATUS : K6 : : : : 3 :
|
||||
VCC_CLKIN3A : K7 : power : : 2.5V : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K10 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K11 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K13 : : : : 5 :
|
||||
RREF : L1 : : : : :
|
||||
GND : L2 : gnd : : : :
|
||||
MSEL2 : L3 : : : : 3 :
|
||||
ENA : L4 : input : 2.5 V : : 3 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 3 :
|
||||
VCCIO3 : L6 : power : : 2.5V : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 3 :
|
||||
VCCIO4 : L8 : power : : 2.5V : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 4 :
|
||||
VCCIO4 : L10 : power : : 2.5V : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L11 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L12 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L13 : : : : 5 :
|
||||
GND : M1 : gnd : : : :
|
||||
VCCA_GXB : M2 : power : : 2.5V : :
|
||||
NC : M3 : : : : :
|
||||
SCLK : M4 : output : 2.5 V : : 3 : N
|
||||
GND : M5 : gnd : : : :
|
||||
CPHA : M6 : input : 2.5 V : : 3 : N
|
||||
GND+ : M7 : : : : 4 :
|
||||
GND : M8 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 4 :
|
||||
GND : M10 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M11 : : : : 4 :
|
||||
GND : M12 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M13 : : : : 5 :
|
||||
VCCL_GXB : N1 : power : : 1.2V : :
|
||||
NC : N2 : : : : :
|
||||
MSEL1 : N3 : : : : 3 :
|
||||
CPOL : N4 : input : 2.5 V : : 3 : N
|
||||
~ALTERA_NCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : N5 : output : 2.5 V : : 3 : N
|
||||
SYNC : N6 : input : 2.5 V : : 3 : N
|
||||
GND+ : N7 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N10 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N11 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N12 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N13 : : : : 5 :
|
||||
Binary file not shown.
@@ -0,0 +1,869 @@
|
||||
TimeQuest Timing Analyzer report for sclk_gen
|
||||
Wed Feb 28 20:25:55 2024
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. TimeQuest Timing Analyzer Summary
|
||||
3. Parallel Compilation
|
||||
4. Clocks
|
||||
5. Slow 1200mV 85C Model Fmax Summary
|
||||
6. Timing Closure Recommendations
|
||||
7. Slow 1200mV 85C Model Setup Summary
|
||||
8. Slow 1200mV 85C Model Hold Summary
|
||||
9. Slow 1200mV 85C Model Recovery Summary
|
||||
10. Slow 1200mV 85C Model Removal Summary
|
||||
11. Slow 1200mV 85C Model Minimum Pulse Width Summary
|
||||
12. Slow 1200mV 85C Model Setup: 'CLK'
|
||||
13. Slow 1200mV 85C Model Hold: 'CLK'
|
||||
14. Slow 1200mV 85C Model Minimum Pulse Width: 'CLK'
|
||||
15. Setup Times
|
||||
16. Hold Times
|
||||
17. Clock to Output Times
|
||||
18. Minimum Clock to Output Times
|
||||
19. Propagation Delay
|
||||
20. Minimum Propagation Delay
|
||||
21. Slow 1200mV 85C Model Metastability Report
|
||||
22. Slow 1200mV 0C Model Fmax Summary
|
||||
23. Slow 1200mV 0C Model Setup Summary
|
||||
24. Slow 1200mV 0C Model Hold Summary
|
||||
25. Slow 1200mV 0C Model Recovery Summary
|
||||
26. Slow 1200mV 0C Model Removal Summary
|
||||
27. Slow 1200mV 0C Model Minimum Pulse Width Summary
|
||||
28. Slow 1200mV 0C Model Setup: 'CLK'
|
||||
29. Slow 1200mV 0C Model Hold: 'CLK'
|
||||
30. Slow 1200mV 0C Model Minimum Pulse Width: 'CLK'
|
||||
31. Setup Times
|
||||
32. Hold Times
|
||||
33. Clock to Output Times
|
||||
34. Minimum Clock to Output Times
|
||||
35. Propagation Delay
|
||||
36. Minimum Propagation Delay
|
||||
37. Slow 1200mV 0C Model Metastability Report
|
||||
38. Fast 1200mV 0C Model Setup Summary
|
||||
39. Fast 1200mV 0C Model Hold Summary
|
||||
40. Fast 1200mV 0C Model Recovery Summary
|
||||
41. Fast 1200mV 0C Model Removal Summary
|
||||
42. Fast 1200mV 0C Model Minimum Pulse Width Summary
|
||||
43. Fast 1200mV 0C Model Setup: 'CLK'
|
||||
44. Fast 1200mV 0C Model Hold: 'CLK'
|
||||
45. Fast 1200mV 0C Model Minimum Pulse Width: 'CLK'
|
||||
46. Setup Times
|
||||
47. Hold Times
|
||||
48. Clock to Output Times
|
||||
49. Minimum Clock to Output Times
|
||||
50. Propagation Delay
|
||||
51. Minimum Propagation Delay
|
||||
52. Fast 1200mV 0C Model Metastability Report
|
||||
53. Multicorner Timing Analysis Summary
|
||||
54. Setup Times
|
||||
55. Hold Times
|
||||
56. Clock to Output Times
|
||||
57. Minimum Clock to Output Times
|
||||
58. Progagation Delay
|
||||
59. Minimum Progagation Delay
|
||||
60. Board Trace Model Assignments
|
||||
61. Input Transition Times
|
||||
62. Signal Integrity Metrics (Slow 1200mv 0c Model)
|
||||
63. Signal Integrity Metrics (Slow 1200mv 85c Model)
|
||||
64. Signal Integrity Metrics (Fast 1200mv 0c Model)
|
||||
65. Setup Transfers
|
||||
66. Hold Transfers
|
||||
67. Report TCCS
|
||||
68. Report RSKM
|
||||
69. Unconstrained Paths
|
||||
70. TimeQuest Timing Analyzer Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------+
|
||||
; TimeQuest Timing Analyzer Summary ;
|
||||
+--------------------+-------------------------------------------------------------------+
|
||||
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
|
||||
; Revision Name ; sclk_gen ;
|
||||
; Device Family ; Cyclone IV GX ;
|
||||
; Device Name ; EP4CGX15BF14C6 ;
|
||||
; Timing Models ; Final ;
|
||||
; Delay Model ; Combined ;
|
||||
; Rise/Fall Delays ; Enabled ;
|
||||
+--------------------+-------------------------------------------------------------------+
|
||||
|
||||
|
||||
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
|
||||
+-------------------------------------+
|
||||
; Parallel Compilation ;
|
||||
+----------------------------+--------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+--------+
|
||||
; Number detected on machine ; 4 ;
|
||||
; Maximum allowed ; 1 ;
|
||||
+----------------------------+--------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Clocks ;
|
||||
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
|
||||
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
|
||||
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
|
||||
; CLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { CLK } ;
|
||||
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------+
|
||||
; Slow 1200mV 85C Model Fmax Summary ;
|
||||
+-------------+-----------------+------------+---------------------------------------------------------------+
|
||||
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
||||
+-------------+-----------------+------------+---------------------------------------------------------------+
|
||||
; 1101.32 MHz ; 250.0 MHz ; CLK ; limit due to minimum period restriction (max I/O toggle rate) ;
|
||||
+-------------+-----------------+------------+---------------------------------------------------------------+
|
||||
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
||||
|
||||
|
||||
----------------------------------
|
||||
; Timing Closure Recommendations ;
|
||||
----------------------------------
|
||||
HTML report is unavailable in plain text report export.
|
||||
|
||||
|
||||
+-------------------------------------+
|
||||
; Slow 1200mV 85C Model Setup Summary ;
|
||||
+-------+-------+---------------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+-------+---------------------+
|
||||
; CLK ; 0.092 ; 0.000 ;
|
||||
+-------+-------+---------------------+
|
||||
|
||||
|
||||
+------------------------------------+
|
||||
; Slow 1200mV 85C Model Hold Summary ;
|
||||
+-------+-------+--------------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+-------+--------------------+
|
||||
; CLK ; 0.359 ; 0.000 ;
|
||||
+-------+-------+--------------------+
|
||||
|
||||
|
||||
------------------------------------------
|
||||
; Slow 1200mV 85C Model Recovery Summary ;
|
||||
------------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-----------------------------------------
|
||||
; Slow 1200mV 85C Model Removal Summary ;
|
||||
-----------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
+---------------------------------------------------+
|
||||
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
|
||||
+-------+--------+----------------------------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+--------+----------------------------------+
|
||||
; CLK ; -3.000 ; -5.000 ;
|
||||
+-------+--------+----------------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------+
|
||||
; Slow 1200mV 85C Model Setup: 'CLK' ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
; 0.092 ; T1 ; Q1 ; CLK ; CLK ; 1.000 ; -0.064 ; 0.839 ;
|
||||
; 0.272 ; T1 ; T1 ; CLK ; CLK ; 1.000 ; -0.064 ; 0.659 ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------+
|
||||
; Slow 1200mV 85C Model Hold: 'CLK' ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
; 0.359 ; T1 ; T1 ; CLK ; CLK ; 0.000 ; 0.064 ; 0.580 ;
|
||||
; 0.524 ; T1 ; Q1 ; CLK ; CLK ; 0.000 ; 0.064 ; 0.745 ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------+
|
||||
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLK' ;
|
||||
+--------+--------------+----------------+------------------+-------+------------+---------------------------+
|
||||
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
||||
+--------+--------------+----------------+------------------+-------+------------+---------------------------+
|
||||
; -3.000 ; 1.000 ; 4.000 ; Port Rate ; CLK ; Rise ; CLK ;
|
||||
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLK ; Rise ; Q1 ;
|
||||
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLK ; Rise ; T1 ;
|
||||
; 0.214 ; 0.398 ; 0.184 ; Low Pulse Width ; CLK ; Rise ; Q1 ;
|
||||
; 0.214 ; 0.398 ; 0.184 ; Low Pulse Width ; CLK ; Rise ; T1 ;
|
||||
; 0.326 ; 0.326 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; CLK~input|o ;
|
||||
; 0.337 ; 0.337 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; CLK~inputclkctrl|inclk[0] ;
|
||||
; 0.337 ; 0.337 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; CLK~inputclkctrl|outclk ;
|
||||
; 0.374 ; 0.374 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; Q1|clk ;
|
||||
; 0.374 ; 0.374 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; T1|clk ;
|
||||
; 0.386 ; 0.602 ; 0.216 ; High Pulse Width ; CLK ; Rise ; Q1 ;
|
||||
; 0.386 ; 0.602 ; 0.216 ; High Pulse Width ; CLK ; Rise ; T1 ;
|
||||
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; CLK ; Rise ; CLK~input|i ;
|
||||
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; CLK~input|i ;
|
||||
; 0.624 ; 0.624 ; 0.000 ; High Pulse Width ; CLK ; Rise ; Q1|clk ;
|
||||
; 0.624 ; 0.624 ; 0.000 ; High Pulse Width ; CLK ; Rise ; T1|clk ;
|
||||
; 0.662 ; 0.662 ; 0.000 ; High Pulse Width ; CLK ; Rise ; CLK~inputclkctrl|inclk[0] ;
|
||||
; 0.662 ; 0.662 ; 0.000 ; High Pulse Width ; CLK ; Rise ; CLK~inputclkctrl|outclk ;
|
||||
; 0.674 ; 0.674 ; 0.000 ; High Pulse Width ; CLK ; Rise ; CLK~input|o ;
|
||||
+--------+--------------+----------------+------------------+-------+------------+---------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Setup Times ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; ENA ; CLK ; 1.515 ; 1.935 ; Rise ; CLK ;
|
||||
; SYNC ; CLK ; 2.135 ; 2.548 ; Rise ; CLK ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------+
|
||||
; Hold Times ;
|
||||
+-----------+------------+--------+--------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+--------+--------+------------+-----------------+
|
||||
; ENA ; CLK ; -1.133 ; -1.532 ; Rise ; CLK ;
|
||||
; SYNC ; CLK ; -1.849 ; -2.251 ; Rise ; CLK ;
|
||||
+-----------+------------+--------+--------+------------+-----------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Clock to Output Times ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; SCLK ; CLK ; 6.218 ; 6.063 ; Rise ; CLK ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Minimum Clock to Output Times ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; SCLK ; CLK ; 5.699 ; 5.578 ; Rise ; CLK ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------+
|
||||
; Propagation Delay ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
; CPHA ; SCLK ; 6.935 ; 6.809 ; 7.355 ; 7.220 ;
|
||||
; CPOL ; SCLK ; 7.002 ; 6.904 ; 7.448 ; 7.336 ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
|
||||
|
||||
+----------------------------------------------------------+
|
||||
; Minimum Propagation Delay ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
; CPHA ; SCLK ; 6.703 ; 6.578 ; 7.114 ; 6.980 ;
|
||||
; CPOL ; SCLK ; 6.719 ; 6.625 ; 7.174 ; 7.008 ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
|
||||
|
||||
----------------------------------------------
|
||||
; Slow 1200mV 85C Model Metastability Report ;
|
||||
----------------------------------------------
|
||||
No synchronizer chains to report.
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------+
|
||||
; Slow 1200mV 0C Model Fmax Summary ;
|
||||
+------------+-----------------+------------+---------------------------------------------------------------+
|
||||
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
||||
+------------+-----------------+------------+---------------------------------------------------------------+
|
||||
; 1228.5 MHz ; 250.0 MHz ; CLK ; limit due to minimum period restriction (max I/O toggle rate) ;
|
||||
+------------+-----------------+------------+---------------------------------------------------------------+
|
||||
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
||||
|
||||
|
||||
+------------------------------------+
|
||||
; Slow 1200mV 0C Model Setup Summary ;
|
||||
+-------+-------+--------------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+-------+--------------------+
|
||||
; CLK ; 0.186 ; 0.000 ;
|
||||
+-------+-------+--------------------+
|
||||
|
||||
|
||||
+-----------------------------------+
|
||||
; Slow 1200mV 0C Model Hold Summary ;
|
||||
+-------+-------+-------------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+-------+-------------------+
|
||||
; CLK ; 0.318 ; 0.000 ;
|
||||
+-------+-------+-------------------+
|
||||
|
||||
|
||||
-----------------------------------------
|
||||
; Slow 1200mV 0C Model Recovery Summary ;
|
||||
-----------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
----------------------------------------
|
||||
; Slow 1200mV 0C Model Removal Summary ;
|
||||
----------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
+--------------------------------------------------+
|
||||
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
|
||||
+-------+--------+---------------------------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+--------+---------------------------------+
|
||||
; CLK ; -3.000 ; -5.000 ;
|
||||
+-------+--------+---------------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------+
|
||||
; Slow 1200mV 0C Model Setup: 'CLK' ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
; 0.186 ; T1 ; Q1 ; CLK ; CLK ; 1.000 ; -0.057 ; 0.752 ;
|
||||
; 0.355 ; T1 ; T1 ; CLK ; CLK ; 1.000 ; -0.057 ; 0.583 ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------+
|
||||
; Slow 1200mV 0C Model Hold: 'CLK' ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
; 0.318 ; T1 ; T1 ; CLK ; CLK ; 0.000 ; 0.057 ; 0.519 ;
|
||||
; 0.474 ; T1 ; Q1 ; CLK ; CLK ; 0.000 ; 0.057 ; 0.675 ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------+
|
||||
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLK' ;
|
||||
+--------+--------------+----------------+------------------+-------+------------+---------------------------+
|
||||
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
||||
+--------+--------------+----------------+------------------+-------+------------+---------------------------+
|
||||
; -3.000 ; 1.000 ; 4.000 ; Port Rate ; CLK ; Rise ; CLK ;
|
||||
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLK ; Rise ; Q1 ;
|
||||
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLK ; Rise ; T1 ;
|
||||
; 0.218 ; 0.402 ; 0.184 ; Low Pulse Width ; CLK ; Rise ; Q1 ;
|
||||
; 0.218 ; 0.402 ; 0.184 ; Low Pulse Width ; CLK ; Rise ; T1 ;
|
||||
; 0.344 ; 0.344 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; CLK~input|o ;
|
||||
; 0.346 ; 0.346 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; CLK~inputclkctrl|inclk[0] ;
|
||||
; 0.346 ; 0.346 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; CLK~inputclkctrl|outclk ;
|
||||
; 0.378 ; 0.378 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; Q1|clk ;
|
||||
; 0.378 ; 0.378 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; T1|clk ;
|
||||
; 0.381 ; 0.597 ; 0.216 ; High Pulse Width ; CLK ; Rise ; Q1 ;
|
||||
; 0.381 ; 0.597 ; 0.216 ; High Pulse Width ; CLK ; Rise ; T1 ;
|
||||
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; CLK ; Rise ; CLK~input|i ;
|
||||
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; CLK~input|i ;
|
||||
; 0.621 ; 0.621 ; 0.000 ; High Pulse Width ; CLK ; Rise ; Q1|clk ;
|
||||
; 0.621 ; 0.621 ; 0.000 ; High Pulse Width ; CLK ; Rise ; T1|clk ;
|
||||
; 0.654 ; 0.654 ; 0.000 ; High Pulse Width ; CLK ; Rise ; CLK~inputclkctrl|inclk[0] ;
|
||||
; 0.654 ; 0.654 ; 0.000 ; High Pulse Width ; CLK ; Rise ; CLK~inputclkctrl|outclk ;
|
||||
; 0.656 ; 0.656 ; 0.000 ; High Pulse Width ; CLK ; Rise ; CLK~input|o ;
|
||||
+--------+--------------+----------------+------------------+-------+------------+---------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Setup Times ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; ENA ; CLK ; 1.264 ; 1.604 ; Rise ; CLK ;
|
||||
; SYNC ; CLK ; 1.841 ; 2.169 ; Rise ; CLK ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------+
|
||||
; Hold Times ;
|
||||
+-----------+------------+--------+--------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+--------+--------+------------+-----------------+
|
||||
; ENA ; CLK ; -0.924 ; -1.250 ; Rise ; CLK ;
|
||||
; SYNC ; CLK ; -1.586 ; -1.906 ; Rise ; CLK ;
|
||||
+-----------+------------+--------+--------+------------+-----------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Clock to Output Times ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; SCLK ; CLK ; 5.541 ; 5.401 ; Rise ; CLK ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Minimum Clock to Output Times ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; SCLK ; CLK ; 5.080 ; 4.968 ; Rise ; CLK ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------+
|
||||
; Propagation Delay ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
; CPHA ; SCLK ; 6.105 ; 5.989 ; 6.443 ; 6.319 ;
|
||||
; CPOL ; SCLK ; 6.167 ; 6.077 ; 6.525 ; 6.421 ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
|
||||
|
||||
+----------------------------------------------------------+
|
||||
; Minimum Propagation Delay ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
; CPHA ; SCLK ; 5.900 ; 5.786 ; 6.229 ; 6.109 ;
|
||||
; CPOL ; SCLK ; 5.916 ; 5.827 ; 6.281 ; 6.132 ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
|
||||
|
||||
---------------------------------------------
|
||||
; Slow 1200mV 0C Model Metastability Report ;
|
||||
---------------------------------------------
|
||||
No synchronizer chains to report.
|
||||
|
||||
|
||||
+------------------------------------+
|
||||
; Fast 1200mV 0C Model Setup Summary ;
|
||||
+-------+-------+--------------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+-------+--------------------+
|
||||
; CLK ; 0.506 ; 0.000 ;
|
||||
+-------+-------+--------------------+
|
||||
|
||||
|
||||
+-----------------------------------+
|
||||
; Fast 1200mV 0C Model Hold Summary ;
|
||||
+-------+-------+-------------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+-------+-------------------+
|
||||
; CLK ; 0.193 ; 0.000 ;
|
||||
+-------+-------+-------------------+
|
||||
|
||||
|
||||
-----------------------------------------
|
||||
; Fast 1200mV 0C Model Recovery Summary ;
|
||||
-----------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
----------------------------------------
|
||||
; Fast 1200mV 0C Model Removal Summary ;
|
||||
----------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
+--------------------------------------------------+
|
||||
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
|
||||
+-------+--------+---------------------------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+--------+---------------------------------+
|
||||
; CLK ; -3.000 ; -5.052 ;
|
||||
+-------+--------+---------------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------+
|
||||
; Fast 1200mV 0C Model Setup: 'CLK' ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
; 0.506 ; T1 ; Q1 ; CLK ; CLK ; 1.000 ; -0.037 ; 0.444 ;
|
||||
; 0.591 ; T1 ; T1 ; CLK ; CLK ; 1.000 ; -0.037 ; 0.359 ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------+
|
||||
; Fast 1200mV 0C Model Hold: 'CLK' ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
; 0.193 ; T1 ; T1 ; CLK ; CLK ; 0.000 ; 0.037 ; 0.314 ;
|
||||
; 0.273 ; T1 ; Q1 ; CLK ; CLK ; 0.000 ; 0.037 ; 0.394 ;
|
||||
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------+
|
||||
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLK' ;
|
||||
+--------+--------------+----------------+------------------+-------+------------+---------------------------+
|
||||
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
||||
+--------+--------------+----------------+------------------+-------+------------+---------------------------+
|
||||
; -3.000 ; 1.000 ; 4.000 ; Port Rate ; CLK ; Rise ; CLK ;
|
||||
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLK ; Rise ; Q1 ;
|
||||
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLK ; Rise ; T1 ;
|
||||
; -0.026 ; 0.158 ; 0.184 ; Low Pulse Width ; CLK ; Rise ; Q1 ;
|
||||
; -0.026 ; 0.158 ; 0.184 ; Low Pulse Width ; CLK ; Rise ; T1 ;
|
||||
; 0.125 ; 0.125 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; CLK~input|o ;
|
||||
; 0.139 ; 0.139 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; CLK~inputclkctrl|inclk[0] ;
|
||||
; 0.139 ; 0.139 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; CLK~inputclkctrl|outclk ;
|
||||
; 0.153 ; 0.153 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; Q1|clk ;
|
||||
; 0.153 ; 0.153 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; T1|clk ;
|
||||
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; CLK ; Rise ; CLK~input|i ;
|
||||
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; CLK~input|i ;
|
||||
; 0.625 ; 0.841 ; 0.216 ; High Pulse Width ; CLK ; Rise ; Q1 ;
|
||||
; 0.625 ; 0.841 ; 0.216 ; High Pulse Width ; CLK ; Rise ; T1 ;
|
||||
; 0.846 ; 0.846 ; 0.000 ; High Pulse Width ; CLK ; Rise ; Q1|clk ;
|
||||
; 0.846 ; 0.846 ; 0.000 ; High Pulse Width ; CLK ; Rise ; T1|clk ;
|
||||
; 0.861 ; 0.861 ; 0.000 ; High Pulse Width ; CLK ; Rise ; CLK~inputclkctrl|inclk[0] ;
|
||||
; 0.861 ; 0.861 ; 0.000 ; High Pulse Width ; CLK ; Rise ; CLK~inputclkctrl|outclk ;
|
||||
; 0.875 ; 0.875 ; 0.000 ; High Pulse Width ; CLK ; Rise ; CLK~input|o ;
|
||||
+--------+--------------+----------------+------------------+-------+------------+---------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Setup Times ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; ENA ; CLK ; 0.841 ; 1.401 ; Rise ; CLK ;
|
||||
; SYNC ; CLK ; 1.195 ; 1.751 ; Rise ; CLK ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------+
|
||||
; Hold Times ;
|
||||
+-----------+------------+--------+--------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+--------+--------+------------+-----------------+
|
||||
; ENA ; CLK ; -0.625 ; -1.172 ; Rise ; CLK ;
|
||||
; SYNC ; CLK ; -1.030 ; -1.578 ; Rise ; CLK ;
|
||||
+-----------+------------+--------+--------+------------+-----------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Clock to Output Times ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; SCLK ; CLK ; 3.619 ; 3.584 ; Rise ; CLK ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Minimum Clock to Output Times ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; SCLK ; CLK ; 3.311 ; 3.306 ; Rise ; CLK ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------+
|
||||
; Propagation Delay ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
; CPHA ; SCLK ; 4.015 ; 4.005 ; 4.582 ; 4.565 ;
|
||||
; CPOL ; SCLK ; 4.067 ; 4.068 ; 4.642 ; 4.630 ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
|
||||
|
||||
+----------------------------------------------------------+
|
||||
; Minimum Propagation Delay ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
; CPHA ; SCLK ; 3.877 ; 3.868 ; 4.437 ; 4.421 ;
|
||||
; CPOL ; SCLK ; 3.900 ; 3.902 ; 4.478 ; 4.436 ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
|
||||
|
||||
---------------------------------------------
|
||||
; Fast 1200mV 0C Model Metastability Report ;
|
||||
---------------------------------------------
|
||||
No synchronizer chains to report.
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------+
|
||||
; Multicorner Timing Analysis Summary ;
|
||||
+------------------+-------+-------+----------+---------+---------------------+
|
||||
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
|
||||
+------------------+-------+-------+----------+---------+---------------------+
|
||||
; Worst-case Slack ; 0.092 ; 0.193 ; N/A ; N/A ; -3.000 ;
|
||||
; CLK ; 0.092 ; 0.193 ; N/A ; N/A ; -3.000 ;
|
||||
; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; -5.052 ;
|
||||
; CLK ; 0.000 ; 0.000 ; N/A ; N/A ; -5.052 ;
|
||||
+------------------+-------+-------+----------+---------+---------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Setup Times ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; ENA ; CLK ; 1.515 ; 1.935 ; Rise ; CLK ;
|
||||
; SYNC ; CLK ; 2.135 ; 2.548 ; Rise ; CLK ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------+
|
||||
; Hold Times ;
|
||||
+-----------+------------+--------+--------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+--------+--------+------------+-----------------+
|
||||
; ENA ; CLK ; -0.625 ; -1.172 ; Rise ; CLK ;
|
||||
; SYNC ; CLK ; -1.030 ; -1.578 ; Rise ; CLK ;
|
||||
+-----------+------------+--------+--------+------------+-----------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Clock to Output Times ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; SCLK ; CLK ; 6.218 ; 6.063 ; Rise ; CLK ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------+
|
||||
; Minimum Clock to Output Times ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
; SCLK ; CLK ; 3.311 ; 3.306 ; Rise ; CLK ;
|
||||
+-----------+------------+-------+-------+------------+-----------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------+
|
||||
; Progagation Delay ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
; CPHA ; SCLK ; 6.935 ; 6.809 ; 7.355 ; 7.220 ;
|
||||
; CPOL ; SCLK ; 7.002 ; 6.904 ; 7.448 ; 7.336 ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
|
||||
|
||||
+----------------------------------------------------------+
|
||||
; Minimum Progagation Delay ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
; CPHA ; SCLK ; 3.877 ; 3.868 ; 4.437 ; 4.421 ;
|
||||
; CPOL ; SCLK ; 3.900 ; 3.902 ; 4.478 ; 4.436 ;
|
||||
+------------+-------------+-------+-------+-------+-------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Board Trace Model Assignments ;
|
||||
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||||
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
|
||||
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||||
; SCLK ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; ~ALTERA_NCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; Input Transition Times ;
|
||||
+----------------+--------------+-----------------+-----------------+
|
||||
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
|
||||
+----------------+--------------+-----------------+-----------------+
|
||||
; CPHA ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; CPOL ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; CLK ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; RESETn ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; SYNC ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENA ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ~ALTERA_ASDO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ~ALTERA_NCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
+----------------+--------------+-----------------+-----------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; SCLK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.29e-09 V ; 2.39 V ; -0.00339 V ; 0.206 V ; 0.007 V ; 2.77e-10 s ; 3.24e-10 s ; Yes ; Yes ; 2.32 V ; 7.29e-09 V ; 2.39 V ; -0.00339 V ; 0.206 V ; 0.007 V ; 2.77e-10 s ; 3.24e-10 s ; Yes ; Yes ;
|
||||
; ~ALTERA_NCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.76e-09 V ; 2.4 V ; -0.034 V ; 0.102 V ; 0.065 V ; 2.49e-10 s ; 3.49e-10 s ; Yes ; Yes ; 2.32 V ; 4.76e-09 V ; 2.4 V ; -0.034 V ; 0.102 V ; 0.065 V ; 2.49e-10 s ; 3.49e-10 s ; Yes ; Yes ;
|
||||
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.94e-09 V ; 2.39 V ; -0.034 V ; 0.156 V ; 0.09 V ; 2.68e-10 s ; 2.6e-10 s ; Yes ; Yes ; 2.32 V ; 5.94e-09 V ; 2.39 V ; -0.034 V ; 0.156 V ; 0.09 V ; 2.68e-10 s ; 2.6e-10 s ; Yes ; Yes ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; SCLK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.21e-06 V ; 2.37 V ; -0.00606 V ; 0.107 V ; 0.021 V ; 4.26e-10 s ; 4.03e-10 s ; Yes ; Yes ; 2.32 V ; 1.21e-06 V ; 2.37 V ; -0.00606 V ; 0.107 V ; 0.021 V ; 4.26e-10 s ; 4.03e-10 s ; Yes ; Yes ;
|
||||
; ~ALTERA_NCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.93e-07 V ; 2.37 V ; -0.0278 V ; 0.106 V ; 0.115 V ; 2.69e-10 s ; 4.05e-10 s ; Yes ; Yes ; 2.32 V ; 7.93e-07 V ; 2.37 V ; -0.0278 V ; 0.106 V ; 0.115 V ; 2.69e-10 s ; 4.05e-10 s ; Yes ; Yes ;
|
||||
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.76e-07 V ; 2.36 V ; -0.00527 V ; 0.088 V ; 0.006 V ; 4.05e-10 s ; 3.35e-10 s ; Yes ; Yes ; 2.32 V ; 9.76e-07 V ; 2.36 V ; -0.00527 V ; 0.088 V ; 0.006 V ; 4.05e-10 s ; 3.35e-10 s ; Yes ; Yes ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; SCLK ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.66e-08 V ; 2.73 V ; -0.0205 V ; 0.17 V ; 0.027 V ; 2.58e-10 s ; 2.57e-10 s ; Yes ; Yes ; 2.62 V ; 4.66e-08 V ; 2.73 V ; -0.0205 V ; 0.17 V ; 0.027 V ; 2.58e-10 s ; 2.57e-10 s ; Yes ; Yes ;
|
||||
; ~ALTERA_NCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.06e-08 V ; 2.86 V ; -0.0341 V ; 0.364 V ; 0.046 V ; 1.17e-10 s ; 2.6e-10 s ; No ; Yes ; 2.62 V ; 3.06e-08 V ; 2.86 V ; -0.0341 V ; 0.364 V ; 0.046 V ; 1.17e-10 s ; 2.6e-10 s ; No ; Yes ;
|
||||
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.81e-08 V ; 2.72 V ; -0.0533 V ; 0.144 V ; 0.088 V ; 2.55e-10 s ; 2.14e-10 s ; Yes ; Yes ; 2.62 V ; 3.81e-08 V ; 2.72 V ; -0.0533 V ; 0.144 V ; 0.088 V ; 2.55e-10 s ; 2.14e-10 s ; Yes ; Yes ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; Setup Transfers ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; CLK ; CLK ; 2 ; 0 ; 0 ; 0 ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; Hold Transfers ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; CLK ; CLK ; 2 ; 0 ; 0 ; 0 ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||||
|
||||
|
||||
---------------
|
||||
; Report TCCS ;
|
||||
---------------
|
||||
No dedicated SERDES Transmitter circuitry present in device or used in design
|
||||
|
||||
|
||||
---------------
|
||||
; Report RSKM ;
|
||||
---------------
|
||||
No dedicated SERDES Receiver circuitry present in device or used in design
|
||||
|
||||
|
||||
+------------------------------------------------+
|
||||
; Unconstrained Paths ;
|
||||
+---------------------------------+-------+------+
|
||||
; Property ; Setup ; Hold ;
|
||||
+---------------------------------+-------+------+
|
||||
; Illegal Clocks ; 0 ; 0 ;
|
||||
; Unconstrained Clocks ; 0 ; 0 ;
|
||||
; Unconstrained Input Ports ; 5 ; 5 ;
|
||||
; Unconstrained Input Port Paths ; 7 ; 7 ;
|
||||
; Unconstrained Output Ports ; 1 ; 1 ;
|
||||
; Unconstrained Output Port Paths ; 4 ; 4 ;
|
||||
+---------------------------------+-------+------+
|
||||
|
||||
|
||||
+------------------------------------+
|
||||
; TimeQuest Timing Analyzer Messages ;
|
||||
+------------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
|
||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Info: Processing started: Wed Feb 28 20:25:53 2024
|
||||
Info: Command: quartus_sta sclk_gen -c sclk_gen
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
|
||||
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
|
||||
Critical Warning (332012): Synopsys Design Constraints File file not found: 'sclk_gen.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
||||
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
||||
Info (332105): Deriving Clocks
|
||||
Info (332105): create_clock -period 1.000 -name CLK CLK
|
||||
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
|
||||
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
|
||||
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
||||
Info: Analyzing Slow 1200mV 85C Model
|
||||
Info (332146): Worst-case setup slack is 0.092
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= ============= =====================
|
||||
Info (332119): 0.092 0.000 CLK
|
||||
Info (332146): Worst-case hold slack is 0.359
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= ============= =====================
|
||||
Info (332119): 0.359 0.000 CLK
|
||||
Info (332140): No Recovery paths to report
|
||||
Info (332140): No Removal paths to report
|
||||
Critical Warning (332148): Timing requirements not met
|
||||
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
|
||||
Info (332146): Worst-case minimum pulse width slack is -3.000
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= ============= =====================
|
||||
Info (332119): -3.000 -5.000 CLK
|
||||
Info: Analyzing Slow 1200mV 0C Model
|
||||
Info (334003): Started post-fitting delay annotation
|
||||
Info (334004): Delay annotation completed successfully
|
||||
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
|
||||
Info (332146): Worst-case setup slack is 0.186
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= ============= =====================
|
||||
Info (332119): 0.186 0.000 CLK
|
||||
Info (332146): Worst-case hold slack is 0.318
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= ============= =====================
|
||||
Info (332119): 0.318 0.000 CLK
|
||||
Info (332140): No Recovery paths to report
|
||||
Info (332140): No Removal paths to report
|
||||
Critical Warning (332148): Timing requirements not met
|
||||
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
|
||||
Info (332146): Worst-case minimum pulse width slack is -3.000
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= ============= =====================
|
||||
Info (332119): -3.000 -5.000 CLK
|
||||
Info: Analyzing Fast 1200mV 0C Model
|
||||
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
|
||||
Info (332146): Worst-case setup slack is 0.506
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= ============= =====================
|
||||
Info (332119): 0.506 0.000 CLK
|
||||
Info (332146): Worst-case hold slack is 0.193
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= ============= =====================
|
||||
Info (332119): 0.193 0.000 CLK
|
||||
Info (332140): No Recovery paths to report
|
||||
Info (332140): No Removal paths to report
|
||||
Critical Warning (332148): Timing requirements not met
|
||||
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
|
||||
Info (332146): Worst-case minimum pulse width slack is -3.000
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= ============= =====================
|
||||
Info (332119): -3.000 -5.052 CLK
|
||||
Info (332102): Design is not fully constrained for setup requirements
|
||||
Info (332102): Design is not fully constrained for hold requirements
|
||||
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
|
||||
Info: Peak virtual memory: 376 megabytes
|
||||
Info: Processing ended: Wed Feb 28 20:25:55 2024
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
|
||||
|
||||
@@ -0,0 +1,41 @@
|
||||
------------------------------------------------------------
|
||||
TimeQuest Timing Analyzer Summary
|
||||
------------------------------------------------------------
|
||||
|
||||
Type : Slow 1200mV 85C Model Setup 'CLK'
|
||||
Slack : 0.092
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Hold 'CLK'
|
||||
Slack : 0.359
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLK'
|
||||
Slack : -3.000
|
||||
TNS : -5.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Setup 'CLK'
|
||||
Slack : 0.186
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Hold 'CLK'
|
||||
Slack : 0.318
|
||||
TNS : 0.000
|
||||
|
||||
Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLK'
|
||||
Slack : -3.000
|
||||
TNS : -5.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Setup 'CLK'
|
||||
Slack : 0.506
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Hold 'CLK'
|
||||
Slack : 0.193
|
||||
TNS : 0.000
|
||||
|
||||
Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLK'
|
||||
Slack : -3.000
|
||||
TNS : -5.052
|
||||
|
||||
------------------------------------------------------------
|
||||
@@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 32-bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 19:17:51 February 28, 2024
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.0"
|
||||
DATE = "19:17:51 February 28, 2024"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "sclk_gen"
|
||||
@@ -0,0 +1,51 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 32-bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 19:17:51 February 28, 2024
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# sclk_gen_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone IV GX"
|
||||
set_global_assignment -name DEVICE auto
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY sclk_gen
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:17:51 FEBRUARY 28, 2024"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name VERILOG_FILE ../src/sclk_gen.v
|
||||
set_global_assignment -name VERILOG_FILE ../src/d_ff.v
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
Binary file not shown.
Reference in New Issue
Block a user