From bb04c8974403503ab4584b9a386cf78caed6c241 Mon Sep 17 00:00:00 2001 From: musabe24 Date: Wed, 28 Feb 2024 22:13:24 +0100 Subject: [PATCH] =?UTF-8?q?L=C3=B6sung=20f=C3=BCr=20Aufgabe=206.5=20hinzug?= =?UTF-8?q?ef=C3=BCgt.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- labor_4/Aufgabe_6-5/sim/down_counter_tb.v | 56 +++ labor_4/Aufgabe_6-5/sim/modelsim.ini | 324 ++++++++++++++++++ labor_4/Aufgabe_6-5/sim/sim_down_counter.tcl | 20 ++ labor_4/Aufgabe_6-5/sim/vsim.wlf | Bin 0 -> 73728 bytes labor_4/Aufgabe_6-5/sim/wave.do | 24 ++ labor_4/Aufgabe_6-5/sim/work/_info | 43 +++ labor_4/Aufgabe_6-5/sim/work/_vmake | 3 + .../sim/work/down_counter/_primary.dat | Bin 0 -> 486 bytes .../sim/work/down_counter/_primary.dbs | Bin 0 -> 545 bytes .../sim/work/down_counter/_primary.vhd | 15 + .../sim/work/down_counter/verilog.prw | Bin 0 -> 293 bytes .../sim/work/down_counter/verilog.psm | Bin 0 -> 5944 bytes .../sim/work/down_counter_tb/_primary.dat | Bin 0 -> 721 bytes .../sim/work/down_counter_tb/_primary.dbs | Bin 0 -> 795 bytes .../sim/work/down_counter_tb/_primary.vhd | 9 + .../sim/work/down_counter_tb/verilog.prw | Bin 0 -> 488 bytes .../sim/work/down_counter_tb/verilog.psm | Bin 0 -> 7320 bytes labor_4/Aufgabe_6-5/src/down_counter.v | 27 ++ 18 files changed, 521 insertions(+) create mode 100644 labor_4/Aufgabe_6-5/sim/down_counter_tb.v create mode 100644 labor_4/Aufgabe_6-5/sim/modelsim.ini create mode 100644 labor_4/Aufgabe_6-5/sim/sim_down_counter.tcl create mode 100644 labor_4/Aufgabe_6-5/sim/vsim.wlf create mode 100644 labor_4/Aufgabe_6-5/sim/wave.do create mode 100644 labor_4/Aufgabe_6-5/sim/work/_info create mode 100644 labor_4/Aufgabe_6-5/sim/work/_vmake create mode 100644 labor_4/Aufgabe_6-5/sim/work/down_counter/_primary.dat create mode 100644 labor_4/Aufgabe_6-5/sim/work/down_counter/_primary.dbs create mode 100644 labor_4/Aufgabe_6-5/sim/work/down_counter/_primary.vhd create mode 100644 labor_4/Aufgabe_6-5/sim/work/down_counter/verilog.prw create mode 100644 labor_4/Aufgabe_6-5/sim/work/down_counter/verilog.psm create mode 100644 labor_4/Aufgabe_6-5/sim/work/down_counter_tb/_primary.dat create mode 100644 labor_4/Aufgabe_6-5/sim/work/down_counter_tb/_primary.dbs create mode 100644 labor_4/Aufgabe_6-5/sim/work/down_counter_tb/_primary.vhd create mode 100644 labor_4/Aufgabe_6-5/sim/work/down_counter_tb/verilog.prw create mode 100644 labor_4/Aufgabe_6-5/sim/work/down_counter_tb/verilog.psm create mode 100644 labor_4/Aufgabe_6-5/src/down_counter.v diff --git a/labor_4/Aufgabe_6-5/sim/down_counter_tb.v b/labor_4/Aufgabe_6-5/sim/down_counter_tb.v new file mode 100644 index 0000000..30ac91a --- /dev/null +++ b/labor_4/Aufgabe_6-5/sim/down_counter_tb.v @@ -0,0 +1,56 @@ +`timescale 1ns / 1ps + +module down_counter_tb; + + // Parameter für die Simulation + parameter CLOCK_DIVIDER = 5; + + // Registrier und Drähte für die Testbench + reg CLK; + reg RESETn; + wire [$clog2(CLOCK_DIVIDER)-1:0] Q; + wire SYNC; + + // Erzeugung des Taktsignals + initial begin + CLK = 0; + forever #10 CLK = ~CLK; // 50 MHz Taktfrequenz + end + + // Testsequenz + initial begin + // Anfangszustand + RESETn = 1; + @(posedge CLK); + @(negedge CLK); + RESETn = 0; // Reset aktivieren + @(posedge CLK); + @(negedge CLK); + RESETn = 1; // Reset deaktivieren + + // Warte genug Zeit, um den Zähler vollständig herunterzuzählen + #((CLOCK_DIVIDER + 1) * 20); + + // Reset erneut aktivieren und deaktivieren, um die Reaktion zu prüfen + @(posedge CLK); + @(negedge CLK); + RESETn = 0; + @(posedge CLK); + @(negedge CLK); + RESETn = 1; + + // Simulation für weitere Zählzyklen fortsetzen + #100; + end + + // Instanziierung des down_counter Moduls + down_counter #( + .CLOCK_DIVIDER(CLOCK_DIVIDER) + ) uut ( + .CLK(CLK), + .RESETn(RESETn), + .Q(Q), + .SYNC(SYNC) + ); + +endmodule diff --git a/labor_4/Aufgabe_6-5/sim/modelsim.ini b/labor_4/Aufgabe_6-5/sim/modelsim.ini new file mode 100644 index 0000000..b0f61a8 --- /dev/null +++ b/labor_4/Aufgabe_6-5/sim/modelsim.ini @@ -0,0 +1,324 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both diff --git a/labor_4/Aufgabe_6-5/sim/sim_down_counter.tcl b/labor_4/Aufgabe_6-5/sim/sim_down_counter.tcl new file mode 100644 index 0000000..65527ee --- /dev/null +++ b/labor_4/Aufgabe_6-5/sim/sim_down_counter.tcl @@ -0,0 +1,20 @@ +#remove working directory +file delete -force work + +#Creating the work lib +vlib work +vmap work work + +#Top level testbench +vlog down_counter_tb.v + +#Compile DUT +vlog ../src/down_counter.v + +#Simulate +vsim -c -t ps down_counter_tb + +#get wave +do wave.do + +run 500 ns \ No newline at end of file diff --git a/labor_4/Aufgabe_6-5/sim/vsim.wlf b/labor_4/Aufgabe_6-5/sim/vsim.wlf new file mode 100644 index 0000000000000000000000000000000000000000..fb7812fd5b889d326a9976454838a75336323902 GIT binary patch literal 73728 zcmeI)?{5@E7{KvoW@mPf9d$lb^ zc~uE-8eeD#Mg@aFj3iax_y-t#>pP7v+886gF!8nF9h7tSj%!3PX|Tbd-^tB(Z)ay_ z_p@!^JkL(mguEqNMZ|MeB)Am1t#-BaUBq|$%GIb;ifp=WJ4X9+LqS(}=dPXY9i@iS zHuv+TPi(5OKGkoxfnF<@2=7ZO4^MP21dtZ|=zsj^|`F+mmXlZyb}6RL@YpKR2jkeQ$Ow*CQte zhMTr#2lKJqP>IF9@@8~gf^Dho^3>C5U0F9aF8%rA<3|SubFty+Q|Hl92mPO4SvpxH2` zR(g#~C7V?5sDb6mGp15DtF-x4CS{fBdg+DsDbpH!y-ZzB%4e$el&|6y6)u0F+m**k z;A{~<009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q1vpfhey3r})1-=e|cZ zI%YDJZpHtLW=We4Y{5vUT5FQYtEOHDTYQ_WzGk{~5Ts2~O_}vx5Hrc6x5L}E-F2rR zfB*srAbp~H_B(Wl-o<$0a3RoO`zBucPRqVPTVW!2)HzXnW*{Z zz0NCkEJQ6Xcc7d)P(Hgjd^A|psEdQ#ioTX7D;{?F1nx6G!<~(P->29z_t(*El-3Xp zf7d*BUE5tZTDrjh*j?U1eQz24Z#{wgxwh`O)I<-Rf&c;tAbudS@&5&7IowZ-eSv-c@e^3!Ja=S=5dVKD z|ATSS2q1s}0tg_000IagfB*srAb4)K5D|IzP5ah-*Q zuX1odG4=)aA^uO literal 0 HcmV?d00001 diff --git a/labor_4/Aufgabe_6-5/sim/wave.do b/labor_4/Aufgabe_6-5/sim/wave.do new file mode 100644 index 0000000..de03913 --- /dev/null +++ b/labor_4/Aufgabe_6-5/sim/wave.do @@ -0,0 +1,24 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /down_counter_tb/CLK +add wave -noupdate /down_counter_tb/RESETn +add wave -noupdate -radix unsigned /down_counter_tb/Q +add wave -noupdate /down_counter_tb/SYNC +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {200065 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 174 +configure wave -valuecolwidth 40 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {525 ns} diff --git a/labor_4/Aufgabe_6-5/sim/work/_info b/labor_4/Aufgabe_6-5/sim/work/_info new file mode 100644 index 0000000..fe71ab1 --- /dev/null +++ b/labor_4/Aufgabe_6-5/sim/work/_info @@ -0,0 +1,43 @@ +m255 +K3 +13 +cModel Technology +Z0 dC:\Users\Erdem\Desktop\labor_eds\labor_4\Aufgabe_6-5\sim +vdown_counter +!i10b 1 +!s100 lJB1>^HLo9B3e`P5Vlk>83 +IgV@JGMKaLghW>KQ>jjKBV1 +V1EaCSmgABcAbc~_MXO* zeP{LNrz}1{-u#*Q=JRRRGfUpMcFfyjf4nB? z1>5__ORh1e&zoW6RKW<;v+=X$Gmzm7=b!eoKhW6{YO#-@uIW7o(*xZrQY$JWX1lX8 zyj;0IVA?`$u*0_7vWJX^<*WQ;;gf3eKd%3)&MI4zRNK zSh6ItD}OY343bVh0+K#Ei)#g&ETg!1q~g5rvbAlIWsBIKl-++1QnB?eNJZjG&PRz0 z4kdOS5M=KWWHDqm4OCy3?74BSzuwE>|C>7VIyKlB_>Wl6;_zkv$~S?BT|?VF1f;!n z6-YayJEziKmMYgj-Yo14yB?|>SS%hf`Is|XW`;LOaR(RlO8{?7Qw}v5mW}G~AErhG{*3b6MvnRarP?Gua{kW~| Reho*p{{8G~sv73mcL1^_xP$-z literal 0 HcmV?d00001 diff --git a/labor_4/Aufgabe_6-5/sim/work/down_counter/_primary.dbs b/labor_4/Aufgabe_6-5/sim/work/down_counter/_primary.dbs new file mode 100644 index 0000000000000000000000000000000000000000..2dc85654e6f5c7020c916cd13a1238d8e21882d5 GIT binary patch literal 545 zcmZQ9IK^i@PlcC_OWqDhEqGfoDdqU&B@95o$Ot5ufLH;D85o#BOb`}f07)>jLb-fk zL1s2Mml-6>4kUPin2&)4#N_}HU@k}-BR7ZuVrd4DHWrXV5SKv%q!^@?55xlk7C|6^ zLrMgv6q7heF9VAtkN~-ufdgbK$PHklfHYVNB*?&mZY48F7Z(s~Fo0N$VD~Ud1DOn9 z*D^3XdT?v$5i_gy*xhrt8F99G{n+-bZ^l*WH-BgK?|f}4vH7>FbPwBP<_Yf>&OWsB z?%Xvi4qq3zD;Ds;@ondYK#&VgmaMdz-QP5C@tx)C&4RBfKC@dC?_>lD3UKH^>|$VO zt{2GHE)qKZSL>UaDa7p{DHbgt0RkY!U_XF8334)HDM%a$j;L!-iRx!y00lHCFj!hZ fqCfzO1PA~HIw%O4SnfbYKyr`(0(l%9c$^9V#gRn> literal 0 HcmV?d00001 diff --git a/labor_4/Aufgabe_6-5/sim/work/down_counter/_primary.vhd b/labor_4/Aufgabe_6-5/sim/work/down_counter/_primary.vhd new file mode 100644 index 0000000..c678572 --- /dev/null +++ b/labor_4/Aufgabe_6-5/sim/work/down_counter/_primary.vhd @@ -0,0 +1,15 @@ +library verilog; +use verilog.vl_types.all; +entity down_counter is + generic( + CLOCK_DIVIDER : integer := 5 + ); + port( + CLK : in vl_logic; + RESETn : in vl_logic; + Q : out vl_logic_vector; + SYNC : out vl_logic + ); + attribute mti_svvh_generic_type : integer; + attribute mti_svvh_generic_type of CLOCK_DIVIDER : constant is 1; +end down_counter; diff --git a/labor_4/Aufgabe_6-5/sim/work/down_counter/verilog.prw b/labor_4/Aufgabe_6-5/sim/work/down_counter/verilog.prw new file mode 100644 index 0000000000000000000000000000000000000000..439e17a7d236af0aaf4e2f546993bf3ec6d34b57 GIT binary patch literal 293 zcmXxf&kBM-5C-t^Umd%2=(w;i(5?#6RXvDNlo52YNIhzV(LsC+-=GKS(fY+p8^;Qs>H`#mK9 literal 0 HcmV?d00001 diff --git a/labor_4/Aufgabe_6-5/sim/work/down_counter/verilog.psm b/labor_4/Aufgabe_6-5/sim/work/down_counter/verilog.psm new file mode 100644 index 0000000000000000000000000000000000000000..d4496f0446ef6736e12c0bcdd1fc0036df53985f GIT binary patch literal 5944 zcmbtYO>9(E6n^*3^me8ccx{It|DbmKsah6;nz+z}gf^7WAObOMV_*nvLLve&U|o2E=<@N_bgm!T)K2)V#J^E`_4UQxV_9+lv(igo_o%Be(!zn z@m%@YJud5C&G5^CZ@4Tg0Y|VdtGrLq11peMfsX(OfV+SjfLnosiW?O-0Uv^VGw^+2 z0lWqNA>ePoVZ{;P&v};BfKbb}C~j5UrnnvWce~w2grD42{9W-c#Xl9vqYDXQa|Of_1>8S*!Rm1K#%^*AQZ$p_HR5*Na>gHk)Qqz<2Vja9g+Nwp2?<4 znjiJn^W(wCcrV_gpI5SMP5pMjj`15>o`(I(|53sp=M(2~WbUB!Edx5uqjV2>u>Q>B z#y$F}LyvLaRPVieQ9R6Ny?D|(*?h-5 z>_`1vy}>zcWc3EmOZ`NBH`mW+_1$)U=-=|O`YfDXIzzqVC(m9Wo;knxCNTrDpFG#D zuT;=3&vN$-0%*5ub6Co{3LMNz?u)SYhPuykQqNxiw%a2E>=V~z1i&@u+gux({(r?^ zu9s`%F}t56&XEDu3-Y&B?j#TAa?S(wUjX8~cI=KJA;jemshkGXThw^pgS_3YG=!(> z9P7w6fO>8f2{Ny1ioCCo;%p)O{}3{H)FzryImB>nv;M_65I1$OnEc z4%tUsoWD44se^M9A^t-67%%PeNL~axCw;2Aoa?wg!c%o#?11XW4~4o7u#n&zQ@ap{ zb1#V;acQ3&=bC!8!0%WetfxdC=|L=Y9SHmT#2@xmUw9B-L-rwOow$~LtjUM|c-fEU zgL39&{hm$MAM5>9cs`UX9zKlm>xzwDzQ41j)4K!J0}dz|yh_;b`FoeRcKzgDM)#@A9i z*@xXG)ziHF3f9bv{^`%`Te2=X=joc}u@dwe!lQkO=TqzFZ$gi}t3kh0FZN*qePBFM zALfy!%!lsxI!E)$@7B?q)4n*)?d z1QG9*lUiTX`&IQqpL*-@0w&*z@>#u&4`PYScw3@(r$4iLK5c(O`92lByZzdIZ2I46 z{xT2I+-|1dXnsaDPrF~Sy{2Aj@84CvY4Kla2oL6hb&uyl)?N6mFDbv;clZw}zsSKq zl<>>C3xCRMYqjt2zoz^m2mdhnBfhX-_+Ir$`I^cnJmBN~7}taI3;xbMuK5PN$gk+( zKIr9Fc{_QWQ@Pu5Z12Yso=@46y-FMI~OjMwI>sd3spaufTEQ}n8C z9!u88Jq)bio}J*j%UthDxC8Z{*MK*`X+ZSwqfw=!cxz%x^of>NrO7ljn4nFUk7}_BEd+dp=41 z@m_Qh+K9(J2t-}RbS@pg+p*p!a`aL3fg(p;Ss3~a-~A=26GWY#&e@VZ=Vq|Od6`z6 z1u}2D$NRPale%wpO6^RKb>bYD-e+2Ok)t0bPx;KA|9?Syfb{oswbyt%=in0d*)P*; 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+ +always @(posedge CLK or negedge RESETn) begin + if(~RESETn) begin + Q <= 1'd0; + end + else begin + if (Q > 1'd0) begin + Q <= Q - 1'd1; + end + else if(Q == 1'd0) begin + Q <= CLOCK_DIVIDER; + end + end +end + +assign SYNC = (Q == 1'd0); + +endmodule \ No newline at end of file