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labor_3/res/ampel/sim/create_designlib.tcl

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+## CREATE DESIGNLIB
+# there needs to be a folder designlib
+# rm -rf designlib
+# mkdir designlib
+vlib designlib/ampel
+vmap ampel "designlib/ampel"
+vlog ../src/ampel.v +define+SIMULATION -work ampel
+vlog ../src/mod_n_counter_10bit.v +define+SIMULATION -work ampel
+

labor_3/res/ampel/sim/designlib/ampel/_info

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+m255
+K3
+13
+cModel Technology
+Z0 dD:\Unverschluesselt\EDS_UEBUNGEN_2020\ampel\sim
+vampel
+IL]jRSX9lQ5YM508d006DE0
+VlCk1Ao:VM2mW]^Odc6Bhj2
+Z1 dD:\Unverschluesselt\EDS_UEBUNGEN_2020\ampel\sim
+Z2 w1580669164
+8../src/ampel.v
+F../src/ampel.v
+L0 17
+Z3 OV;L;10.1b;51
+r1
+31
+Z4 o-work ampel -O0
+!i10b 1
+!s100 Rg2UN1YACYn>hH5^mG_mX1
+!s85 0
+!s108 1583413383.761000
+!s107 ../src/ampel.v|
+!s90 -reportprogress|300|../src/ampel.v|+define+SIMULATION|-work|ampel|
+!s101 -O0
+Z5 !s92 +define+SIMULATION -work ampel -O0
+vmod_n_counter_10bit
+!i10b 1
+!s100 9e`GV_]:ML:l92jkefb>Q0
+IL;d^FF@OdJ:kj4TXO^Q0>3
+VOCKRzhG[H7hm^_`n>48^e3
+R1
+R2
+8../src/mod_n_counter_10bit.v
+F../src/mod_n_counter_10bit.v
+L0 1
+R3
+r1
+!s85 0
+31
+!s108 1583413384.279000
+!s107 ../src/mod_n_counter_10bit.v|
+!s90 -reportprogress|300|../src/mod_n_counter_10bit.v|+define+SIMULATION|-work|ampel|
+!s101 -O0
+R4
+R5

labor_3/res/ampel/sim/designlib/ampel/_vmake

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+m255
+K3
+cModel Technology

labor_3/res/ampel/sim/designlib/ampel/ampel/_primary.vhd

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+library verilog;
+use verilog.vl_types.all;
+entity ampel is
+    generic(
+        FUSS_AUS        : vl_logic_vector(0 to 1) := (Hi0, Hi0);
+        FUSS_ROT        : vl_logic_vector(0 to 1) := (Hi1, Hi0);
+        FUSS_GRUEN      : vl_logic_vector(0 to 1) := (Hi0, Hi1);
+        AUTO_AUS        : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi0);
+        AUTO_ROT        : vl_logic_vector(0 to 2) := (Hi1, Hi0, Hi0);
+        AUTO_GELB       : vl_logic_vector(0 to 2) := (Hi0, Hi1, Hi0);
+        AUTO_GRUEN      : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi1)
+    );
+    port(
+        CLOCK_50        : in     vl_logic;
+        KEY             : in     vl_logic_vector(1 downto 0);
+        LEDH_L          : out    vl_logic_vector(2 downto 0);
+        LEDH_R          : out    vl_logic_vector(2 downto 0);
+        LEDN_L          : out    vl_logic_vector(2 downto 0);
+        LEDN_R          : out    vl_logic_vector(2 downto 0);
+        LEDF_L          : out    vl_logic_vector(1 downto 0);
+        LEDF_R          : out    vl_logic_vector(1 downto 0)
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of FUSS_AUS : constant is 1;
+    attribute mti_svvh_generic_type of FUSS_ROT : constant is 1;
+    attribute mti_svvh_generic_type of FUSS_GRUEN : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_AUS : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_ROT : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_GELB : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_GRUEN : constant is 1;
+end ampel;

labor_3/res/ampel/sim/designlib/ampel/mod_n_counter_10bit/_primary.vhd

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+library verilog;
+use verilog.vl_types.all;
+entity mod_n_counter_10bit is
+    generic(
+        N               : integer := 10
+    );
+    port(
+        CLK             : in     vl_logic;
+        RST             : in     vl_logic;
+        EN              : in     vl_logic;
+        Q               : out    vl_logic_vector(9 downto 0);
+        TC              : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of N : constant is 1;
+end mod_n_counter_10bit;

labor_3/res/ampel/sim/sim.tcl

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+#JZ 2020
+
+#remove working directory
+file delete -force work
+
+#Creating the work lib
+vlib work
+vmap ampel "designlib/ampel"
+vmap work work
+
+#Top level testbench
+vlog tb_ampel.v
+#vlog ../src/ampel.v +define+SIMULATION
+
+#Simulate
+vsim -c -t ps -L ampel tb_ampel
+#vsim -c -t ps tb_ampel
+
+#get wave
+do wave.do
+
+run 1500 us

labor_3/res/ampel/sim/tb_ampel.v

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+/******************************************************
+*                                                     
+*  Description:  tb_ampel                                
+*         Date:  13.01.2018                           
+*    File Name:  tb_ampel.v                              
+*      Version:  1.0                                  
+*       Target:  Simulation             
+*   Technology:                                       
+*                                                     
+* Rev   Author   Date          Changes                
+* -----------------------------------------------------        
+* 1.0   JZ       13.01.2018    Testbench zur Ampelsteuerung
+*******************************************************/
+
+`timescale 1ns / 1ps
+
+module tb_ampel;
+
+reg CLK;
+reg RSTn;
+reg SW;
+
+wire [2:0] HAUPTSTR_LINKS;
+wire [2:0] NEBENSTR_LINKS;
+wire [1:0] FUSSGAENGER_LINKS;
+wire [2:0] HAUPTSTR_RECHTS;
+wire [2:0] NEBENSTR_RECHTS;
+wire [1:0] FUSSGAENGER_RECHTS;
+
+//50 MHz clock
+initial
+  begin
+  CLK  = 1'b0;
+  end
+
+always
+  CLK = #10 ~CLK;
+
+//push buttons
+initial
+  begin
+  RSTn = 1'b1;
+  SW = 1'b1;
+  #100;
+  RSTn = 1'b0;
+  #10;
+  RSTn = 1'b1;
+  #50_000;
+  SW = 1'b0;
+  #100;
+  SW = 1'b1;
+  end
+
+ampel ampel(
+.CLOCK_50 (CLK),
+.KEY ({RSTn, SW}),
+.LEDH_L(HAUPTSTR_LINKS),
+.LEDN_L(NEBENSTR_LINKS),
+.LEDF_L(FUSSGAENGER_LINKS),
+.LEDH_R(HAUPTSTR_RECHTS),
+.LEDN_R(NEBENSTR_RECHTS),
+.LEDF_R(FUSSGAENGER_RECHTS)
+);
+
+
+
+endmodule