From f65a8de67cf1786c883b51199ca821ebe5ef271c Mon Sep 17 00:00:00 2001
From: musabe24 <erdem.musab@outlook.de>
Date: Tue, 27 Feb 2024 11:52:07 +0100
Subject: [PATCH] Aufgabe bearbeitet.

---
 labor_3/res/ampel/sim/vsim.wlf                | Bin 73728 -> 73728 bytes
 labor_3/Ãœbungen/ampel/sim/modelsim.ini        | 324 ++++++++++++++++++
 labor_3/Ãœbungen/ampel/sim/sim.tcl             |   3 +-
 labor_3/Ãœbungen/ampel/sim/vsim.wlf            | Bin 0 -> 81920 bytes
 labor_3/Ãœbungen/ampel/sim/work/_info          |  63 ++++
 labor_3/Ãœbungen/ampel/sim/work/_vmake         |   3 +
 .../Ãœbungen/ampel/sim/work/ampel/_primary.dat | Bin 0 -> 4341 bytes
 .../Ãœbungen/ampel/sim/work/ampel/_primary.dbs | Bin 0 -> 6075 bytes
 .../Ãœbungen/ampel/sim/work/ampel/_primary.vhd |  32 ++
 .../Ãœbungen/ampel/sim/work/ampel/verilog.prw  | Bin 0 -> 2109 bytes
 .../Ãœbungen/ampel/sim/work/ampel/verilog.psm  | Bin 0 -> 47064 bytes
 .../sim/work/mod_n_counter_10bit/_primary.dat | Bin 0 -> 506 bytes
 .../sim/work/mod_n_counter_10bit/_primary.dbs | Bin 0 -> 651 bytes
 .../sim/work/mod_n_counter_10bit/_primary.vhd |  16 +
 .../sim/work/mod_n_counter_10bit/verilog.prw  | Bin 0 -> 304 bytes
 .../sim/work/mod_n_counter_10bit/verilog.psm  | Bin 0 -> 6352 bytes
 .../ampel/sim/work/tb_ampel/_primary.dat      | Bin 0 -> 939 bytes
 .../ampel/sim/work/tb_ampel/_primary.dbs      | Bin 0 -> 1173 bytes
 .../ampel/sim/work/tb_ampel/_primary.vhd      |   4 +
 .../ampel/sim/work/tb_ampel/verilog.prw       | Bin 0 -> 558 bytes
 .../ampel/sim/work/tb_ampel/verilog.psm       | Bin 0 -> 8016 bytes
 labor_3/Ãœbungen/ampel/src/ampel.v             | 307 +++++++++++++++++
 labor_3/Ãœbungen/ampel/src/ampel.v.bak         | 307 +++++++++++++++++
 labor_3/Ãœbungen/ampel/src/ampel_wo_src.v      | 159 ---------
 labor_3/Ãœbungen/ampel/src/jk_ff.v             |  38 ++
 25 files changed, 1096 insertions(+), 160 deletions(-)
 create mode 100644 labor_3/Ãœbungen/ampel/sim/modelsim.ini
 create mode 100644 labor_3/Ãœbungen/ampel/sim/vsim.wlf
 create mode 100644 labor_3/Ãœbungen/ampel/sim/work/_info
 create mode 100644 labor_3/Ãœbungen/ampel/sim/work/_vmake
 create mode 100644 labor_3/Ãœbungen/ampel/sim/work/ampel/_primary.dat
 create mode 100644 labor_3/Ãœbungen/ampel/sim/work/ampel/_primary.dbs
 create mode 100644 labor_3/Ãœbungen/ampel/sim/work/ampel/_primary.vhd
 create mode 100644 labor_3/Ãœbungen/ampel/sim/work/ampel/verilog.prw
 create mode 100644 labor_3/Ãœbungen/ampel/sim/work/ampel/verilog.psm
 create mode 100644 labor_3/Ãœbungen/ampel/sim/work/mod_n_counter_10bit/_primary.dat
 create mode 100644 labor_3/Ãœbungen/ampel/sim/work/mod_n_counter_10bit/_primary.dbs
 create mode 100644 labor_3/Ãœbungen/ampel/sim/work/mod_n_counter_10bit/_primary.vhd
 create mode 100644 labor_3/Ãœbungen/ampel/sim/work/mod_n_counter_10bit/verilog.prw
 create mode 100644 labor_3/Ãœbungen/ampel/sim/work/mod_n_counter_10bit/verilog.psm
 create mode 100644 labor_3/Ãœbungen/ampel/sim/work/tb_ampel/_primary.dat
 create mode 100644 labor_3/Ãœbungen/ampel/sim/work/tb_ampel/_primary.dbs
 create mode 100644 labor_3/Ãœbungen/ampel/sim/work/tb_ampel/_primary.vhd
 create mode 100644 labor_3/Ãœbungen/ampel/sim/work/tb_ampel/verilog.prw
 create mode 100644 labor_3/Ãœbungen/ampel/sim/work/tb_ampel/verilog.psm
 create mode 100644 labor_3/Ãœbungen/ampel/src/ampel.v
 create mode 100644 labor_3/Ãœbungen/ampel/src/ampel.v.bak
 delete mode 100644 labor_3/Ãœbungen/ampel/src/ampel_wo_src.v
 create mode 100644 labor_3/Ãœbungen/ampel/src/jk_ff.v

diff --git a/labor_3/res/ampel/sim/vsim.wlf b/labor_3/res/ampel/sim/vsim.wlf
index 788f89b7bff9780dcbebb1aaf3babd3d327375ed..fe649355198b25d4456bff831f2a7a7b803236f4 100644
GIT binary patch
delta 21
ccmZoTz|wGlg-M`nB9k_wOrzdbJ;qD&0801<Z~y=R

delta 21
ccmZoTz|wGlg-JMNB9k_wWTW0zJ;qD&07@VRUH||9

diff --git a/labor_3/Ãœbungen/ampel/sim/modelsim.ini b/labor_3/Ãœbungen/ampel/sim/modelsim.ini
new file mode 100644
index 0000000..b0f61a8
--- /dev/null
+++ b/labor_3/Ãœbungen/ampel/sim/modelsim.ini
@@ -0,0 +1,324 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+;
+; Verilog Section
+;
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license isn't available
+; viewsim	Try for viewer license but accept simulator license(s) instead
+;		of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type).  Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and 
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer).  The other settings
+; are to send messages only to the transcript or only to the 
+; wlf file.  The valid values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both
diff --git a/labor_3/Ãœbungen/ampel/sim/sim.tcl b/labor_3/Ãœbungen/ampel/sim/sim.tcl
index 1773ef0..1b31acb 100644
--- a/labor_3/Ãœbungen/ampel/sim/sim.tcl
+++ b/labor_3/Ãœbungen/ampel/sim/sim.tcl
@@ -10,7 +10,8 @@ vmap work work
 
 #Top level testbench
 vlog tb_ampel.v
-#vlog ../src/ampel.v +define+SIMULATION
+vlog ../src/ampel.v +define+SIMULATION
+vlog ../src/mod_n_counter_10bit.v
 
 #Simulate
 #vsim -c -t ps -L ampel tb_ampel
diff --git a/labor_3/Ãœbungen/ampel/sim/vsim.wlf b/labor_3/Ãœbungen/ampel/sim/vsim.wlf
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diff --git a/labor_3/Ãœbungen/ampel/sim/work/_info b/labor_3/Ãœbungen/ampel/sim/work/_info
new file mode 100644
index 0000000..1ca19de
--- /dev/null
+++ b/labor_3/Ãœbungen/ampel/sim/work/_info
@@ -0,0 +1,63 @@
+m255
+K3
+13
+cModel Technology
+Z0 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_3\Übungen\ampel\sim
+vampel
+Z1 IAVFK:UCi>e]M?9Rf^BY>j0
+Z2 VRO2_FXGbKEQ9T<W2M?dVH1
+Z3 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_3\Übungen\ampel\sim
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+Z6 F../src/ampel.v
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+!i10b 1
+Z8 !s100 S?HeNBV[mV3T>a:hdNfS10
+!s85 0
+Z9 !s108 1708618418.950000
+Z10 !s107 ../src/ampel.v|
+Z11 !s90 -reportprogress|300|../src/ampel.v|+define+SIMULATION|
+!s101 -O0
+Z12 !s92 +define+SIMULATION -O0
+vmod_n_counter_10bit
+!i10b 1
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+F../src/mod_n_counter_10bit.v
+L0 1
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+r1
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+!s107 ../src/mod_n_counter_10bit.v|
+!s90 -reportprogress|300|../src/mod_n_counter_10bit.v|
+!s101 -O0
+o-O0
+vtb_ampel
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+Z15 V6nf?5m:3VQD@E=_a?l5VH1
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+Z17 Ftb_ampel.v
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+Z21 !s90 -reportprogress|300|tb_ampel.v|
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+!s85 0
+!s101 -O0
diff --git a/labor_3/Ãœbungen/ampel/sim/work/_vmake b/labor_3/Ãœbungen/ampel/sim/work/_vmake
new file mode 100644
index 0000000..2f7e729
--- /dev/null
+++ b/labor_3/Ãœbungen/ampel/sim/work/_vmake
@@ -0,0 +1,3 @@
+m255
+K3
+cModel Technology
diff --git a/labor_3/Ãœbungen/ampel/sim/work/ampel/_primary.dat b/labor_3/Ãœbungen/ampel/sim/work/ampel/_primary.dat
new file mode 100644
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diff --git a/labor_3/Ãœbungen/ampel/sim/work/ampel/_primary.dbs b/labor_3/Ãœbungen/ampel/sim/work/ampel/_primary.dbs
new file mode 100644
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diff --git a/labor_3/Ãœbungen/ampel/sim/work/ampel/_primary.vhd b/labor_3/Ãœbungen/ampel/sim/work/ampel/_primary.vhd
new file mode 100644
index 0000000..706b9fd
--- /dev/null
+++ b/labor_3/Ãœbungen/ampel/sim/work/ampel/_primary.vhd
@@ -0,0 +1,32 @@
+library verilog;
+use verilog.vl_types.all;
+entity ampel is
+    generic(
+        FUSS_AUS        : vl_logic_vector(0 to 1) := (Hi0, Hi0);
+        FUSS_ROT        : vl_logic_vector(0 to 1) := (Hi1, Hi0);
+        FUSS_GRUEN      : vl_logic_vector(0 to 1) := (Hi0, Hi1);
+        AUTO_AUS        : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi0);
+        AUTO_ROT        : vl_logic_vector(0 to 2) := (Hi1, Hi0, Hi0);
+        AUTO_GELB       : vl_logic_vector(0 to 2) := (Hi0, Hi1, Hi0);
+        AUTO_GRUEN      : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi1)
+    );
+    port(
+        CLOCK_50        : in     vl_logic;
+        KEY             : in     vl_logic_vector(1 downto 0);
+        LEDH_L          : out    vl_logic_vector(2 downto 0);
+        LEDH_R          : out    vl_logic_vector(2 downto 0);
+        LEDN_L          : out    vl_logic_vector(2 downto 0);
+        LEDN_R          : out    vl_logic_vector(2 downto 0);
+        LEDF_L          : out    vl_logic_vector(1 downto 0);
+        LEDF_R          : out    vl_logic_vector(1 downto 0);
+        DBG             : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of FUSS_AUS : constant is 1;
+    attribute mti_svvh_generic_type of FUSS_ROT : constant is 1;
+    attribute mti_svvh_generic_type of FUSS_GRUEN : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_AUS : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_ROT : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_GELB : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_GRUEN : constant is 1;
+end ampel;
diff --git a/labor_3/Ãœbungen/ampel/sim/work/ampel/verilog.prw b/labor_3/Ãœbungen/ampel/sim/work/ampel/verilog.prw
new file mode 100644
index 0000000000000000000000000000000000000000..8457ff938e2c24c8ad8c55dcc4c26f24695c4501
GIT binary patch
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literal 0
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diff --git a/labor_3/Ãœbungen/ampel/sim/work/ampel/verilog.psm b/labor_3/Ãœbungen/ampel/sim/work/ampel/verilog.psm
new file mode 100644
index 0000000000000000000000000000000000000000..8de7bcda1fadd13537bd81cbf8e1c6b0a3f75882
GIT binary patch
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diff --git a/labor_3/Ãœbungen/ampel/sim/work/mod_n_counter_10bit/_primary.dat b/labor_3/Ãœbungen/ampel/sim/work/mod_n_counter_10bit/_primary.dat
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diff --git a/labor_3/Ãœbungen/ampel/sim/work/mod_n_counter_10bit/_primary.dbs b/labor_3/Ãœbungen/ampel/sim/work/mod_n_counter_10bit/_primary.dbs
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diff --git a/labor_3/Ãœbungen/ampel/sim/work/mod_n_counter_10bit/_primary.vhd b/labor_3/Ãœbungen/ampel/sim/work/mod_n_counter_10bit/_primary.vhd
new file mode 100644
index 0000000..5969a9e
--- /dev/null
+++ b/labor_3/Ãœbungen/ampel/sim/work/mod_n_counter_10bit/_primary.vhd
@@ -0,0 +1,16 @@
+library verilog;
+use verilog.vl_types.all;
+entity mod_n_counter_10bit is
+    generic(
+        N               : integer := 10
+    );
+    port(
+        CLK             : in     vl_logic;
+        RST             : in     vl_logic;
+        EN              : in     vl_logic;
+        Q               : out    vl_logic_vector(9 downto 0);
+        TC              : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of N : constant is 1;
+end mod_n_counter_10bit;
diff --git a/labor_3/Ãœbungen/ampel/sim/work/mod_n_counter_10bit/verilog.prw b/labor_3/Ãœbungen/ampel/sim/work/mod_n_counter_10bit/verilog.prw
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diff --git a/labor_3/Ãœbungen/ampel/sim/work/mod_n_counter_10bit/verilog.psm b/labor_3/Ãœbungen/ampel/sim/work/mod_n_counter_10bit/verilog.psm
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diff --git a/labor_3/Ãœbungen/ampel/sim/work/tb_ampel/_primary.dat b/labor_3/Ãœbungen/ampel/sim/work/tb_ampel/_primary.dat
new file mode 100644
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diff --git a/labor_3/Ãœbungen/ampel/sim/work/tb_ampel/_primary.dbs b/labor_3/Ãœbungen/ampel/sim/work/tb_ampel/_primary.dbs
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diff --git a/labor_3/Ãœbungen/ampel/sim/work/tb_ampel/_primary.vhd b/labor_3/Ãœbungen/ampel/sim/work/tb_ampel/_primary.vhd
new file mode 100644
index 0000000..ee3ae5c
--- /dev/null
+++ b/labor_3/Ãœbungen/ampel/sim/work/tb_ampel/_primary.vhd
@@ -0,0 +1,4 @@
+library verilog;
+use verilog.vl_types.all;
+entity tb_ampel is
+end tb_ampel;
diff --git a/labor_3/Ãœbungen/ampel/sim/work/tb_ampel/verilog.prw b/labor_3/Ãœbungen/ampel/sim/work/tb_ampel/verilog.prw
new file mode 100644
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diff --git a/labor_3/Ãœbungen/ampel/src/ampel.v b/labor_3/Ãœbungen/ampel/src/ampel.v
new file mode 100644
index 0000000..ea5a876
--- /dev/null
+++ b/labor_3/Ãœbungen/ampel/src/ampel.v
@@ -0,0 +1,307 @@
+/******************************************************
+*                                                     
+*  Description:  Vorlage Ampelsteurerung                                
+*         Date:  05.01.2018                          
+*    File Name:  ampel_wo_src.v                              
+*      Version:  1.2                                  
+*       Target:  Simulation and Synthesis             
+*   Technology:                                       
+*                                                     
+* Rev   Author   Date          Changes                
+* -----------------------------------------------------
+* 1.0   RHK      10.10.2011    Initial Release        
+* 1.1   JZ       10.03.2016    several bugfixes
+* 1.2   JZ       05.01.2018    angepasst auf neues Ampelboard
+* 1.3   MW       07.03.2019    STATE Konstanten angepasst
+*******************************************************/
+
+`timescale 1ns / 1ps
+
+module ampel (
+  input              CLOCK_50,
+  input        [1:0] KEY,
+  output       [2:0] LEDH_L,
+  output       [2:0] LEDH_R,
+  output       [2:0] LEDN_L,
+  output       [2:0] LEDN_R,
+  output       [1:0] LEDF_L,
+  output       [1:0] LEDF_R, 
+  output reg			DBG  
+);
+
+reg [9:0] CLKDIV1;
+reg [9:0] CLKDIV2;
+reg [9:0] CLKDIV3;
+
+reg MELDER;
+reg MELDER_Q;
+reg MELDER_QQ;
+reg MELDER_ACK;
+reg CLOCK_ENABLE;
+
+reg START_WARTEN;
+reg [3:0] STATE;
+reg [2:0] HAUPTSTR;
+reg [2:0] NEBENSTR;
+reg [1:0] FUSSGAENGER;
+
+reg [3:0] WARTEZAEHLER;
+reg [3:0] WARTEWERT;
+
+wire en_div_1;
+wire en_div_2;
+wire en_div_3;
+
+wire tc_div_1;
+wire tc_div_2;
+wire tc_div_3;
+
+wire [9:0] q_div_1;
+wire [9:0] q_div_2;
+wire [9:0] q_div_3;
+
+//                       R Gr
+parameter FUSS_AUS   = 2'b00;
+parameter FUSS_ROT   = 2'b10;
+parameter FUSS_GRUEN = 2'b01;
+//                      R Ge Gr
+parameter AUTO_AUS   = 3'b000;
+parameter AUTO_ROT   = 3'b100;
+parameter AUTO_GELB  = 3'b010;
+parameter AUTO_GRUEN = 3'b001;
+
+assign RESET                     = ~KEY[1];
+
+assign LEDH_L  = HAUPTSTR;
+assign LEDH_R  = HAUPTSTR;
+assign LEDN_L = NEBENSTR;
+assign LEDN_R = NEBENSTR;
+assign LEDF_L = FUSSGAENGER;
+assign LEDF_R = FUSSGAENGER;
+
+`ifdef SIMULATION
+`define DIVVAL1 10-1
+`define DIVVAL3 5-1
+`else
+`define DIVVAL1 1000-1
+`define DIVVAL3 50-1
+`endif
+
+`define FUSS_WARTEN       4  //Wartezeit
+`define GELB_DAUER        4  //Wartezeit 
+`define FUSS_GRUEN_DAUER  4  //Wartezeit
+`define ALLE_ROT_DAUER    4  //Wartezeit
+
+`define HAUPT_GRUEN_DAUER 4  //Wartezeit
+`define NEBEN_GRUEN_DAUER 4  //Wartezeit
+
+
+`define PHASEVAL 8
+
+//clock divider to generate 1 Hz
+//
+
+assign en_div_1 = 1'b1;
+assign en_div_2 = tc_div_1;
+assign en_div_3 = tc_div_1 & tc_div_2;
+
+always  begin
+      CLOCK_ENABLE = tc_div_3;
+end
+
+// synchronisze KEY to CLOCK_50
+always @(posedge CLOCK_50) begin
+      MELDER_Q = ~KEY[0];
+      MELDER_QQ = MELDER_Q;
+end
+
+// Melder sofort setzen 
+// Melder zuruecksetzen wenn die Anforderung von der Statemachine verarbeitet
+// wurde. Die Ampelanlage gibt den FUSSGAENGERn nur dann gruen wenn
+// ein Melder anstehst...			
+always @(posedge CLOCK_50 or negedge RESET) begin
+  if (RESET)
+    MELDER <= 1'b0;
+  else begin
+      case ({MELDER_QQ, MELDER_ACK})
+            2'b01: MELDER <= 1'b0;
+            2'b10: MELDER <= 1'b1;
+            2'b11: MELDER <= ~MELDER;
+            default: ;
+      endcase
+  end 	
+end   
+
+assign WARTEN_FERTIG = (WARTEZAEHLER == 4'b0000);
+
+//Wartezaehler
+always @(posedge CLOCK_50 or RESET) begin
+      if(RESET) begin
+            WARTEZAEHLER <= WARTEWERT;
+      end
+      else if(CLOCK_ENABLE)  begin
+            if (START_WARTEN)
+                  WARTEZAEHLER <= WARTEWERT;
+                  START_WARTEN <= 1'b0;
+            if (~WARTEN_FERTIG)
+                  WARTEZAEHLER <= WARTEZAEHLER - 1'b1;
+      end
+end
+
+always @(posedge CLOCK_50 or negedge RESET)
+  if (RESET)
+    begin
+    HAUPTSTR     <= AUTO_GRUEN;
+    NEBENSTR     <= AUTO_ROT;
+    FUSSGAENGER  <= FUSS_ROT;
+    START_WARTEN <= 1'b0;
+    STATE        <= 4'd0;
+    MELDER_ACK   <= 1'b0;
+    end
+  else
+  if (CLOCK_ENABLE)
+  case (STATE)
+    4'd0: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR <= AUTO_GRUEN;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `HAUPT_GRUEN_DAUER;
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end        
+    4'd1: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR = AUTO_GELB;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `GELB_DAUER;
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end
+    4'd2: begin
+            if(WARTEN_FERTIG && MELDER) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `FUSS_WARTEN;
+                  MELDER_ACK <= 1'b1; 
+
+            end else if (WARTEN_FERTIG && ~MELDER) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `ALLE_ROT_DAUER;
+
+            end else if(~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+            end
+          end
+    4'd3: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_GRUEN;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `FUSS_GRUEN_DAUER;
+                  MELDER_ACK <= 1'b0;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end 
+    4'd4: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_GELB|AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `GELB_DAUER;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end
+    4'd5: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_GRUEN;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `NEBEN_GRUEN_DAUER;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end
+    4'd6: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_GELB;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `GELB_DAUER;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end     
+    4'd7: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `ALLE_ROT_DAUER;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end     
+    4'd8: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR <= AUTO_GELB|AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `GELB_DAUER;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end     
+    default:                      
+          STATE <= 4'd1;
+  endcase
+
+mod_n_counter_10bit #(.N(`DIVVAL1)) clock_divider_1(
+      .CLK(CLOCK_50),
+      .RST(RESET),
+      .EN(en_div_1),
+      .Q(q_div_1),
+      .TC(tc_div_1)
+);
+
+mod_n_counter_10bit #(.N(`DIVVAL1)) clock_divider_2(
+      .CLK(CLOCK_50),
+      .RST(RESET),
+      .EN(en_div_2),
+      .Q(q_div_2),
+      .TC(tc_div_2)
+);
+
+mod_n_counter_10bit #(.N(`DIVVAL3)) clock_divider_3(
+      .CLK(CLOCK_50),
+      .RST(RESET),
+      .EN(en_div_3),
+      .Q(q_div_3),
+      .TC(tc_div_3)
+);
+                        
+endmodule
\ No newline at end of file
diff --git a/labor_3/Ãœbungen/ampel/src/ampel.v.bak b/labor_3/Ãœbungen/ampel/src/ampel.v.bak
new file mode 100644
index 0000000..18cac12
--- /dev/null
+++ b/labor_3/Ãœbungen/ampel/src/ampel.v.bak
@@ -0,0 +1,307 @@
+/******************************************************
+*                                                     
+*  Description:  Vorlage Ampelsteurerung                                
+*         Date:  05.01.2018                          
+*    File Name:  ampel_wo_src.v                              
+*      Version:  1.2                                  
+*       Target:  Simulation and Synthesis             
+*   Technology:                                       
+*                                                     
+* Rev   Author   Date          Changes                
+* -----------------------------------------------------
+* 1.0   RHK      10.10.2011    Initial Release        
+* 1.1   JZ       10.03.2016    several bugfixes
+* 1.2   JZ       05.01.2018    angepasst auf neues Ampelboard
+* 1.3   MW       07.03.2019    STATE Konstanten angepasst
+*******************************************************/
+
+`timescale 1ns / 1ps
+
+module ampel (
+  input              CLOCK_50,
+  input        [1:0] KEY,
+  output       [2:0] LEDH_L,
+  output       [2:0] LEDH_R,
+  output       [2:0] LEDN_L,
+  output       [2:0] LEDN_R,
+  output       [1:0] LEDF_L,
+  output       [1:0] LEDF_R, 
+  output reg			DBG  
+);
+
+reg [9:0] CLKDIV1;
+reg [9:0] CLKDIV2;
+reg [9:0] CLKDIV3;
+
+reg MELDER;
+reg MELDER_Q;
+reg MELDER_QQ;
+reg MELDER_ACK;
+reg CLOCK_ENABLE;
+
+reg START_WARTEN;
+reg [3:0] STATE;
+reg [2:0] HAUPTSTR;
+reg [2:0] NEBENSTR;
+reg [1:0] FUSSGAENGER;
+
+reg [3:0] WARTEZAEHLER;
+reg [3:0] WARTEWERT;
+
+wire en_div_1;
+wire en_div_2;
+wire en_div_3;
+
+wire tc_div_1;
+wire tc_div_2;
+wire tc_div_3;
+
+wire [9:0] q_div_1;
+wire [9:0] q_div_2;
+wire [9:0] q_div_3;
+
+//                       R Gr
+parameter FUSS_AUS   = 2'b00;
+parameter FUSS_ROT   = 2'b10;
+parameter FUSS_GRUEN = 2'b01;
+//                      R Ge Gr
+parameter AUTO_AUS   = 3'b000;
+parameter AUTO_ROT   = 3'b100;
+parameter AUTO_GELB  = 3'b010;
+parameter AUTO_GRUEN = 3'b001;
+
+assign RESET                     = ~KEY[1];
+
+assign LEDH_L  = HAUPTSTR;
+assign LEDH_R  = HAUPTSTR;
+assign LEDN_L = NEBENSTR;
+assign LEDN_R = NEBENSTR;
+assign LEDF_L = FUSSGAENGER;
+assign LEDF_R = FUSSGAENGER;
+
+`ifdef SIMULATION
+`define DIVVAL1 10-1
+`define DIVVAL3 5-1
+`else
+`define DIVVAL1 1000-1
+`define DIVVAL3 50-1
+`endif
+
+`define FUSS_WARTEN       4  //Wartezeit
+`define GELB_DAUER        4  //Wartezeit 
+`define FUSS_GRUEN_DAUER  4  //Wartezeit
+`define ALLE_ROT_DAUER    4  //Wartezeit
+
+`define HAUPT_GRUEN_DAUER 4  //Wartezeit
+`define NEBEN_GRUEN_DAUER 4  //Wartezeit
+
+
+`define PHASEVAL 8
+
+//clock divider to generate 1 Hz
+//
+
+assign en_div_1 = 1'b1;
+assign en_div_2 = tc_div_1;
+assign en_div_3 = tc_div_1 & tc_div_2;
+
+always  begin
+      CLOCK_ENABLE = tc_div_3;
+end
+
+// synchronisze KEY to CLOCK_50
+always @(posedge CLOCK_50) begin
+      MELDER_Q = ~KEY[0];
+      MELDER_QQ = MELDER_Q;
+end
+
+// Melder sofort setzen 
+// Melder zuruecksetzen wenn die Anforderung von der Statemachine verarbeitet
+// wurde. Die Ampelanlage gibt den FUSSGAENGERn nur dann gruen wenn
+// ein Melder anstehst...			
+always @(posedge CLOCK_50 or negedge RESET) begin
+  if (RESET)
+    MELDER <= 1'b0;
+  else begin
+      case ({MELDER_QQ, MELDER_ACK})
+            2'b01: MELDER <= 1'b0;
+            2'b10: MELDER <= 1'b1;
+            2'b11: MELDER <= ~MELDER;
+            default: ;
+      endcase
+  end 	
+end   
+
+assign WARTEN_FERTIG = (WARTEZAEHLER == 4'b0000);
+
+//Wartezaehler
+always @(posedge CLOCK_50 or RESET) begin
+      if(RST) begin
+            WARTEZAEHLER <= WARTEWERT;
+      end
+      else if(CLOCK_ENABLE)  begin
+            if (START_WARTEN)
+                  WARTEZAEHLER <= WARTEWERT;
+                  START_WARTEN <= 1'b0;
+            if (~WARTEN_FERTIG)
+                  WARTEZAEHLER <= WARTEZAEHLER - 1'b1;
+      end
+end
+
+always @(posedge CLOCK_50 or negedge RESET)
+  if (RESET)
+    begin
+    HAUPTSTR     <= AUTO_GRUEN;
+    NEBENSTR     <= AUTO_ROT;
+    FUSSGAENGER  <= FUSS_ROT;
+    START_WARTEN <= 1'b0;
+    STATE        <= 4'd0;
+    MELDER_ACK   <= 1'b0;
+    end
+  else
+  if (CLOCK_ENABLE)
+  case (STATE)
+    4'd0: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR <= AUTO_GRUEN;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= HAUPT_GRUEN_DAUER;
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end        
+    4'd1: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR = AUTO_GELB;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= GELB_DAUER;
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end
+    4'd2: begin
+            if(WARTEN_FERTIG && MELDER) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= FUSS_WARTEN;
+                  MELDER_ACK <= 1'b1; 
+
+            end else if (WARTEN_FERTIG && ~MELDER) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= ALLE_ROT_DAUER;
+
+            end else if(~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+            end
+          end
+    4'd3: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_GRUEN;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= FUSS_GRUEN_DAUER;
+                  MELDER_ACK <= 1'b0;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end 
+    4'd4: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_GELB|AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= GELB_DAUER;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end
+    4'd5: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_GRUEN;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT = NEBEN_GRUEN_DAUER;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end
+    4'd6: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR = AUTO_ROT;
+                  NEBENSTR = AUTO_GELB;
+                  FUSSGAENGER = FUSS_ROT;
+                  START_WARTEN = 1'b1;
+                  WARTEWERT = GELB_DAUER;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end     
+    4'd7: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR = AUTO_ROT;
+                  NEBENSTR = AUTO_ROT;
+                  FUSSGAENGER = FUSS_ROT;
+                  START_WARTEN = 1'b1;
+                  WARTEWERT = ALLE_ROT_DAUER;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end     
+    4'd8: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR = AUTO_GELB|AUTO_ROT;
+                  NEBENSTR = AUTO_ROT;
+                  FUSSGAENGER = FUSS_ROT;
+                  START_WARTEN = 1'b1;
+                  WARTEWERT = GELB_DAUER;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end     
+    default:                      
+          STATE <= 4'd1;
+  endcase
+
+mod_n_counter_10bit #(.N(DIVVAL1)) clock_divider_1(
+      .CLK(CLOCK_50),
+      .RST(RESET),
+      .EN(en_div_1),
+      .Q(q_div_1),
+      .TC(tc_div_1)
+);
+
+mod_n_counter_10bit #(.N(DIVVAL1)) clock_divider_2(
+      .CLK(CLOCK_50),
+      .RST(RESET),
+      .EN(en_div_2),
+      .Q(q_div_2),
+      .TC(tc_div_2)
+);
+
+mod_n_counter_10bit #(.N(DIVVAL3)) clock_divider_3(
+      .CLK(CLOCK_50),
+      .RST(RESET),
+      .EN(en_div_3),
+      .Q(q_div_3),
+      .TC(tc_div_3)
+);
+                        
+endmodule
diff --git a/labor_3/Ãœbungen/ampel/src/ampel_wo_src.v b/labor_3/Ãœbungen/ampel/src/ampel_wo_src.v
deleted file mode 100644
index 03994c7..0000000
--- a/labor_3/Ãœbungen/ampel/src/ampel_wo_src.v
+++ /dev/null
@@ -1,159 +0,0 @@
-/******************************************************
-*                                                     
-*  Description:  Vorlage Ampelsteurerung                                
-*         Date:  05.01.2018                          
-*    File Name:  ampel_wo_src.v                              
-*      Version:  1.2                                  
-*       Target:  Simulation and Synthesis             
-*   Technology:                                       
-*                                                     
-* Rev   Author   Date          Changes                
-* -----------------------------------------------------
-* 1.0   RHK      10.10.2011    Initial Release        
-* 1.1   JZ       10.03.2016    several bugfixes
-* 1.2   JZ       05.01.2018    angepasst auf neues Ampelboard
-* 1.3   MW       07.03.2019    STATE Konstanten angepasst
-*******************************************************/
-
-`timescale 1ns / 1ps
-
-module ampel (
-  input              CLOCK_50,
-  input        [1:0] KEY,
-  output       [2:0] LEDH_L,
-  output       [2:0] LEDH_R,
-  output       [2:0] LEDN_L,
-  output       [2:0] LEDN_R,
-  output       [1:0] LEDF_L,
-  output       [1:0] LEDF_R, 
-  output reg			DBG  
-);
-
-reg [9:0] CLKDIV1;
-reg [9:0] CLKDIV2;
-reg [9:0] CLKDIV3;
-
-reg MELDER;
-reg MELDER_Q;
-reg MELDER_QQ;
-reg MELDER_ACK;
-reg CLOCK_ENABLE;
-
-reg START_WARTEN;
-reg [3:0] STATE;
-reg [2:0] HAUPTSTR;
-reg [2:0] NEBENSTR;
-reg [1:0] FUSSGAENGER;
-
-reg [3:0] WARTEZAEHLER;
-reg [3:0] WARTEWERT;
-
-//                       R Gr
-parameter FUSS_AUS   = 2'b00;
-parameter FUSS_ROT   = 2'b10;
-parameter FUSS_GRUEN = 2'b01;
-//                      R Ge Gr
-parameter AUTO_AUS   = 3'b000;
-parameter AUTO_ROT   = 3'b100;
-parameter AUTO_GELB  = 3'b010;
-parameter AUTO_GRUEN = 3'b001;
-
-assign RESETn                     = KEY[1];
-
-assign LEDH_L  = HAUPTSTR;
-assign LEDH_R  = HAUPTSTR;
-assign LEDN_L = NEBENSTR;
-assign LEDN_R = NEBENSTR;
-assign LEDF_L = FUSSGAENGER;
-assign LEDF_R = FUSSGAENGER;
-
-`ifdef SIMULATION
-`define DIVVAL1 10-1
-`define DIVVAL3 5-1
-`else
-`define DIVVAL1 1000-1
-`define DIVVAL3 50-1
-`endif
-
-`define FUSS_WARTEN       4  //Wartezeit
-`define GELB_DAUER        4  //Wartezeit 
-`define FUSS_GRUEN_DAUER  4  //Wartezeit
-`define ALLE_ROT_DAUER    4  //Wartezeit
-
-`define HAUPT_GRUEN_DAUER 4  //Wartezeit
-`define NEBEN_GRUEN_DAUER 4  //Wartezeit
-
-
-`define PHASEVAL 8
-
-//clock divider to generate 1 Hz
-//
-
-// HIER IHREN CODE EINFÃœGEN
-
-
-// synchronisze KEY to CLOCK_50
-always @(posedge CLOCK_50) begin
-// HIER IHREN CODE EINFÃœGEN
-end
-
-// Melder sofort setzen 
-// Melder zuruecksetzen wenn die Anforderung von der Statemachine verarbeitet
-// wurde. Die Ampelanlage gibt den FUSSGAENGERn nur dann gruen wenn
-// ein Melder anstehst...			
-always @(posedge CLOCK_50 or negedge RESETn) begin
-  if (~RESETn)
-    MELDER <= 1'b0;
-  else begin
-// HIER IHREN CODE EINFÃœGEN
-  end 	
-end            
-
-//Wartezaehler
-// HIER IHREN CODE EINFÃœGEN
-
-assign WARTEN_FERTIG =  // HIER IHREN CODE EINFÃœGEN;
-
-
-always @(posedge CLOCK_50 or negedge RESETn)
-  if (~RESETn)
-    begin
-    HAUPTSTR     <= AUTO_GRUEN;
-    NEBENSTR     <= AUTO_ROT;
-    FUSSGAENGER  <= FUSS_ROT;
-    START_WARTEN <= 1'b0;
-    STATE        <= 4'd0;
-    MELDER_ACK   <= 1'b0;
-    end
-  else
-  if (CLOCK_ENABLE)
-  case (STATE)
-    4'd0: begin
-
-          end        
-    4'd1: begin
-
-          end
-    4'd2: begin
-
-          end
-    4'd3: begin
-
-          end 
-    4'd4: begin
-    
-          end
-    4'd5: begin
-    
-          end
-    4'd6: begin
-    
-          end     
-    4'd7: begin
-    
-          end     
-    default:                      
-          STATE <= 4'd1;
-  endcase
-                        
-endmodule
diff --git a/labor_3/Ãœbungen/ampel/src/jk_ff.v b/labor_3/Ãœbungen/ampel/src/jk_ff.v
new file mode 100644
index 0000000..ea8b0ad
--- /dev/null
+++ b/labor_3/Ãœbungen/ampel/src/jk_ff.v
@@ -0,0 +1,38 @@
+//Modellierung eines jk-ff
+//Autor: M. Erdem
+//Mat.-Nr.: 8757524
+//Datum: 21.02.2024
+
+module jk_ff (
+    //Ein- und Ausgänge anlegen
+    R,
+    CLK,
+    EN,
+    J,
+    K,
+    Q
+);    
+    input R, CLK, EN, J, K;
+    output reg Q;
+
+    //Verhaltensbeschreibung
+    always @(R or posedge CLK) begin
+
+        //Bei einem Reset soll Q auf 0 gesetzt werden
+        if(R) begin
+            Q <= 1'b0;
+
+            //Wenn EN = 1 dann soll das Modul aktiv sein
+        end else if (EN) begin
+
+            //Zustände von J und K werden analysiert und entsprechend Q angesteuert.
+            //Hierbei ist J Bit Nr. 1 und K ist Bit Nr. 0. (Von Rechts nach Links.)
+            case ({J, K})
+                2'b01: Q <= 1'b0;
+                2'b10: Q <= 1'b1;
+                2'b11: Q <= ~Q;
+                default: ;
+            endcase
+        end
+    end
+endmodule
\ No newline at end of file