Vorbereitungsaufgabe 2:

- Das Zeichen "-" in den Dateinamen musste in "_" umgeändert werden.
- Simulation lauffähig gemacht
- Wave Konfiguration angelegt
- Logik der Testbench angepasst
- Aufgabe abgeschlossen
(- ChatGPT bewerten lassen)
- Kommentare eingefügt

labor_3/README.md

@@ -9,7 +9,7 @@ Aufgabenstellung aus der Email:
 - Zustandsdiagramm der Ampelsteuerung vorbereiten
     - In Teams und Share gibt es das Projekt 'ampel'
     - Simulierung in Modelsim möglich
-        - kompiliertes Moduke 'ampel' in Lirary 'designlib' unter der Library 'work'
+        - kompiliertes Module 'ampel' in Library 'designlib' unter der Library 'work'
         - Zustandsdiagramm per Reverse Engineering aus der Simulation entwickeln
 
 ### Hinweise zur Vorbereitung 1

labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/modelsim.ini

@@ -0,0 +1,324 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+;
+; Verilog Section
+;
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license isn't available
+; viewsim	Try for viewer license but accept simulator license(s) instead
+;		of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type).  Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and 
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer).  The other settings
+; are to send messages only to the transcript or only to the 
+; wlf file.  The valid values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both

labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/sim_jk_ff.tcl

@@ -0,0 +1,27 @@
+# simulation control script für jk-ff Testbench
+#Autor: M. Erdem
+#Mat.-Nr.: 8757524
+#Datum: 21.02.2024
+
+# Vorbereitung der work Library
+file delete -force work
+vlib work
+vmap work work
+
+# Kompiliere Testbench
+puts "Compile Testbench"
+vlog tb_jk_ff.v
+
+# Kompiliere dut Module
+puts "Compile DUT module"
+vlog    ../src/jk_ff.v \
+
+# Starten der Simulation
+puts "Starting Simulation"
+vsim -c -t ps tb_jk_ff
+
+# Darstellung des Graphen
+do wave_jk_ff.tcl
+
+# Simulation Berechnen für angegebene Zeit
+run 300 ns

labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/tb_jk_ff.v

@@ -0,0 +1,96 @@
+//Testbench: jk-ff
+//Autor: M. Erdem
+//Mat.-Nr.: 8757524
+//Datum: 21.02.2024
+
+//Einstellung der Zeitskalierung
+`timescale 1ns/1ps
+
+module tb_jk_ff();
+
+//Definition globaler Pins
+reg clk;
+reg res;
+reg en;
+
+//Definition der Ein- und Ausgänge vom dut
+reg dut_j;
+reg dut_k;
+
+wire dut_q;
+
+//Zählervariable i
+integer i;
+
+//Zu Beginn werden alle Pins auf 0 gesetzt.
+initial begin
+    clk = 1'b0;
+    res = 1'b0;
+    en = 1'b0;
+    dut_j = 1'b0;
+    dut_k = 1'b0;
+end
+
+//Starten eines Clocks mit 50 kHz
+always begin
+    #10 clk = ~clk;
+end
+
+//Ablauf des Testszenarios
+initial begin
+
+    //Warte 4 Clock-Zyklen
+    for (i=0;i<4;i=i+1) begin
+        @ (negedge clk);
+    end
+   
+   //Reset ein und aus
+    res = ~res;
+    #40
+    res = ~res;
+    
+    //Alle Schaltmöglichkeiten für JK probieren
+    //Es wird immer auf eine neg. Flanke des clk gewartet, damit das Signal bei einer pos. Flanke bereits anliegt.
+    @ (negedge clk);
+    dut_j = 1'b0;
+    dut_k = 1'b1;
+    @ (negedge clk);
+    dut_j = 1'b1;
+    dut_k = 1'b0;
+    @ (negedge clk);
+    dut_j = 1'b1;
+    dut_k = 1'b1;
+    @ (negedge clk);
+    dut_j = 1'b0;
+    dut_k = 1'b0;
+    
+    //Enable Eingang aktivieren
+    en = 1'b1;
+
+    //Alle Schaltmöglichkeiten für JK probieren
+    @ (negedge clk);
+    dut_j = 1'b0;
+    dut_k = 1'b1;
+    @ (negedge clk);
+    dut_j = 1'b1;
+    dut_k = 1'b0;
+    @ (negedge clk);
+    dut_j = 1'b1;
+    dut_k = 1'b1;
+    @ (negedge clk);
+    dut_j = 1'b0;
+    dut_k = 1'b0;
+    #20;
+end
+
+//Instanziierung des jk-ff
+jk_ff dut(
+    .R(res),
+    .CLK(clk),
+    .EN(en),
+    .J(dut_j),
+    .K(dut_k),
+    .Q(dut_q)
+);
+
+endmodule

labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/wave_jk_ff.tcl

@@ -0,0 +1,26 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /tb_jk_ff/clk
+add wave -noupdate /tb_jk_ff/res
+add wave -noupdate /tb_jk_ff/en
+add wave -noupdate /tb_jk_ff/dut_j
+add wave -noupdate /tb_jk_ff/dut_k
+add wave -noupdate /tb_jk_ff/dut_q
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {299767 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 5000
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {315 ns}

labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/_info

@@ -0,0 +1,43 @@
+m255
+K3
+13
+cModel Technology
+Z0 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_3\Vorbereitungsaufgaben\Vorbereitungsaufgabe 2\jk-ff\sim
+vjk_ff
+!i10b 1
+!s100 V0RJkme:RF`4Q=d7T=HdI3
+I6RDN1LRWHoaU2V[WHmgi@2
+VoXdRX^91Bk>:04>jiF40n1
+Z1 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_3\Vorbereitungsaufgaben\Vorbereitungsaufgabe 2\jk-ff\sim
+w1708541791
+8../src/jk_ff.v
+F../src/jk_ff.v
+L0 2
+Z2 OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1708541825.484000
+!s107 ../src/jk_ff.v|
+!s90 -reportprogress|300|../src/jk_ff.v|
+!s101 -O0
+o-O0
+vtb_jk_ff
+Z3 ISgG=LbWX]jL6OJOWU_5jb2
+Z4 VUT[Z^]I>AQgS]P1gjENDb3
+R1
+Z5 w1708541779
+Z6 8tb_jk_ff.v
+Z7 Ftb_jk_ff.v
+L0 6
+R2
+r1
+31
+o-O0
+!i10b 1
+Z8 !s100 K>`z4HiDMJNSBP<cdOW7K3
+!s85 0
+Z9 !s108 1708541825.331000
+Z10 !s107 tb_jk_ff.v|
+Z11 !s90 -reportprogress|300|tb_jk_ff.v|
+!s101 -O0

labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/_vmake

@@ -0,0 +1,3 @@
+m255
+K3
+cModel Technology

labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/jk_ff/_primary.vhd

@@ -0,0 +1,12 @@
+library verilog;
+use verilog.vl_types.all;
+entity jk_ff is
+    port(
+        R               : in     vl_logic;
+        CLK             : in     vl_logic;
+        EN              : in     vl_logic;
+        J               : in     vl_logic;
+        K               : in     vl_logic;
+        Q               : out    vl_logic
+    );
+end jk_ff;

labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/sim/work/tb_jk_ff/_primary.vhd

@@ -0,0 +1,4 @@
+library verilog;
+use verilog.vl_types.all;
+entity tb_jk_ff is
+end tb_jk_ff;

labor_3/Vorbereitungsaufgaben/Vorbereitungsaufgabe 2/jk-ff/src/jk_ff.v

@@ -0,0 +1,38 @@
+//Modellierung eines jk-ff
+//Autor: M. Erdem
+//Mat.-Nr.: 8757524
+//Datum: 21.02.2024
+
+module jk_ff (
+    //Ein- und Ausgänge anlegen
+    R,
+    CLK,
+    EN,
+    J,
+    K,
+    Q
+);    
+    input R, CLK, EN, J, K;
+    output reg Q;
+
+    //Verhaltensbeschreibung
+    always @(R or posedge CLK) begin
+
+        //Bei einem Reset soll Q auf 0 gesetzt werden
+        if(R) begin
+            Q <= 1'b0;
+
+            //Wenn EN = 1 dann soll das Modul aktiv sein
+        end else if (EN) begin
+
+            //Zustände von J und K werden analysiert und entsprechend Q angesteuert.
+            //Hierbei ist J Bit Nr. 1 und K ist Bit Nr. 0. (Von Rechts nach Links.)
+            case ({J, K})
+                2'b01: Q <= 1'b0;
+                2'b10: Q <= 1'b1;
+                2'b11: Q <= ~Q;
+                default: ;
+            endcase
+        end
+    end
+endmodule

labor_3/res/ampel/quartus/ampel.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 21:34:38  February 28, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "12.1"
+DATE = "21:34:38  February 28, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "ampel"

labor_3/res/ampel/quartus/ampel.qsf

@@ -0,0 +1,500 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 21:34:38  February 28, 2017
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		ampel_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C35F672C6
+set_global_assignment -name TOP_LEVEL_ENTITY ampel
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:34:38  FEBRUARY 28, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_location_assignment PIN_N25 -to SW[0]
+set_location_assignment PIN_N26 -to SW[1]
+set_location_assignment PIN_P25 -to SW[2]
+set_location_assignment PIN_AE14 -to SW[3]
+set_location_assignment PIN_AF14 -to SW[4]
+set_location_assignment PIN_AD13 -to SW[5]
+set_location_assignment PIN_AC13 -to SW[6]
+set_location_assignment PIN_C13 -to SW[7]
+set_location_assignment PIN_B13 -to SW[8]
+set_location_assignment PIN_A13 -to SW[9]
+set_location_assignment PIN_N1 -to SW[10]
+set_location_assignment PIN_P1 -to SW[11]
+set_location_assignment PIN_P2 -to SW[12]
+set_location_assignment PIN_T7 -to SW[13]
+set_location_assignment PIN_U3 -to SW[14]
+set_location_assignment PIN_U4 -to SW[15]
+set_location_assignment PIN_V1 -to SW[16]
+set_location_assignment PIN_V2 -to SW[17]
+set_location_assignment PIN_T6 -to DRAM_ADDR[0]
+set_location_assignment PIN_V4 -to DRAM_ADDR[1]
+set_location_assignment PIN_V3 -to DRAM_ADDR[2]
+set_location_assignment PIN_W2 -to DRAM_ADDR[3]
+set_location_assignment PIN_W1 -to DRAM_ADDR[4]
+set_location_assignment PIN_U6 -to DRAM_ADDR[5]
+set_location_assignment PIN_U7 -to DRAM_ADDR[6]
+set_location_assignment PIN_U5 -to DRAM_ADDR[7]
+set_location_assignment PIN_W4 -to DRAM_ADDR[8]
+set_location_assignment PIN_W3 -to DRAM_ADDR[9]
+set_location_assignment PIN_Y1 -to DRAM_ADDR[10]
+set_location_assignment PIN_V5 -to DRAM_ADDR[11]
+set_location_assignment PIN_AE2 -to DRAM_BA_0
+set_location_assignment PIN_AE3 -to DRAM_BA_1
+set_location_assignment PIN_AB3 -to DRAM_CAS_N
+set_location_assignment PIN_AA6 -to DRAM_CKE
+set_location_assignment PIN_AA7 -to DRAM_CLK
+set_location_assignment PIN_AC3 -to DRAM_CS_N
+set_location_assignment PIN_V6 -to DRAM_DQ[0]
+set_location_assignment PIN_AA2 -to DRAM_DQ[1]
+set_location_assignment PIN_AA1 -to DRAM_DQ[2]
+set_location_assignment PIN_Y3 -to DRAM_DQ[3]
+set_location_assignment PIN_Y4 -to DRAM_DQ[4]
+set_location_assignment PIN_R8 -to DRAM_DQ[5]
+set_location_assignment PIN_T8 -to DRAM_DQ[6]
+set_location_assignment PIN_V7 -to DRAM_DQ[7]
+set_location_assignment PIN_W6 -to DRAM_DQ[8]
+set_location_assignment PIN_AB2 -to DRAM_DQ[9]
+set_location_assignment PIN_AB1 -to DRAM_DQ[10]
+set_location_assignment PIN_AA4 -to DRAM_DQ[11]
+set_location_assignment PIN_AA3 -to DRAM_DQ[12]
+set_location_assignment PIN_AC2 -to DRAM_DQ[13]
+set_location_assignment PIN_AC1 -to DRAM_DQ[14]
+set_location_assignment PIN_AA5 -to DRAM_DQ[15]
+set_location_assignment PIN_AD2 -to DRAM_LDQM
+set_location_assignment PIN_Y5 -to DRAM_UDQM
+set_location_assignment PIN_AB4 -to DRAM_RAS_N
+set_location_assignment PIN_AD3 -to DRAM_WE_N
+set_location_assignment PIN_AC18 -to FL_ADDR[0]
+set_location_assignment PIN_AB18 -to FL_ADDR[1]
+set_location_assignment PIN_AE19 -to FL_ADDR[2]
+set_location_assignment PIN_AF19 -to FL_ADDR[3]
+set_location_assignment PIN_AE18 -to FL_ADDR[4]
+set_location_assignment PIN_AF18 -to FL_ADDR[5]
+set_location_assignment PIN_Y16 -to FL_ADDR[6]
+set_location_assignment PIN_AA16 -to FL_ADDR[7]
+set_location_assignment PIN_AD17 -to FL_ADDR[8]
+set_location_assignment PIN_AC17 -to FL_ADDR[9]
+set_location_assignment PIN_AE17 -to FL_ADDR[10]
+set_location_assignment PIN_AF17 -to FL_ADDR[11]
+set_location_assignment PIN_W16 -to FL_ADDR[12]
+set_location_assignment PIN_W15 -to FL_ADDR[13]
+set_location_assignment PIN_AC16 -to FL_ADDR[14]
+set_location_assignment PIN_AD16 -to FL_ADDR[15]
+set_location_assignment PIN_AE16 -to FL_ADDR[16]
+set_location_assignment PIN_AC15 -to FL_ADDR[17]
+set_location_assignment PIN_AB15 -to FL_ADDR[18]
+set_location_assignment PIN_AA15 -to FL_ADDR[19]
+set_location_assignment PIN_Y15 -to FL_ADDR[20]
+set_location_assignment PIN_Y14 -to FL_ADDR[21]
+set_location_assignment PIN_V17 -to FL_CE_N
+set_location_assignment PIN_W17 -to FL_OE_N
+set_location_assignment PIN_AD19 -to FL_DQ[0]
+set_location_assignment PIN_AC19 -to FL_DQ[1]
+set_location_assignment PIN_AF20 -to FL_DQ[2]
+set_location_assignment PIN_AE20 -to FL_DQ[3]
+set_location_assignment PIN_AB20 -to FL_DQ[4]
+set_location_assignment PIN_AC20 -to FL_DQ[5]
+set_location_assignment PIN_AF21 -to FL_DQ[6]
+set_location_assignment PIN_AE21 -to FL_DQ[7]
+set_location_assignment PIN_AA18 -to FL_RST_N
+set_location_assignment PIN_AA17 -to FL_WE_N
+set_location_assignment PIN_AF10 -to HEX0[0]
+set_location_assignment PIN_AB12 -to HEX0[1]
+set_location_assignment PIN_AC12 -to HEX0[2]
+set_location_assignment PIN_AD11 -to HEX0[3]
+set_location_assignment PIN_AE11 -to HEX0[4]
+set_location_assignment PIN_V14 -to HEX0[5]
+set_location_assignment PIN_V13 -to HEX0[6]
+set_location_assignment PIN_V20 -to HEX1[0]
+set_location_assignment PIN_V21 -to HEX1[1]
+set_location_assignment PIN_W21 -to HEX1[2]
+set_location_assignment PIN_Y22 -to HEX1[3]
+set_location_assignment PIN_AA24 -to HEX1[4]
+set_location_assignment PIN_AA23 -to HEX1[5]
+set_location_assignment PIN_AB24 -to HEX1[6]
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_V22 -to HEX2[1]
+set_location_assignment PIN_AC25 -to HEX2[2]
+set_location_assignment PIN_AC26 -to HEX2[3]
+set_location_assignment PIN_AB26 -to HEX2[4]
+set_location_assignment PIN_AB25 -to HEX2[5]
+set_location_assignment PIN_Y24 -to HEX2[6]
+set_location_assignment PIN_Y23 -to HEX3[0]
+set_location_assignment PIN_AA25 -to HEX3[1]
+set_location_assignment PIN_AA26 -to HEX3[2]
+set_location_assignment PIN_Y26 -to HEX3[3]
+set_location_assignment PIN_Y25 -to HEX3[4]
+set_location_assignment PIN_U22 -to HEX3[5]
+set_location_assignment PIN_W24 -to HEX3[6]
+set_location_assignment PIN_U9 -to HEX4[0]
+set_location_assignment PIN_U1 -to HEX4[1]
+set_location_assignment PIN_U2 -to HEX4[2]
+set_location_assignment PIN_T4 -to HEX4[3]
+set_location_assignment PIN_R7 -to HEX4[4]
+set_location_assignment PIN_R6 -to HEX4[5]
+set_location_assignment PIN_T3 -to HEX4[6]
+set_location_assignment PIN_T2 -to HEX5[0]
+set_location_assignment PIN_P6 -to HEX5[1]
+set_location_assignment PIN_P7 -to HEX5[2]
+set_location_assignment PIN_T9 -to HEX5[3]
+set_location_assignment PIN_R5 -to HEX5[4]
+set_location_assignment PIN_R4 -to HEX5[5]
+set_location_assignment PIN_R3 -to HEX5[6]
+set_location_assignment PIN_R2 -to HEX6[0]
+set_location_assignment PIN_P4 -to HEX6[1]
+set_location_assignment PIN_P3 -to HEX6[2]
+set_location_assignment PIN_M2 -to HEX6[3]
+set_location_assignment PIN_M3 -to HEX6[4]
+set_location_assignment PIN_M5 -to HEX6[5]
+set_location_assignment PIN_M4 -to HEX6[6]
+set_location_assignment PIN_L3 -to HEX7[0]
+set_location_assignment PIN_L2 -to HEX7[1]
+set_location_assignment PIN_L9 -to HEX7[2]
+set_location_assignment PIN_L6 -to HEX7[3]
+set_location_assignment PIN_L7 -to HEX7[4]
+set_location_assignment PIN_P9 -to HEX7[5]
+set_location_assignment PIN_N9 -to HEX7[6]
+set_location_assignment PIN_G26 -to KEY[0]
+set_location_assignment PIN_N23 -to KEY[1]
+set_location_assignment PIN_P23 -to KEY[2]
+set_location_assignment PIN_W26 -to KEY[3]
+set_location_assignment PIN_AE23 -to LEDR[0]
+set_location_assignment PIN_AF23 -to LEDR[1]
+set_location_assignment PIN_AB21 -to LEDR[2]
+set_location_assignment PIN_AC22 -to LEDR[3]
+set_location_assignment PIN_AD22 -to LEDR[4]
+set_location_assignment PIN_AD23 -to LEDR[5]
+set_location_assignment PIN_AD21 -to LEDR[6]
+set_location_assignment PIN_AC21 -to LEDR[7]
+set_location_assignment PIN_AA14 -to LEDR[8]
+set_location_assignment PIN_Y13 -to LEDR[9]
+set_location_assignment PIN_AA13 -to LEDR[10]
+set_location_assignment PIN_AC14 -to LEDR[11]
+set_location_assignment PIN_AD15 -to LEDR[12]
+set_location_assignment PIN_AE15 -to LEDR[13]
+set_location_assignment PIN_AF13 -to LEDR[14]
+set_location_assignment PIN_AE13 -to LEDR[15]
+set_location_assignment PIN_AE12 -to LEDR[16]
+set_location_assignment PIN_AD12 -to LEDR[17]
+set_location_assignment PIN_AE22 -to LEDG[0]
+set_location_assignment PIN_AF22 -to LEDG[1]
+set_location_assignment PIN_W19 -to LEDG[2]
+set_location_assignment PIN_V18 -to LEDG[3]
+set_location_assignment PIN_U18 -to LEDG[4]
+set_location_assignment PIN_U17 -to LEDG[5]
+set_location_assignment PIN_AA20 -to LEDG[6]
+set_location_assignment PIN_Y18 -to LEDG[7]
+set_location_assignment PIN_Y12 -to LEDG[8]
+set_location_assignment PIN_D13 -to CLOCK_27
+set_location_assignment PIN_N2 -to CLOCK_50
+set_location_assignment PIN_P26 -to EXT_CLOCK
+set_location_assignment PIN_D26 -to PS2_CLK
+set_location_assignment PIN_C24 -to PS2_DAT
+set_location_assignment PIN_C25 -to UART_RXD
+set_location_assignment PIN_B25 -to UART_TXD
+set_location_assignment PIN_K4 -to LCD_RW
+set_location_assignment PIN_K3 -to LCD_EN
+set_location_assignment PIN_K1 -to LCD_RS
+set_location_assignment PIN_J1 -to LCD_DATA[0]
+set_location_assignment PIN_J2 -to LCD_DATA[1]
+set_location_assignment PIN_H1 -to LCD_DATA[2]
+set_location_assignment PIN_H2 -to LCD_DATA[3]
+set_location_assignment PIN_J4 -to LCD_DATA[4]
+set_location_assignment PIN_J3 -to LCD_DATA[5]
+set_location_assignment PIN_H4 -to LCD_DATA[6]
+set_location_assignment PIN_H3 -to LCD_DATA[7]
+set_location_assignment PIN_L4 -to LCD_ON
+set_location_assignment PIN_K2 -to LCD_BLON
+set_location_assignment PIN_AE4 -to SRAM_ADDR[0]
+set_location_assignment PIN_AF4 -to SRAM_ADDR[1]
+set_location_assignment PIN_AC5 -to SRAM_ADDR[2]
+set_location_assignment PIN_AC6 -to SRAM_ADDR[3]
+set_location_assignment PIN_AD4 -to SRAM_ADDR[4]
+set_location_assignment PIN_AD5 -to SRAM_ADDR[5]
+set_location_assignment PIN_AE5 -to SRAM_ADDR[6]
+set_location_assignment PIN_AF5 -to SRAM_ADDR[7]
+set_location_assignment PIN_AD6 -to SRAM_ADDR[8]
+set_location_assignment PIN_AD7 -to SRAM_ADDR[9]
+set_location_assignment PIN_V10 -to SRAM_ADDR[10]
+set_location_assignment PIN_V9 -to SRAM_ADDR[11]
+set_location_assignment PIN_AC7 -to SRAM_ADDR[12]
+set_location_assignment PIN_W8 -to SRAM_ADDR[13]
+set_location_assignment PIN_W10 -to SRAM_ADDR[14]
+set_location_assignment PIN_Y10 -to SRAM_ADDR[15]
+set_location_assignment PIN_AB8 -to SRAM_ADDR[16]
+set_location_assignment PIN_AC8 -to SRAM_ADDR[17]
+set_location_assignment PIN_AD8 -to SRAM_DQ[0]
+set_location_assignment PIN_AE6 -to SRAM_DQ[1]
+set_location_assignment PIN_AF6 -to SRAM_DQ[2]
+set_location_assignment PIN_AA9 -to SRAM_DQ[3]
+set_location_assignment PIN_AA10 -to SRAM_DQ[4]
+set_location_assignment PIN_AB10 -to SRAM_DQ[5]
+set_location_assignment PIN_AA11 -to SRAM_DQ[6]
+set_location_assignment PIN_Y11 -to SRAM_DQ[7]
+set_location_assignment PIN_AE7 -to SRAM_DQ[8]
+set_location_assignment PIN_AF7 -to SRAM_DQ[9]
+set_location_assignment PIN_AE8 -to SRAM_DQ[10]
+set_location_assignment PIN_AF8 -to SRAM_DQ[11]
+set_location_assignment PIN_W11 -to SRAM_DQ[12]
+set_location_assignment PIN_W12 -to SRAM_DQ[13]
+set_location_assignment PIN_AC9 -to SRAM_DQ[14]
+set_location_assignment PIN_AC10 -to SRAM_DQ[15]
+set_location_assignment PIN_AE10 -to SRAM_WE_N
+set_location_assignment PIN_AD10 -to SRAM_OE_N
+set_location_assignment PIN_AF9 -to SRAM_UB_N
+set_location_assignment PIN_AE9 -to SRAM_LB_N
+set_location_assignment PIN_AC11 -to SRAM_CE_N
+set_location_assignment PIN_K7 -to OTG_ADDR[0]
+set_location_assignment PIN_F2 -to OTG_ADDR[1]
+set_location_assignment PIN_F1 -to OTG_CS_N
+set_location_assignment PIN_G2 -to OTG_RD_N
+set_location_assignment PIN_G1 -to OTG_WR_N
+set_location_assignment PIN_G5 -to OTG_RST_N
+set_location_assignment PIN_F4 -to OTG_DATA[0]
+set_location_assignment PIN_D2 -to OTG_DATA[1]
+set_location_assignment PIN_D1 -to OTG_DATA[2]
+set_location_assignment PIN_F7 -to OTG_DATA[3]
+set_location_assignment PIN_J5 -to OTG_DATA[4]
+set_location_assignment PIN_J8 -to OTG_DATA[5]
+set_location_assignment PIN_J7 -to OTG_DATA[6]
+set_location_assignment PIN_H6 -to OTG_DATA[7]
+set_location_assignment PIN_E2 -to OTG_DATA[8]
+set_location_assignment PIN_E1 -to OTG_DATA[9]
+set_location_assignment PIN_K6 -to OTG_DATA[10]
+set_location_assignment PIN_K5 -to OTG_DATA[11]
+set_location_assignment PIN_G4 -to OTG_DATA[12]
+set_location_assignment PIN_G3 -to OTG_DATA[13]
+set_location_assignment PIN_J6 -to OTG_DATA[14]
+set_location_assignment PIN_K8 -to OTG_DATA[15]
+set_location_assignment PIN_B3 -to OTG_INT0
+set_location_assignment PIN_C3 -to OTG_INT1
+set_location_assignment PIN_C2 -to OTG_DACK0_N
+set_location_assignment PIN_B2 -to OTG_DACK1_N
+set_location_assignment PIN_F6 -to OTG_DREQ0
+set_location_assignment PIN_E5 -to OTG_DREQ1
+set_location_assignment PIN_F3 -to OTG_FSPEED
+set_location_assignment PIN_G6 -to OTG_LSPEED
+set_location_assignment PIN_B14 -to TDI
+set_location_assignment PIN_A14 -to TCS
+set_location_assignment PIN_D14 -to TCK
+set_location_assignment PIN_F14 -to TDO
+set_location_assignment PIN_C4 -to TD_RESET
+set_location_assignment PIN_C8 -to VGA_R[0]
+set_location_assignment PIN_F10 -to VGA_R[1]
+set_location_assignment PIN_G10 -to VGA_R[2]
+set_location_assignment PIN_D9 -to VGA_R[3]
+set_location_assignment PIN_C9 -to VGA_R[4]
+set_location_assignment PIN_A8 -to VGA_R[5]
+set_location_assignment PIN_H11 -to VGA_R[6]
+set_location_assignment PIN_H12 -to VGA_R[7]
+set_location_assignment PIN_F11 -to VGA_R[8]
+set_location_assignment PIN_E10 -to VGA_R[9]
+set_location_assignment PIN_B9 -to VGA_G[0]
+set_location_assignment PIN_A9 -to VGA_G[1]
+set_location_assignment PIN_C10 -to VGA_G[2]
+set_location_assignment PIN_D10 -to VGA_G[3]
+set_location_assignment PIN_B10 -to VGA_G[4]
+set_location_assignment PIN_A10 -to VGA_G[5]
+set_location_assignment PIN_G11 -to VGA_G[6]
+set_location_assignment PIN_D11 -to VGA_G[7]
+set_location_assignment PIN_E12 -to VGA_G[8]
+set_location_assignment PIN_D12 -to VGA_G[9]
+set_location_assignment PIN_J13 -to VGA_B[0]
+set_location_assignment PIN_J14 -to VGA_B[1]
+set_location_assignment PIN_F12 -to VGA_B[2]
+set_location_assignment PIN_G12 -to VGA_B[3]
+set_location_assignment PIN_J10 -to VGA_B[4]
+set_location_assignment PIN_J11 -to VGA_B[5]
+set_location_assignment PIN_C11 -to VGA_B[6]
+set_location_assignment PIN_B11 -to VGA_B[7]
+set_location_assignment PIN_C12 -to VGA_B[8]
+set_location_assignment PIN_B12 -to VGA_B[9]
+set_location_assignment PIN_B8 -to VGA_CLK
+set_location_assignment PIN_D6 -to VGA_BLANK
+set_location_assignment PIN_A7 -to VGA_HS
+set_location_assignment PIN_D8 -to VGA_VS
+set_location_assignment PIN_B7 -to VGA_SYNC
+set_location_assignment PIN_A6 -to I2C_SCLK
+set_location_assignment PIN_B6 -to I2C_SDAT
+set_location_assignment PIN_J9 -to TD_DATA[0]
+set_location_assignment PIN_E8 -to TD_DATA[1]
+set_location_assignment PIN_H8 -to TD_DATA[2]
+set_location_assignment PIN_H10 -to TD_DATA[3]
+set_location_assignment PIN_G9 -to TD_DATA[4]
+set_location_assignment PIN_F9 -to TD_DATA[5]
+set_location_assignment PIN_D7 -to TD_DATA[6]
+set_location_assignment PIN_C7 -to TD_DATA[7]
+set_location_assignment PIN_D5 -to TD_HS
+set_location_assignment PIN_K9 -to TD_VS
+set_location_assignment PIN_C5 -to AUD_ADCLRCK
+set_location_assignment PIN_B5 -to AUD_ADCDAT
+set_location_assignment PIN_C6 -to AUD_DACLRCK
+set_location_assignment PIN_A4 -to AUD_DACDAT
+set_location_assignment PIN_A5 -to AUD_XCK
+set_location_assignment PIN_B4 -to AUD_BCLK
+set_location_assignment PIN_D17 -to ENET_DATA[0]
+set_location_assignment PIN_C17 -to ENET_DATA[1]
+set_location_assignment PIN_B18 -to ENET_DATA[2]
+set_location_assignment PIN_A18 -to ENET_DATA[3]
+set_location_assignment PIN_B17 -to ENET_DATA[4]
+set_location_assignment PIN_A17 -to ENET_DATA[5]
+set_location_assignment PIN_B16 -to ENET_DATA[6]
+set_location_assignment PIN_B15 -to ENET_DATA[7]
+set_location_assignment PIN_B20 -to ENET_DATA[8]
+set_location_assignment PIN_A20 -to ENET_DATA[9]
+set_location_assignment PIN_C19 -to ENET_DATA[10]
+set_location_assignment PIN_D19 -to ENET_DATA[11]
+set_location_assignment PIN_B19 -to ENET_DATA[12]
+set_location_assignment PIN_A19 -to ENET_DATA[13]
+set_location_assignment PIN_E18 -to ENET_DATA[14]
+set_location_assignment PIN_D18 -to ENET_DATA[15]
+set_location_assignment PIN_B24 -to ENET_CLK
+set_location_assignment PIN_A21 -to ENET_CMD
+set_location_assignment PIN_A23 -to ENET_CS_N
+set_location_assignment PIN_B21 -to ENET_INT
+set_location_assignment PIN_A22 -to ENET_RD_N
+set_location_assignment PIN_B22 -to ENET_WR_N
+set_location_assignment PIN_B23 -to ENET_RST_N
+set_location_assignment PIN_AE24 -to IRDA_TXD
+set_location_assignment PIN_AE25 -to IRDA_RXD
+set_location_assignment PIN_AD24 -to SD_DAT
+set_location_assignment PIN_AC23 -to SD_DAT3
+set_location_assignment PIN_Y21 -to SD_CMD
+set_location_assignment PIN_AD25 -to SD_CLK
+set_location_assignment PIN_D25 -to GPIO_0[0]
+set_location_assignment PIN_J22 -to GPIO_0[1]
+set_location_assignment PIN_E26 -to GPIO_0[2]
+set_location_assignment PIN_E25 -to GPIO_0[3]
+set_location_assignment PIN_F24 -to GPIO_0[4]
+set_location_assignment PIN_F23 -to GPIO_0[5]
+set_location_assignment PIN_J21 -to GPIO_0[6]
+set_location_assignment PIN_J20 -to GPIO_0[7]
+set_location_assignment PIN_F25 -to GPIO_0[8]
+set_location_assignment PIN_F26 -to GPIO_0[9]
+set_location_assignment PIN_N18 -to GPIO_0[10]
+set_location_assignment PIN_P18 -to GPIO_0[11]
+set_location_assignment PIN_G23 -to GPIO_0[12]
+set_location_assignment PIN_G24 -to GPIO_0[13]
+set_location_assignment PIN_K22 -to GPIO_0[14]
+set_location_assignment PIN_G25 -to GPIO_0[15]
+set_location_assignment PIN_H23 -to GPIO_0[16]
+set_location_assignment PIN_H24 -to GPIO_0[17]
+set_location_assignment PIN_J23 -to GPIO_0[18]
+set_location_assignment PIN_J24 -to GPIO_0[19]
+set_location_assignment PIN_H25 -to GPIO_0[20]
+set_location_assignment PIN_H26 -to GPIO_0[21]
+set_location_assignment PIN_H19 -to GPIO_0[22]
+set_location_assignment PIN_K18 -to GPIO_0[23]
+set_location_assignment PIN_K19 -to GPIO_0[24]
+set_location_assignment PIN_K21 -to GPIO_0[25]
+set_location_assignment PIN_K23 -to GPIO_0[26]
+set_location_assignment PIN_K24 -to GPIO_0[27]
+set_location_assignment PIN_L21 -to GPIO_0[28]
+set_location_assignment PIN_L20 -to GPIO_0[29]
+set_location_assignment PIN_J25 -to GPIO_0[30]
+set_location_assignment PIN_J26 -to GPIO_0[31]
+set_location_assignment PIN_L23 -to GPIO_0[32]
+set_location_assignment PIN_L24 -to GPIO_0[33]
+set_location_assignment PIN_L25 -to GPIO_0[34]
+set_location_assignment PIN_L19 -to GPIO_0[35]
+
+#output       [2:0] LEDH_L,
+set_location_assignment PIN_K25 -to LEDH_L[0]
+set_location_assignment PIN_K26 -to LEDH_L[1]
+set_location_assignment PIN_M22 -to LEDH_L[2]
+#output       [2:0] LEDH_R,
+set_location_assignment PIN_V26 -to LEDH_R[0]
+set_location_assignment PIN_U21 -to LEDH_R[1]
+set_location_assignment PIN_U20 -to LEDH_R[2]
+#output       [2:0] LEDN_L,
+set_location_assignment PIN_V23 -to LEDN_L[0]
+set_location_assignment PIN_V24 -to LEDN_L[1]
+set_location_assignment PIN_V25 -to LEDN_L[2]  
+#output       [2:0] LEDN_R,
+set_location_assignment PIN_M25 -to LEDN_R[0]
+set_location_assignment PIN_M24 -to LEDN_R[1]
+set_location_assignment PIN_M21 -to LEDN_R[2]
+#output       [1:0] LEDF_L,
+set_location_assignment PIN_M19 -to LEDF_L[1]
+set_location_assignment PIN_M23 -to LEDF_L[0]
+#output       [1:0] LEDF_R, 
+set_location_assignment PIN_R19 -to LEDF_R[1]
+set_location_assignment PIN_T19 -to LEDF_R[0]
+
+set_location_assignment PIN_M20 -to GPIO_1[5]
+set_location_assignment PIN_N20 -to GPIO_1[6]
+set_location_assignment PIN_N24 -to GPIO_1[10]
+set_location_assignment PIN_P24 -to GPIO_1[11]
+set_location_assignment PIN_R25 -to GPIO_1[12]
+set_location_assignment PIN_R24 -to GPIO_1[13]
+set_location_assignment PIN_R20 -to GPIO_1[14]
+set_location_assignment PIN_T22 -to GPIO_1[15]
+set_location_assignment PIN_T23 -to GPIO_1[16]
+set_location_assignment PIN_T24 -to GPIO_1[17]
+set_location_assignment PIN_T25 -to GPIO_1[18]
+set_location_assignment PIN_T18 -to GPIO_1[19]
+set_location_assignment PIN_T21 -to GPIO_1[20]
+set_location_assignment PIN_T20 -to GPIO_1[21]
+set_location_assignment PIN_U26 -to GPIO_1[22]
+set_location_assignment PIN_U25 -to GPIO_1[23]
+set_location_assignment PIN_U23 -to GPIO_1[24]
+set_location_assignment PIN_U24 -to GPIO_1[25]
+
+set_location_assignment PIN_U20 -to GPIO_1[28]
+set_location_assignment PIN_U21 -to GPIO_1[29]
+
+
+set_location_assignment PIN_W25 -to GPIO_1[34]
+set_location_assignment PIN_W23 -to GPIO_1[35]
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+set_global_assignment -name VERILOG_FILE ../src/ampel.v
+set_global_assignment -name SDC_FILE ampel.sdc
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

labor_3/res/ampel/quartus/ampel.sdc

@@ -0,0 +1,41 @@
+#************************************************************
+# THIS IS A WIZARD-GENERATED FILE.                           
+#
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+#
+#************************************************************
+
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+# Clock constraints
+
+create_clock -name "CLK50" -period 20.000ns [get_ports {CLOCK_50}]
+
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+#derive_clock_uncertainty
+# Not supported for family Cyclone II
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+

labor_3/res/ampel/sim __quartus13.1__/create_designlib.tcl

@@ -0,0 +1,9 @@
+## CREATE DESIGNLIB
+# there needs to be a folder designlib
+file delete -force designlib
+mkdir designlib
+vlib designlib/ampel
+vmap ampel "designlib/ampel"
+vlog ../src/ampel.v +define+SIMULATION -work ampel
+vlog ../src/mod_n_counter_10bit.v +define+SIMULATION -work ampel
+

labor_3/res/ampel/sim __quartus13.1__/designlib/ampel/_info

@@ -0,0 +1,45 @@
+m255
+K3
+13
+cModel Technology
+Z0 dC:\designs\ampel\sim
+vampel
+IgiF3cjjhn@S2zL[i7OlRF1
+VlCk1Ao:VM2mW]^Odc6Bhj2
+Z1 dC:\designs\ampel\sim
+w1613653211
+8../src/ampel.v
+F../src/ampel.v
+L0 17
+Z2 OV;L;10.1d;51
+r1
+31
+Z3 o-work ampel -O0
+!i10b 1
+!s100 ;LmPghzX9J7gLRTecfgeY3
+!s85 0
+!s108 1613653433.512000
+!s107 ../src/ampel.v|
+!s90 -reportprogress|300|../src/ampel.v|+define+SIMULATION|-work|ampel|
+!s101 -O0
+Z4 !s92 +define+SIMULATION -work ampel -O0
+vmod_n_counter_10bit
+!i10b 1
+!s100 9e`GV_]:ML:l92jkefb>Q0
+IL;d^FF@OdJ:kj4TXO^Q0>3
+VOCKRzhG[H7hm^_`n>48^e3
+R1
+w1580669164
+8../src/mod_n_counter_10bit.v
+F../src/mod_n_counter_10bit.v
+L0 1
+R2
+r1
+!s85 0
+31
+!s108 1613653433.695000
+!s107 ../src/mod_n_counter_10bit.v|
+!s90 -reportprogress|300|../src/mod_n_counter_10bit.v|+define+SIMULATION|-work|ampel|
+!s101 -O0
+R3
+R4

labor_3/res/ampel/sim __quartus13.1__/designlib/ampel/_vmake

@@ -0,0 +1,3 @@
+m255
+K3
+cModel Technology

labor_3/res/ampel/sim __quartus13.1__/designlib/ampel/ampel/_primary.vhd

@@ -0,0 +1,31 @@
+library verilog;
+use verilog.vl_types.all;
+entity ampel is
+    generic(
+        FUSS_AUS        : vl_logic_vector(0 to 1) := (Hi0, Hi0);
+        FUSS_ROT        : vl_logic_vector(0 to 1) := (Hi1, Hi0);
+        FUSS_GRUEN      : vl_logic_vector(0 to 1) := (Hi0, Hi1);
+        AUTO_AUS        : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi0);
+        AUTO_ROT        : vl_logic_vector(0 to 2) := (Hi1, Hi0, Hi0);
+        AUTO_GELB       : vl_logic_vector(0 to 2) := (Hi0, Hi1, Hi0);
+        AUTO_GRUEN      : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi1)
+    );
+    port(
+        CLOCK_50        : in     vl_logic;
+        KEY             : in     vl_logic_vector(1 downto 0);
+        LEDH_L          : out    vl_logic_vector(2 downto 0);
+        LEDH_R          : out    vl_logic_vector(2 downto 0);
+        LEDN_L          : out    vl_logic_vector(2 downto 0);
+        LEDN_R          : out    vl_logic_vector(2 downto 0);
+        LEDF_L          : out    vl_logic_vector(1 downto 0);
+        LEDF_R          : out    vl_logic_vector(1 downto 0)
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of FUSS_AUS : constant is 1;
+    attribute mti_svvh_generic_type of FUSS_ROT : constant is 1;
+    attribute mti_svvh_generic_type of FUSS_GRUEN : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_AUS : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_ROT : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_GELB : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_GRUEN : constant is 1;
+end ampel;

labor_3/res/ampel/sim __quartus13.1__/designlib/ampel/mod_n_counter_10bit/_primary.vhd

@@ -0,0 +1,16 @@
+library verilog;
+use verilog.vl_types.all;
+entity mod_n_counter_10bit is
+    generic(
+        N               : integer := 10
+    );
+    port(
+        CLK             : in     vl_logic;
+        RST             : in     vl_logic;
+        EN              : in     vl_logic;
+        Q               : out    vl_logic_vector(9 downto 0);
+        TC              : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of N : constant is 1;
+end mod_n_counter_10bit;

labor_3/res/ampel/sim __quartus13.1__/modelsim.ini

@@ -0,0 +1,325 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+;
+; Verilog Section
+;
+
+ampel = designlib/ampel
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license isn't available
+; viewsim	Try for viewer license but accept simulator license(s) instead
+;		of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type).  Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and 
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer).  The other settings
+; are to send messages only to the transcript or only to the 
+; wlf file.  The valid values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both

labor_3/res/ampel/sim __quartus13.1__/sim.tcl

@@ -0,0 +1,22 @@
+#JZ 2020
+
+#remove working directory
+file delete -force work
+
+#Creating the work lib
+vlib work
+vmap ampel "designlib/ampel"
+vmap work work
+
+#Top level testbench
+vlog tb_ampel.v
+#vlog ../src/ampel.v +define+SIMULATION
+
+#Simulate
+vsim -c -t ps -L ampel tb_ampel
+#vsim -c -t ps tb_ampel
+
+#get wave
+do wave.do
+
+run 1500 us

labor_3/res/ampel/sim __quartus13.1__/tb_ampel.v

@@ -0,0 +1,67 @@
+/******************************************************
+*                                                     
+*  Description:  tb_ampel                                
+*         Date:  13.01.2018                           
+*    File Name:  tb_ampel.v                              
+*      Version:  1.0                                  
+*       Target:  Simulation             
+*   Technology:                                       
+*                                                     
+* Rev   Author   Date          Changes                
+* -----------------------------------------------------        
+* 1.0   JZ       13.01.2018    Testbench zur Ampelsteuerung
+*******************************************************/
+
+`timescale 1ns / 1ps
+
+module tb_ampel;
+
+reg CLK;
+reg RSTn;
+reg SW;
+
+wire [2:0] HAUPTSTR_LINKS;
+wire [2:0] NEBENSTR_LINKS;
+wire [1:0] FUSSGAENGER_LINKS;
+wire [2:0] HAUPTSTR_RECHTS;
+wire [2:0] NEBENSTR_RECHTS;
+wire [1:0] FUSSGAENGER_RECHTS;
+
+//50 MHz clock
+initial
+  begin
+  CLK  = 1'b0;
+  end
+
+always
+  CLK = #10 ~CLK;
+
+//push buttons
+initial
+  begin
+  RSTn = 1'b1;
+  SW = 1'b1;
+  #100;
+  RSTn = 1'b0;
+  #10;
+  RSTn = 1'b1;
+  #50_000;
+  SW = 1'b0;
+  #100;
+  SW = 1'b1;
+  end
+
+ampel ampel(
+.CLOCK_50 (CLK),
+.KEY ({RSTn, SW}),
+.LEDH_L(HAUPTSTR_LINKS),
+.LEDN_L(NEBENSTR_LINKS),
+.LEDF_L(FUSSGAENGER_LINKS),
+.LEDH_R(HAUPTSTR_RECHTS),
+.LEDN_R(NEBENSTR_RECHTS),
+.LEDF_R(FUSSGAENGER_RECHTS)
+);
+
+
+
+endmodule

labor_3/res/ampel/sim __quartus13.1__/work/_info

@@ -0,0 +1,24 @@
+m255
+K3
+13
+cModel Technology
+Z0 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_3\res\ampel\sim __quartus13.1__
+vtb_ampel
+!i10b 1
+!s100 1oY2jolgFK??ee;z]EH8c2
+I:0IMZj9F7dM=NBGQ@:fYS0
+V6nf?5m:3VQD@E=_a?l5VH1
+Z1 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_3\res\ampel\sim __quartus13.1__
+w1708524120
+8tb_ampel.v
+Ftb_ampel.v
+L0 17
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1708528477.147000
+!s107 tb_ampel.v|
+!s90 -reportprogress|300|tb_ampel.v|
+!s101 -O0
+o-O0

labor_3/res/ampel/sim __quartus13.1__/work/_vmake

@@ -0,0 +1,3 @@
+m255
+K3
+cModel Technology

labor_3/res/ampel/sim __quartus13.1__/work/tb_ampel/_primary.vhd

@@ -0,0 +1,4 @@
+library verilog;
+use verilog.vl_types.all;
+entity tb_ampel is
+end tb_ampel;

labor_3/res/ampel/sim/create_designlib.tcl

@@ -0,0 +1,9 @@
+## CREATE DESIGNLIB
+# there needs to be a folder designlib
+# rm -rf designlib
+# mkdir designlib
+vlib designlib/ampel
+vmap ampel "designlib/ampel"
+vlog ../src/ampel.v +define+SIMULATION -work ampel
+vlog ../src/mod_n_counter_10bit.v +define+SIMULATION -work ampel
+

labor_3/res/ampel/sim/designlib/ampel/_info

@@ -0,0 +1,45 @@
+m255
+K3
+13
+cModel Technology
+Z0 dD:\Unverschluesselt\EDS_UEBUNGEN_2020\ampel\sim
+vampel
+IL]jRSX9lQ5YM508d006DE0
+VlCk1Ao:VM2mW]^Odc6Bhj2
+Z1 dD:\Unverschluesselt\EDS_UEBUNGEN_2020\ampel\sim
+Z2 w1580669164
+8../src/ampel.v
+F../src/ampel.v
+L0 17
+Z3 OV;L;10.1b;51
+r1
+31
+Z4 o-work ampel -O0
+!i10b 1
+!s100 Rg2UN1YACYn>hH5^mG_mX1
+!s85 0
+!s108 1583413383.761000
+!s107 ../src/ampel.v|
+!s90 -reportprogress|300|../src/ampel.v|+define+SIMULATION|-work|ampel|
+!s101 -O0
+Z5 !s92 +define+SIMULATION -work ampel -O0
+vmod_n_counter_10bit
+!i10b 1
+!s100 9e`GV_]:ML:l92jkefb>Q0
+IL;d^FF@OdJ:kj4TXO^Q0>3
+VOCKRzhG[H7hm^_`n>48^e3
+R1
+R2
+8../src/mod_n_counter_10bit.v
+F../src/mod_n_counter_10bit.v
+L0 1
+R3
+r1
+!s85 0
+31
+!s108 1583413384.279000
+!s107 ../src/mod_n_counter_10bit.v|
+!s90 -reportprogress|300|../src/mod_n_counter_10bit.v|+define+SIMULATION|-work|ampel|
+!s101 -O0
+R4
+R5

labor_3/res/ampel/sim/designlib/ampel/_vmake

@@ -0,0 +1,3 @@
+m255
+K3
+cModel Technology

labor_3/res/ampel/sim/designlib/ampel/ampel/_primary.vhd

@@ -0,0 +1,31 @@
+library verilog;
+use verilog.vl_types.all;
+entity ampel is
+    generic(
+        FUSS_AUS        : vl_logic_vector(0 to 1) := (Hi0, Hi0);
+        FUSS_ROT        : vl_logic_vector(0 to 1) := (Hi1, Hi0);
+        FUSS_GRUEN      : vl_logic_vector(0 to 1) := (Hi0, Hi1);
+        AUTO_AUS        : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi0);
+        AUTO_ROT        : vl_logic_vector(0 to 2) := (Hi1, Hi0, Hi0);
+        AUTO_GELB       : vl_logic_vector(0 to 2) := (Hi0, Hi1, Hi0);
+        AUTO_GRUEN      : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi1)
+    );
+    port(
+        CLOCK_50        : in     vl_logic;
+        KEY             : in     vl_logic_vector(1 downto 0);
+        LEDH_L          : out    vl_logic_vector(2 downto 0);
+        LEDH_R          : out    vl_logic_vector(2 downto 0);
+        LEDN_L          : out    vl_logic_vector(2 downto 0);
+        LEDN_R          : out    vl_logic_vector(2 downto 0);
+        LEDF_L          : out    vl_logic_vector(1 downto 0);
+        LEDF_R          : out    vl_logic_vector(1 downto 0)
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of FUSS_AUS : constant is 1;
+    attribute mti_svvh_generic_type of FUSS_ROT : constant is 1;
+    attribute mti_svvh_generic_type of FUSS_GRUEN : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_AUS : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_ROT : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_GELB : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_GRUEN : constant is 1;
+end ampel;

labor_3/res/ampel/sim/designlib/ampel/mod_n_counter_10bit/_primary.vhd

@@ -0,0 +1,16 @@
+library verilog;
+use verilog.vl_types.all;
+entity mod_n_counter_10bit is
+    generic(
+        N               : integer := 10
+    );
+    port(
+        CLK             : in     vl_logic;
+        RST             : in     vl_logic;
+        EN              : in     vl_logic;
+        Q               : out    vl_logic_vector(9 downto 0);
+        TC              : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of N : constant is 1;
+end mod_n_counter_10bit;

labor_3/res/ampel/sim/sim.tcl

@@ -0,0 +1,22 @@
+#JZ 2020
+
+#remove working directory
+file delete -force work
+
+#Creating the work lib
+vlib work
+vmap ampel "designlib/ampel"
+vmap work work
+
+#Top level testbench
+vlog tb_ampel.v
+#vlog ../src/ampel.v +define+SIMULATION
+
+#Simulate
+vsim -c -t ps -L ampel tb_ampel
+#vsim -c -t ps tb_ampel
+
+#get wave
+do wave.do
+
+run 1500 us

labor_3/res/ampel/sim/tb_ampel.v

@@ -0,0 +1,67 @@
+/******************************************************
+*                                                     
+*  Description:  tb_ampel                                
+*         Date:  13.01.2018                           
+*    File Name:  tb_ampel.v                              
+*      Version:  1.0                                  
+*       Target:  Simulation             
+*   Technology:                                       
+*                                                     
+* Rev   Author   Date          Changes                
+* -----------------------------------------------------        
+* 1.0   JZ       13.01.2018    Testbench zur Ampelsteuerung
+*******************************************************/
+
+`timescale 1ns / 1ps
+
+module tb_ampel;
+
+reg CLK;
+reg RSTn;
+reg SW;
+
+wire [2:0] HAUPTSTR_LINKS;
+wire [2:0] NEBENSTR_LINKS;
+wire [1:0] FUSSGAENGER_LINKS;
+wire [2:0] HAUPTSTR_RECHTS;
+wire [2:0] NEBENSTR_RECHTS;
+wire [1:0] FUSSGAENGER_RECHTS;
+
+//50 MHz clock
+initial
+  begin
+  CLK  = 1'b0;
+  end
+
+always
+  CLK = #10 ~CLK;
+
+//push buttons
+initial
+  begin
+  RSTn = 1'b1;
+  SW = 1'b1;
+  #100;
+  RSTn = 1'b0;
+  #10;
+  RSTn = 1'b1;
+  #50_000;
+  SW = 1'b0;
+  #100;
+  SW = 1'b1;
+  end
+
+ampel ampel(
+.CLOCK_50 (CLK),
+.KEY ({RSTn, SW}),
+.LEDH_L(HAUPTSTR_LINKS),
+.LEDN_L(NEBENSTR_LINKS),
+.LEDF_L(FUSSGAENGER_LINKS),
+.LEDH_R(HAUPTSTR_RECHTS),
+.LEDN_R(NEBENSTR_RECHTS),
+.LEDF_R(FUSSGAENGER_RECHTS)
+);
+
+
+
+endmodule

labor_3/res/ampel/src/ampel_wo_src.v

@@ -0,0 +1,159 @@
+/******************************************************
+*                                                     
+*  Description:  Vorlage Ampelsteurerung                                
+*         Date:  05.01.2018                          
+*    File Name:  ampel_wo_src.v                              
+*      Version:  1.2                                  
+*       Target:  Simulation and Synthesis             
+*   Technology:                                       
+*                                                     
+* Rev   Author   Date          Changes                
+* -----------------------------------------------------
+* 1.0   RHK      10.10.2011    Initial Release        
+* 1.1   JZ       10.03.2016    several bugfixes
+* 1.2   JZ       05.01.2018    angepasst auf neues Ampelboard
+* 1.3   MW       07.03.2019    STATE Konstanten angepasst
+*******************************************************/
+
+`timescale 1ns / 1ps
+
+module ampel (
+  input              CLOCK_50,
+  input        [1:0] KEY,
+  output       [2:0] LEDH_L,
+  output       [2:0] LEDH_R,
+  output       [2:0] LEDN_L,
+  output       [2:0] LEDN_R,
+  output       [1:0] LEDF_L,
+  output       [1:0] LEDF_R, 
+  output reg			DBG  
+);
+
+reg [9:0] CLKDIV1;
+reg [9:0] CLKDIV2;
+reg [9:0] CLKDIV3;
+
+reg MELDER;
+reg MELDER_Q;
+reg MELDER_QQ;
+reg MELDER_ACK;
+reg CLOCK_ENABLE;
+
+reg START_WARTEN;
+reg [3:0] STATE;
+reg [2:0] HAUPTSTR;
+reg [2:0] NEBENSTR;
+reg [1:0] FUSSGAENGER;
+
+reg [3:0] WARTEZAEHLER;
+reg [3:0] WARTEWERT;
+
+//                       R Gr
+parameter FUSS_AUS   = 2'b00;
+parameter FUSS_ROT   = 2'b10;
+parameter FUSS_GRUEN = 2'b01;
+//                      R Ge Gr
+parameter AUTO_AUS   = 3'b000;
+parameter AUTO_ROT   = 3'b100;
+parameter AUTO_GELB  = 3'b010;
+parameter AUTO_GRUEN = 3'b001;
+
+assign RESETn                     = KEY[1];
+
+assign LEDH_L  = HAUPTSTR;
+assign LEDH_R  = HAUPTSTR;
+assign LEDN_L = NEBENSTR;
+assign LEDN_R = NEBENSTR;
+assign LEDF_L = FUSSGAENGER;
+assign LEDF_R = FUSSGAENGER;
+
+`ifdef SIMULATION
+`define DIVVAL1 10-1
+`define DIVVAL3 5-1
+`else
+`define DIVVAL1 1000-1
+`define DIVVAL3 50-1
+`endif
+
+`define FUSS_WARTEN       4  //Wartezeit
+`define GELB_DAUER        4  //Wartezeit 
+`define FUSS_GRUEN_DAUER  4  //Wartezeit
+`define ALLE_ROT_DAUER    4  //Wartezeit
+
+`define HAUPT_GRUEN_DAUER 4  //Wartezeit
+`define NEBEN_GRUEN_DAUER 4  //Wartezeit
+
+
+`define PHASEVAL 8
+
+//clock divider to generate 1 Hz
+//
+
+// HIER IHREN CODE EINFÜGEN
+
+
+// synchronisze KEY to CLOCK_50
+always @(posedge CLOCK_50) begin
+// HIER IHREN CODE EINFÜGEN
+end
+
+// Melder sofort setzen 
+// Melder zuruecksetzen wenn die Anforderung von der Statemachine verarbeitet
+// wurde. Die Ampelanlage gibt den FUSSGAENGERn nur dann gruen wenn
+// ein Melder anstehst...			
+always @(posedge CLOCK_50 or negedge RESETn) begin
+  if (~RESETn)
+    MELDER <= 1'b0;
+  else begin
+// HIER IHREN CODE EINFÜGEN
+  end 	
+end            
+
+//Wartezaehler
+// HIER IHREN CODE EINFÜGEN
+
+assign WARTEN_FERTIG =  // HIER IHREN CODE EINFÜGEN;
+
+
+always @(posedge CLOCK_50 or negedge RESETn)
+  if (~RESETn)
+    begin
+    HAUPTSTR     <= AUTO_GRUEN;
+    NEBENSTR     <= AUTO_ROT;
+    FUSSGAENGER  <= FUSS_ROT;
+    START_WARTEN <= 1'b0;
+    STATE        <= 4'd0;
+    MELDER_ACK   <= 1'b0;
+    end
+  else
+  if (CLOCK_ENABLE)
+  case (STATE)
+    4'd0: begin
+
+          end        
+    4'd1: begin
+
+          end
+    4'd2: begin
+
+          end
+    4'd3: begin
+
+          end 
+    4'd4: begin
+    
+          end
+    4'd5: begin
+    
+          end
+    4'd6: begin
+    
+          end     
+    4'd7: begin
+    
+          end     
+    default:                      
+          STATE <= 4'd1;
+  endcase
+                        
+endmodule

labor_3/res/ampel/src/mod_n_counter_10bit.v

@@ -0,0 +1,31 @@
+module mod_n_counter_10bit
+# (parameter N = 10)
+(
+  // module inputs
+  input CLK,
+  input RST,
+  input EN,
+  // module outputs
+  output reg [9:0] Q,
+  output TC
+);
+
+localparam TERMINAL_COUNT = N-1;
+
+always @ (posedge CLK or posedge RST) begin
+  if (RST) begin
+    Q <= 10'd0;
+  end else if (EN) begin
+    if (Q == TERMINAL_COUNT) begin
+      Q <= 10'd0;
+    end else begin
+      Q <= Q + 10'd1;
+    end
+  end else begin
+    Q <= Q;
+  end
+end
+
+assign TC = (Q == TERMINAL_COUNT);
+
+endmodule