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14 changed files with 547 additions and 4 deletions

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@@ -2,12 +2,21 @@ m255
K3 K3
13 13
cModel Technology cModel Technology
<<<<<<< HEAD
Z0 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_3\<5C>bungen\ampel\sim
vampel
Z1 IAVFK:UCi>e]M?9Rf^BY>j0
Z2 VRO2_FXGbKEQ9T<W2M?dVH1
Z3 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_3\<5C>bungen\ampel\sim
Z4 w1708618307
=======
Z0 dC:\Users\Erdem\Desktop\labor_eds\labor_3\<5C>bungen\ampel\sim Z0 dC:\Users\Erdem\Desktop\labor_eds\labor_3\<5C>bungen\ampel\sim
vampel vampel
Z1 IaQGYY?BdBf@agb6lTWYkz3 Z1 IaQGYY?BdBf@agb6lTWYkz3
Z2 VRO2_FXGbKEQ9T<W2M?dVH1 Z2 VRO2_FXGbKEQ9T<W2M?dVH1
Z3 dC:\Users\Erdem\Desktop\labor_eds\labor_3\<5C>bungen\ampel\sim Z3 dC:\Users\Erdem\Desktop\labor_eds\labor_3\<5C>bungen\ampel\sim
Z4 w1708681481 Z4 w1708681481
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
Z5 8../src/ampel.v Z5 8../src/ampel.v
Z6 F../src/ampel.v Z6 F../src/ampel.v
L0 20 L0 20
@@ -16,9 +25,15 @@ r1
31 31
o-O0 o-O0
!i10b 1 !i10b 1
<<<<<<< HEAD
Z8 !s100 S?HeNBV[mV3T>a:hdNfS10
!s85 0
Z9 !s108 1708618418.950000
=======
Z8 !s100 V^If:`L@9b]?^9XGzD5z@3 Z8 !s100 V^If:`L@9b]?^9XGzD5z@3
!s85 0 !s85 0
Z9 !s108 1708681485.221000 Z9 !s108 1708681485.221000
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
Z10 !s107 ../src/ampel.v| Z10 !s107 ../src/ampel.v|
Z11 !s90 -reportprogress|300|../src/ampel.v|+define+SIMULATION| Z11 !s90 -reportprogress|300|../src/ampel.v|+define+SIMULATION|
!s101 -O0 !s101 -O0
@@ -29,7 +44,11 @@ vmod_n_counter_10bit
IlLNUY`h`GTJ1?TjLj1BUS2 IlLNUY`h`GTJ1?TjLj1BUS2
VOCKRzhG[H7hm^_`n>48^e3 VOCKRzhG[H7hm^_`n>48^e3
R3 R3
<<<<<<< HEAD
Z13 w1708542298
=======
Z13 w1708675165 Z13 w1708675165
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
8../src/mod_n_counter_10bit.v 8../src/mod_n_counter_10bit.v
F../src/mod_n_counter_10bit.v F../src/mod_n_counter_10bit.v
L0 1 L0 1
@@ -37,7 +56,11 @@ R7
r1 r1
!s85 0 !s85 0
31 31
<<<<<<< HEAD
!s108 1708618419.009000
=======
!s108 1708681485.276000 !s108 1708681485.276000
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
!s107 ../src/mod_n_counter_10bit.v| !s107 ../src/mod_n_counter_10bit.v|
!s90 -reportprogress|300|../src/mod_n_counter_10bit.v| !s90 -reportprogress|300|../src/mod_n_counter_10bit.v|
!s101 -O0 !s101 -O0
@@ -55,7 +78,11 @@ r1
31 31
o-O0 o-O0
Z18 !s100 1oY2jolgFK??ee;z]EH8c2 Z18 !s100 1oY2jolgFK??ee;z]EH8c2
<<<<<<< HEAD
Z19 !s108 1708618418.897000
=======
Z19 !s108 1708681485.163000 Z19 !s108 1708681485.163000
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
Z20 !s107 tb_ampel.v| Z20 !s107 tb_ampel.v|
Z21 !s90 -reportprogress|300|tb_ampel.v| Z21 !s90 -reportprogress|300|tb_ampel.v|
!i10b 1 !i10b 1

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@@ -52,14 +52,24 @@ wire en_div_1;
wire en_div_2; wire en_div_2;
wire en_div_3; wire en_div_3;
wire [9:0] q_div_1; <<<<<<< HEAD
wire [9:0] q_div_2;
wire [9:0] q_div_3;
wire tc_div_1; wire tc_div_1;
wire tc_div_2; wire tc_div_2;
wire tc_div_3; wire tc_div_3;
=======
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
wire [9:0] q_div_1;
wire [9:0] q_div_2;
wire [9:0] q_div_3;
<<<<<<< HEAD
=======
wire tc_div_1;
wire tc_div_2;
wire tc_div_3;
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
// R Gr // R Gr
parameter FUSS_AUS = 2'b00; parameter FUSS_AUS = 2'b00;
parameter FUSS_ROT = 2'b10; parameter FUSS_ROT = 2'b10;
@@ -99,17 +109,31 @@ assign LEDF_R = FUSSGAENGER;
`define PHASEVAL 8 `define PHASEVAL 8
//clock divider to generate 1 Hz //clock divider to generate 1 Hz
<<<<<<< HEAD
//
=======
//Clock Enable Generation //Clock Enable Generation
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
assign en_div_1 = 1'b1; assign en_div_1 = 1'b1;
assign en_div_2 = tc_div_1; assign en_div_2 = tc_div_1;
assign en_div_3 = tc_div_1 & tc_div_2; assign en_div_3 = tc_div_1 & tc_div_2;
<<<<<<< HEAD
always begin
CLOCK_ENABLE = tc_div_3;
end
// synchronisze KEY to CLOCK_50
always @(posedge CLOCK_50) begin
=======
always @(tc_div_3) begin always @(tc_div_3) begin
CLOCK_ENABLE <= tc_div_3; CLOCK_ENABLE <= tc_div_3;
end end
// synchronisze KEY to CLOCK_50 // synchronisze KEY to CLOCK_50
always @(posedge CLOCK_50 or posedge ~KEY[0]) begin always @(posedge CLOCK_50 or posedge ~KEY[0]) begin
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
MELDER_Q = ~KEY[0]; MELDER_Q = ~KEY[0];
MELDER_QQ = MELDER_Q; MELDER_QQ = MELDER_Q;
end end
@@ -118,6 +142,38 @@ end
// Melder zuruecksetzen wenn die Anforderung von der Statemachine verarbeitet // Melder zuruecksetzen wenn die Anforderung von der Statemachine verarbeitet
// wurde. Die Ampelanlage gibt den FUSSGAENGERn nur dann gruen wenn // wurde. Die Ampelanlage gibt den FUSSGAENGERn nur dann gruen wenn
// ein Melder anstehst... // ein Melder anstehst...
<<<<<<< HEAD
always @(posedge CLOCK_50 or negedge RESET) begin
if (RESET)
MELDER <= 1'b0;
else begin
case ({MELDER_QQ, MELDER_ACK})
2'b01: MELDER <= 1'b0;
2'b10: MELDER <= 1'b1;
2'b11: MELDER <= ~MELDER;
default: ;
endcase
end
end
assign WARTEN_FERTIG = (WARTEZAEHLER == 4'b0000);
//Wartezaehler
always @(posedge CLOCK_50 or RESET) begin
if(RESET) begin
WARTEZAEHLER <= WARTEWERT;
end
else if(CLOCK_ENABLE) begin
if (START_WARTEN)
WARTEZAEHLER <= WARTEWERT;
START_WARTEN <= 1'b0;
if (~WARTEN_FERTIG)
WARTEZAEHLER <= WARTEZAEHLER - 1'b1;
end
end
always @(posedge CLOCK_50 or negedge RESET)
=======
always @(posedge CLOCK_50 or posedge RESET) begin always @(posedge CLOCK_50 or posedge RESET) begin
if (RESET) if (RESET)
MELDER <= 1'b0; MELDER <= 1'b0;
@@ -152,6 +208,7 @@ end
always @(posedge CLOCK_50 or posedge RESET) always @(posedge CLOCK_50 or posedge RESET)
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
if (RESET) if (RESET)
begin begin
HAUPTSTR <= AUTO_GRUEN; HAUPTSTR <= AUTO_GRUEN;
@@ -165,16 +222,29 @@ always @(posedge CLOCK_50 or posedge RESET)
if (CLOCK_ENABLE) if (CLOCK_ENABLE)
case (STATE) case (STATE)
4'd0: begin 4'd0: begin
<<<<<<< HEAD
if(WARTEN_FERTIG) begin
=======
if (~WARTEN_FERTIG) begin if (~WARTEN_FERTIG) begin
START_WARTEN <= 1'b0; START_WARTEN <= 1'b0;
STATE <= 4'd0; STATE <= 4'd0;
end end
else begin else begin
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
HAUPTSTR <= AUTO_GRUEN; HAUPTSTR <= AUTO_GRUEN;
NEBENSTR <= AUTO_ROT; NEBENSTR <= AUTO_ROT;
FUSSGAENGER <= FUSS_ROT; FUSSGAENGER <= FUSS_ROT;
START_WARTEN <= 1'b1; START_WARTEN <= 1'b1;
WARTEWERT <= `HAUPT_GRUEN_DAUER; WARTEWERT <= `HAUPT_GRUEN_DAUER;
<<<<<<< HEAD
end else begin
START_WARTEN <= 1'b0;
end
end
4'd1: begin
if(WARTEN_FERTIG) begin
HAUPTSTR = AUTO_GELB;
=======
STATE <= 4'd1; STATE <= 4'd1;
end end
end end
@@ -186,10 +256,19 @@ always @(posedge CLOCK_50 or posedge RESET)
end end
else begin else begin
HAUPTSTR <= AUTO_GELB; HAUPTSTR <= AUTO_GELB;
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
NEBENSTR <= AUTO_ROT; NEBENSTR <= AUTO_ROT;
FUSSGAENGER <= FUSS_ROT; FUSSGAENGER <= FUSS_ROT;
START_WARTEN <= 1'b1; START_WARTEN <= 1'b1;
WARTEWERT <= `GELB_DAUER; WARTEWERT <= `GELB_DAUER;
<<<<<<< HEAD
end else begin
START_WARTEN <= 1'b0;
end
end
4'd2: begin
if(WARTEN_FERTIG && MELDER) begin
=======
STATE <= 4'd2; STATE <= 4'd2;
end end
@@ -200,20 +279,36 @@ always @(posedge CLOCK_50 or posedge RESET)
STATE <= 4'd2; STATE <= 4'd2;
end end
else if (WARTEN_FERTIG && MELDER) begin else if (WARTEN_FERTIG && MELDER) begin
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
HAUPTSTR <= AUTO_ROT; HAUPTSTR <= AUTO_ROT;
NEBENSTR <= AUTO_ROT; NEBENSTR <= AUTO_ROT;
FUSSGAENGER <= FUSS_ROT; FUSSGAENGER <= FUSS_ROT;
START_WARTEN <= 1'b1; START_WARTEN <= 1'b1;
WARTEWERT <= `FUSS_WARTEN; WARTEWERT <= `FUSS_WARTEN;
<<<<<<< HEAD
MELDER_ACK <= 1'b1;
end else if (WARTEN_FERTIG && ~MELDER) begin
=======
MELDER_ACK <= 1'b1; MELDER_ACK <= 1'b1;
STATE <= 4'd3; STATE <= 4'd3;
end end
else if (WARTEN_FERTIG && ~MELDER) begin else if (WARTEN_FERTIG && ~MELDER) begin
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
HAUPTSTR <= AUTO_ROT; HAUPTSTR <= AUTO_ROT;
NEBENSTR <= AUTO_ROT; NEBENSTR <= AUTO_ROT;
FUSSGAENGER <= FUSS_ROT; FUSSGAENGER <= FUSS_ROT;
START_WARTEN <= 1'b1; START_WARTEN <= 1'b1;
WARTEWERT <= `ALLE_ROT_DAUER; WARTEWERT <= `ALLE_ROT_DAUER;
<<<<<<< HEAD
end else if(~WARTEN_FERTIG) begin
START_WARTEN <= 1'b0;
end
end
4'd3: begin
if(WARTEN_FERTIG) begin
=======
STATE <= 4'd4; STATE <= 4'd4;
end end
@@ -224,12 +319,34 @@ always @(posedge CLOCK_50 or posedge RESET)
STATE <= 4'd3; STATE <= 4'd3;
end end
else begin else begin
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
HAUPTSTR <= AUTO_ROT; HAUPTSTR <= AUTO_ROT;
NEBENSTR <= AUTO_ROT; NEBENSTR <= AUTO_ROT;
FUSSGAENGER <= FUSS_GRUEN; FUSSGAENGER <= FUSS_GRUEN;
START_WARTEN <= 1'b1; START_WARTEN <= 1'b1;
WARTEWERT <= `FUSS_GRUEN_DAUER; WARTEWERT <= `FUSS_GRUEN_DAUER;
MELDER_ACK <= 1'b0; MELDER_ACK <= 1'b0;
<<<<<<< HEAD
end else begin
START_WARTEN <= 1'b0;
end
end
4'd4: begin
if(WARTEN_FERTIG) begin
HAUPTSTR <= AUTO_ROT;
NEBENSTR <= AUTO_GELB|AUTO_ROT;
FUSSGAENGER <= FUSS_ROT;
START_WARTEN <= 1'b1;
WARTEWERT <= `GELB_DAUER;
end else begin
START_WARTEN <= 1'b0;
end
end
4'd5: begin
if(WARTEN_FERTIG) begin
=======
STATE <= 4'd2; STATE <= 4'd2;
end end
end end
@@ -253,11 +370,21 @@ always @(posedge CLOCK_50 or posedge RESET)
STATE <= 4'd5; STATE <= 4'd5;
end end
else begin else begin
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
HAUPTSTR <= AUTO_ROT; HAUPTSTR <= AUTO_ROT;
NEBENSTR <= AUTO_GRUEN; NEBENSTR <= AUTO_GRUEN;
FUSSGAENGER <= FUSS_ROT; FUSSGAENGER <= FUSS_ROT;
START_WARTEN <= 1'b1; START_WARTEN <= 1'b1;
WARTEWERT <= `NEBEN_GRUEN_DAUER; WARTEWERT <= `NEBEN_GRUEN_DAUER;
<<<<<<< HEAD
end else begin
START_WARTEN <= 1'b0;
end
end
4'd6: begin
if(WARTEN_FERTIG) begin
=======
STATE <= 4'd6; STATE <= 4'd6;
end end
end end
@@ -267,11 +394,21 @@ always @(posedge CLOCK_50 or posedge RESET)
STATE <= 4'd6; STATE <= 4'd6;
end end
else begin else begin
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
HAUPTSTR <= AUTO_ROT; HAUPTSTR <= AUTO_ROT;
NEBENSTR <= AUTO_GELB; NEBENSTR <= AUTO_GELB;
FUSSGAENGER <= FUSS_ROT; FUSSGAENGER <= FUSS_ROT;
START_WARTEN <= 1'b1; START_WARTEN <= 1'b1;
WARTEWERT <= `GELB_DAUER; WARTEWERT <= `GELB_DAUER;
<<<<<<< HEAD
end else begin
START_WARTEN <= 1'b0;
end
end
4'd7: begin
if(WARTEN_FERTIG) begin
=======
STATE <= 4'd7; STATE <= 4'd7;
end end
end end
@@ -281,11 +418,22 @@ always @(posedge CLOCK_50 or posedge RESET)
STATE <= 4'd7; STATE <= 4'd7;
end end
else begin else begin
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
HAUPTSTR <= AUTO_ROT; HAUPTSTR <= AUTO_ROT;
NEBENSTR <= AUTO_ROT; NEBENSTR <= AUTO_ROT;
FUSSGAENGER <= FUSS_ROT; FUSSGAENGER <= FUSS_ROT;
START_WARTEN <= 1'b1; START_WARTEN <= 1'b1;
WARTEWERT <= `ALLE_ROT_DAUER; WARTEWERT <= `ALLE_ROT_DAUER;
<<<<<<< HEAD
end else begin
START_WARTEN <= 1'b0;
end
end
4'd8: begin
if(WARTEN_FERTIG) begin
HAUPTSTR <= AUTO_GELB|AUTO_ROT;
=======
STATE <= 4'd8; STATE <= 4'd8;
end end
end end
@@ -296,18 +444,29 @@ always @(posedge CLOCK_50 or posedge RESET)
end end
else begin else begin
HAUPTSTR <= AUTO_GELB | AUTO_ROT; HAUPTSTR <= AUTO_GELB | AUTO_ROT;
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
NEBENSTR <= AUTO_ROT; NEBENSTR <= AUTO_ROT;
FUSSGAENGER <= FUSS_ROT; FUSSGAENGER <= FUSS_ROT;
START_WARTEN <= 1'b1; START_WARTEN <= 1'b1;
WARTEWERT <= `GELB_DAUER; WARTEWERT <= `GELB_DAUER;
<<<<<<< HEAD
end else begin
START_WARTEN <= 1'b0;
=======
STATE <= 4'd0; STATE <= 4'd0;
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
end end
end end
default: default:
STATE <= 4'd1; STATE <= 4'd1;
endcase endcase
<<<<<<< HEAD
mod_n_counter_10bit #(.N(`DIVVAL1)) clock_divider_1(
=======
mod_n_counter_10bit #(.N(`DIVVAL1)) divider_1( mod_n_counter_10bit #(.N(`DIVVAL1)) divider_1(
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
.CLK(CLOCK_50), .CLK(CLOCK_50),
.RST(RESET), .RST(RESET),
.EN(en_div_1), .EN(en_div_1),
@@ -315,7 +474,11 @@ mod_n_counter_10bit #(.N(`DIVVAL1)) divider_1(
.TC(tc_div_1) .TC(tc_div_1)
); );
<<<<<<< HEAD
mod_n_counter_10bit #(.N(`DIVVAL1)) clock_divider_2(
=======
mod_n_counter_10bit #(.N(`DIVVAL1)) divider_2( mod_n_counter_10bit #(.N(`DIVVAL1)) divider_2(
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
.CLK(CLOCK_50), .CLK(CLOCK_50),
.RST(RESET), .RST(RESET),
.EN(en_div_2), .EN(en_div_2),
@@ -323,7 +486,11 @@ mod_n_counter_10bit #(.N(`DIVVAL1)) divider_2(
.TC(tc_div_2) .TC(tc_div_2)
); );
<<<<<<< HEAD
mod_n_counter_10bit #(.N(`DIVVAL3)) clock_divider_3(
=======
mod_n_counter_10bit #(.N(`DIVVAL3)) divider_3( mod_n_counter_10bit #(.N(`DIVVAL3)) divider_3(
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
.CLK(CLOCK_50), .CLK(CLOCK_50),
.RST(RESET), .RST(RESET),
.EN(en_div_3), .EN(en_div_3),
@@ -331,4 +498,8 @@ mod_n_counter_10bit #(.N(`DIVVAL3)) divider_3(
.TC(tc_div_3) .TC(tc_div_3)
); );
<<<<<<< HEAD
endmodule endmodule
=======
endmodule
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45

View File

@@ -0,0 +1,307 @@
/******************************************************
*
* Description: Vorlage Ampelsteurerung
* Date: 05.01.2018
* File Name: ampel_wo_src.v
* Version: 1.2
* Target: Simulation and Synthesis
* Technology:
*
* Rev Author Date Changes
* -----------------------------------------------------
* 1.0 RHK 10.10.2011 Initial Release
* 1.1 JZ 10.03.2016 several bugfixes
* 1.2 JZ 05.01.2018 angepasst auf neues Ampelboard
* 1.3 MW 07.03.2019 STATE Konstanten angepasst
*******************************************************/
`timescale 1ns / 1ps
module ampel (
input CLOCK_50,
input [1:0] KEY,
output [2:0] LEDH_L,
output [2:0] LEDH_R,
output [2:0] LEDN_L,
output [2:0] LEDN_R,
output [1:0] LEDF_L,
output [1:0] LEDF_R,
output reg DBG
);
reg [9:0] CLKDIV1;
reg [9:0] CLKDIV2;
reg [9:0] CLKDIV3;
reg MELDER;
reg MELDER_Q;
reg MELDER_QQ;
reg MELDER_ACK;
reg CLOCK_ENABLE;
reg START_WARTEN;
reg [3:0] STATE;
reg [2:0] HAUPTSTR;
reg [2:0] NEBENSTR;
reg [1:0] FUSSGAENGER;
reg [3:0] WARTEZAEHLER;
reg [3:0] WARTEWERT;
wire en_div_1;
wire en_div_2;
wire en_div_3;
wire tc_div_1;
wire tc_div_2;
wire tc_div_3;
wire [9:0] q_div_1;
wire [9:0] q_div_2;
wire [9:0] q_div_3;
// R Gr
parameter FUSS_AUS = 2'b00;
parameter FUSS_ROT = 2'b10;
parameter FUSS_GRUEN = 2'b01;
// R Ge Gr
parameter AUTO_AUS = 3'b000;
parameter AUTO_ROT = 3'b100;
parameter AUTO_GELB = 3'b010;
parameter AUTO_GRUEN = 3'b001;
assign RESET = ~KEY[1];
assign LEDH_L = HAUPTSTR;
assign LEDH_R = HAUPTSTR;
assign LEDN_L = NEBENSTR;
assign LEDN_R = NEBENSTR;
assign LEDF_L = FUSSGAENGER;
assign LEDF_R = FUSSGAENGER;
`ifdef SIMULATION
`define DIVVAL1 10-1
`define DIVVAL3 5-1
`else
`define DIVVAL1 1000-1
`define DIVVAL3 50-1
`endif
`define FUSS_WARTEN 4 //Wartezeit
`define GELB_DAUER 4 //Wartezeit
`define FUSS_GRUEN_DAUER 4 //Wartezeit
`define ALLE_ROT_DAUER 4 //Wartezeit
`define HAUPT_GRUEN_DAUER 4 //Wartezeit
`define NEBEN_GRUEN_DAUER 4 //Wartezeit
`define PHASEVAL 8
//clock divider to generate 1 Hz
//
assign en_div_1 = 1'b1;
assign en_div_2 = tc_div_1;
assign en_div_3 = tc_div_1 & tc_div_2;
always begin
CLOCK_ENABLE = tc_div_3;
end
// synchronisze KEY to CLOCK_50
always @(posedge CLOCK_50) begin
MELDER_Q = ~KEY[0];
MELDER_QQ = MELDER_Q;
end
// Melder sofort setzen
// Melder zuruecksetzen wenn die Anforderung von der Statemachine verarbeitet
// wurde. Die Ampelanlage gibt den FUSSGAENGERn nur dann gruen wenn
// ein Melder anstehst...
always @(posedge CLOCK_50 or negedge RESET) begin
if (RESET)
MELDER <= 1'b0;
else begin
case ({MELDER_QQ, MELDER_ACK})
2'b01: MELDER <= 1'b0;
2'b10: MELDER <= 1'b1;
2'b11: MELDER <= ~MELDER;
default: ;
endcase
end
end
assign WARTEN_FERTIG = (WARTEZAEHLER == 4'b0000);
//Wartezaehler
always @(posedge CLOCK_50 or RESET) begin
if(RST) begin
WARTEZAEHLER <= WARTEWERT;
end
else if(CLOCK_ENABLE) begin
if (START_WARTEN)
WARTEZAEHLER <= WARTEWERT;
START_WARTEN <= 1'b0;
if (~WARTEN_FERTIG)
WARTEZAEHLER <= WARTEZAEHLER - 1'b1;
end
end
always @(posedge CLOCK_50 or negedge RESET)
if (RESET)
begin
HAUPTSTR <= AUTO_GRUEN;
NEBENSTR <= AUTO_ROT;
FUSSGAENGER <= FUSS_ROT;
START_WARTEN <= 1'b0;
STATE <= 4'd0;
MELDER_ACK <= 1'b0;
end
else
if (CLOCK_ENABLE)
case (STATE)
4'd0: begin
if(WARTEN_FERTIG) begin
HAUPTSTR <= AUTO_GRUEN;
NEBENSTR <= AUTO_ROT;
FUSSGAENGER <= FUSS_ROT;
START_WARTEN <= 1'b1;
WARTEWERT <= HAUPT_GRUEN_DAUER;
end else begin
START_WARTEN <= 1'b0;
end
end
4'd1: begin
if(WARTEN_FERTIG) begin
HAUPTSTR = AUTO_GELB;
NEBENSTR <= AUTO_ROT;
FUSSGAENGER <= FUSS_ROT;
START_WARTEN <= 1'b1;
WARTEWERT <= GELB_DAUER;
end else begin
START_WARTEN <= 1'b0;
end
end
4'd2: begin
if(WARTEN_FERTIG && MELDER) begin
HAUPTSTR <= AUTO_ROT;
NEBENSTR <= AUTO_ROT;
FUSSGAENGER <= FUSS_ROT;
START_WARTEN <= 1'b1;
WARTEWERT <= FUSS_WARTEN;
MELDER_ACK <= 1'b1;
end else if (WARTEN_FERTIG && ~MELDER) begin
HAUPTSTR <= AUTO_ROT;
NEBENSTR <= AUTO_ROT;
FUSSGAENGER <= FUSS_ROT;
START_WARTEN <= 1'b1;
WARTEWERT <= ALLE_ROT_DAUER;
end else if(~WARTEN_FERTIG) begin
START_WARTEN <= 1'b0;
end
end
4'd3: begin
if(WARTEN_FERTIG) begin
HAUPTSTR <= AUTO_ROT;
NEBENSTR <= AUTO_ROT;
FUSSGAENGER <= FUSS_GRUEN;
START_WARTEN <= 1'b1;
WARTEWERT <= FUSS_GRUEN_DAUER;
MELDER_ACK <= 1'b0;
end else begin
START_WARTEN <= 1'b0;
end
end
4'd4: begin
if(WARTEN_FERTIG) begin
HAUPTSTR <= AUTO_ROT;
NEBENSTR <= AUTO_GELB|AUTO_ROT;
FUSSGAENGER <= FUSS_ROT;
START_WARTEN <= 1'b1;
WARTEWERT <= GELB_DAUER;
end else begin
START_WARTEN <= 1'b0;
end
end
4'd5: begin
if(WARTEN_FERTIG) begin
HAUPTSTR <= AUTO_ROT;
NEBENSTR <= AUTO_GRUEN;
FUSSGAENGER <= FUSS_ROT;
START_WARTEN <= 1'b1;
WARTEWERT = NEBEN_GRUEN_DAUER;
end else begin
START_WARTEN <= 1'b0;
end
end
4'd6: begin
if(WARTEN_FERTIG) begin
HAUPTSTR = AUTO_ROT;
NEBENSTR = AUTO_GELB;
FUSSGAENGER = FUSS_ROT;
START_WARTEN = 1'b1;
WARTEWERT = GELB_DAUER;
end else begin
START_WARTEN <= 1'b0;
end
end
4'd7: begin
if(WARTEN_FERTIG) begin
HAUPTSTR = AUTO_ROT;
NEBENSTR = AUTO_ROT;
FUSSGAENGER = FUSS_ROT;
START_WARTEN = 1'b1;
WARTEWERT = ALLE_ROT_DAUER;
end else begin
START_WARTEN <= 1'b0;
end
end
4'd8: begin
if(WARTEN_FERTIG) begin
HAUPTSTR = AUTO_GELB|AUTO_ROT;
NEBENSTR = AUTO_ROT;
FUSSGAENGER = FUSS_ROT;
START_WARTEN = 1'b1;
WARTEWERT = GELB_DAUER;
end else begin
START_WARTEN <= 1'b0;
end
end
default:
STATE <= 4'd1;
endcase
mod_n_counter_10bit #(.N(DIVVAL1)) clock_divider_1(
.CLK(CLOCK_50),
.RST(RESET),
.EN(en_div_1),
.Q(q_div_1),
.TC(tc_div_1)
);
mod_n_counter_10bit #(.N(DIVVAL1)) clock_divider_2(
.CLK(CLOCK_50),
.RST(RESET),
.EN(en_div_2),
.Q(q_div_2),
.TC(tc_div_2)
);
mod_n_counter_10bit #(.N(DIVVAL3)) clock_divider_3(
.CLK(CLOCK_50),
.RST(RESET),
.EN(en_div_3),
.Q(q_div_3),
.TC(tc_div_3)
);
endmodule

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@@ -0,0 +1,38 @@
//Modellierung eines jk-ff
//Autor: M. Erdem
//Mat.-Nr.: 8757524
//Datum: 21.02.2024
module jk_ff (
//Ein- und Ausgänge anlegen
R,
CLK,
EN,
J,
K,
Q
);
input R, CLK, EN, J, K;
output reg Q;
//Verhaltensbeschreibung
always @(R or posedge CLK) begin
//Bei einem Reset soll Q auf 0 gesetzt werden
if(R) begin
Q <= 1'b0;
//Wenn EN = 1 dann soll das Modul aktiv sein
end else if (EN) begin
//Zustände von J und K werden analysiert und entsprechend Q angesteuert.
//Hierbei ist J Bit Nr. 1 und K ist Bit Nr. 0. (Von Rechts nach Links.)
case ({J, K})
2'b01: Q <= 1'b0;
2'b10: Q <= 1'b1;
2'b11: Q <= ~Q;
default: ;
endcase
end
end
endmodule