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5 Commits
59771a4813
...
working
| Author | SHA1 | Date | |
|---|---|---|---|
| 17bebf30d3 | |||
| f65a8de67c | |||
| 1b9840c27c | |||
| 2d7ad7298f | |||
| 3c2c1f9075 |
Binary file not shown.
@@ -21,3 +21,4 @@ vsim -c -t ps tb_ampel
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do wave.do
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run 1500 us
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#run 400 us
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Binary file not shown.
@@ -3,18 +3,52 @@ quietly WaveActivateNextPane {} 0
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add wave -noupdate /tb_ampel/CLK
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add wave -noupdate /tb_ampel/RSTn
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add wave -noupdate /tb_ampel/SW
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add wave -noupdate -expand -subitemconfig {{/tb_ampel/HAUPTSTR_LINKS[2]} {-color Red} {/tb_ampel/HAUPTSTR_LINKS[1]} {-color Gold}} /tb_ampel/HAUPTSTR_LINKS
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add wave -noupdate -expand -subitemconfig {{/tb_ampel/NEBENSTR_LINKS[2]} {-color Red} {/tb_ampel/NEBENSTR_LINKS[1]} {-color Gold}} /tb_ampel/NEBENSTR_LINKS
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add wave -noupdate -expand -subitemconfig {{/tb_ampel/FUSSGAENGER_LINKS[1]} {-color Red}} /tb_ampel/FUSSGAENGER_LINKS
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add wave -noupdate -expand -subitemconfig {{/tb_ampel/HAUPTSTR_RECHTS[2]} {-color Red} {/tb_ampel/HAUPTSTR_RECHTS[1]} {-color Gold}} /tb_ampel/HAUPTSTR_RECHTS
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add wave -noupdate -expand -subitemconfig {{/tb_ampel/NEBENSTR_RECHTS[2]} {-color Red} {/tb_ampel/NEBENSTR_RECHTS[1]} {-color Gold}} /tb_ampel/NEBENSTR_RECHTS
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add wave -noupdate -expand -subitemconfig {{/tb_ampel/FUSSGAENGER_RECHTS[1]} {-color Red}} /tb_ampel/FUSSGAENGER_RECHTS
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add wave -position end sim:/tb_ampel/ampel/CLOCK_ENABLE
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add wave -noupdate -subitemconfig {{/tb_ampel/HAUPTSTR_LINKS[2]} {-color Red -height 15} {/tb_ampel/HAUPTSTR_LINKS[1]} {-color Gold -height 15}} /tb_ampel/HAUPTSTR_LINKS
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add wave -noupdate -subitemconfig {{/tb_ampel/NEBENSTR_LINKS[2]} {-color Red -height 15} {/tb_ampel/NEBENSTR_LINKS[1]} {-color Gold -height 15}} /tb_ampel/NEBENSTR_LINKS
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add wave -noupdate -subitemconfig {{/tb_ampel/FUSSGAENGER_LINKS[1]} {-color Red -height 15}} /tb_ampel/FUSSGAENGER_LINKS
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add wave -noupdate -subitemconfig {{/tb_ampel/HAUPTSTR_RECHTS[2]} {-color Red -height 15} {/tb_ampel/HAUPTSTR_RECHTS[1]} {-color Gold -height 15}} /tb_ampel/HAUPTSTR_RECHTS
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add wave -noupdate -subitemconfig {{/tb_ampel/NEBENSTR_RECHTS[2]} {-color Red -height 15} {/tb_ampel/NEBENSTR_RECHTS[1]} {-color Gold -height 15}} /tb_ampel/NEBENSTR_RECHTS
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add wave -noupdate -subitemconfig {{/tb_ampel/FUSSGAENGER_RECHTS[1]} {-color Red -height 15}} /tb_ampel/FUSSGAENGER_RECHTS
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add wave -noupdate /tb_ampel/ampel/CLOCK_50
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add wave -noupdate /tb_ampel/ampel/KEY
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add wave -noupdate /tb_ampel/ampel/LEDH_L
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add wave -noupdate /tb_ampel/ampel/LEDH_R
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add wave -noupdate /tb_ampel/ampel/LEDN_L
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add wave -noupdate /tb_ampel/ampel/LEDN_R
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add wave -noupdate /tb_ampel/ampel/LEDF_L
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add wave -noupdate /tb_ampel/ampel/LEDF_R
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add wave -noupdate /tb_ampel/ampel/DBG
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add wave -noupdate /tb_ampel/ampel/CLKDIV1
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add wave -noupdate /tb_ampel/ampel/CLKDIV2
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add wave -noupdate /tb_ampel/ampel/CLKDIV3
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add wave -noupdate /tb_ampel/ampel/MELDER
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add wave -noupdate /tb_ampel/ampel/MELDER_Q
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add wave -noupdate /tb_ampel/ampel/MELDER_QQ
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add wave -noupdate /tb_ampel/ampel/MELDER_ACK
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add wave -noupdate /tb_ampel/ampel/CLOCK_ENABLE
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add wave -noupdate /tb_ampel/ampel/START_WARTEN
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add wave -noupdate /tb_ampel/ampel/STATE
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add wave -noupdate /tb_ampel/ampel/HAUPTSTR
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add wave -noupdate /tb_ampel/ampel/NEBENSTR
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add wave -noupdate /tb_ampel/ampel/FUSSGAENGER
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add wave -noupdate /tb_ampel/ampel/WARTEZAEHLER
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add wave -noupdate /tb_ampel/ampel/WARTEWERT
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add wave -noupdate /tb_ampel/ampel/en_div_1
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add wave -noupdate /tb_ampel/ampel/en_div_2
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add wave -noupdate /tb_ampel/ampel/en_div_3
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add wave -noupdate /tb_ampel/ampel/q_div_1
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add wave -noupdate /tb_ampel/ampel/q_div_2
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add wave -noupdate /tb_ampel/ampel/q_div_3
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add wave -noupdate /tb_ampel/ampel/tc_div_1
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add wave -noupdate /tb_ampel/ampel/tc_div_2
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add wave -noupdate /tb_ampel/ampel/tc_div_3
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add wave -noupdate /tb_ampel/ampel/RESET
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add wave -noupdate /tb_ampel/ampel/WARTEN_FERTIG
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {833117378 ps} 0}
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WaveRestoreCursors {{Cursor 1} {157723025 ps} 0}
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quietly wave cursor active 1
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -valuecolwidth 39
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configure wave -justifyvalue left
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configure wave -signalnamewidth 0
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configure wave -snapdistance 10
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@@ -27,4 +61,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {0 ps} {1575 us}
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WaveRestoreZoom {0 ps} {420 us}
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@@ -2,12 +2,21 @@ m255
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K3
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13
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cModel Technology
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<<<<<<< HEAD
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Z0 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_3\<5C>bungen\ampel\sim
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vampel
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Z1 IAVFK:UCi>e]M?9Rf^BY>j0
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Z2 VRO2_FXGbKEQ9T<W2M?dVH1
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Z3 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_3\<5C>bungen\ampel\sim
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Z4 w1708618307
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=======
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Z0 dC:\Users\Erdem\Desktop\labor_eds\labor_3\<5C>bungen\ampel\sim
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vampel
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Z1 IZGe1P?3miOhU2OZfIKL_U2
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Z1 IaQGYY?BdBf@agb6lTWYkz3
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Z2 VRO2_FXGbKEQ9T<W2M?dVH1
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Z3 dC:\Users\Erdem\Desktop\labor_eds\labor_3\<5C>bungen\ampel\sim
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Z4 w1708639470
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Z4 w1708681481
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>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
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Z5 8../src/ampel.v
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Z6 F../src/ampel.v
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L0 20
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@@ -16,9 +25,15 @@ r1
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31
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o-O0
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!i10b 1
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Z8 !s100 0n0`N_LmU0KcJ3PPGdNQ[0
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<<<<<<< HEAD
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Z8 !s100 S?HeNBV[mV3T>a:hdNfS10
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!s85 0
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Z9 !s108 1708639474.702000
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Z9 !s108 1708618418.950000
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=======
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Z8 !s100 V^If:`L@9b]?^9XGzD5z@3
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!s85 0
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Z9 !s108 1708681485.221000
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>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
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Z10 !s107 ../src/ampel.v|
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Z11 !s90 -reportprogress|300|../src/ampel.v|+define+SIMULATION|
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!s101 -O0
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@@ -29,7 +44,11 @@ vmod_n_counter_10bit
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IlLNUY`h`GTJ1?TjLj1BUS2
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VOCKRzhG[H7hm^_`n>48^e3
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R3
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Z13 w1708631937
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<<<<<<< HEAD
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Z13 w1708542298
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=======
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Z13 w1708675165
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>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
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8../src/mod_n_counter_10bit.v
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F../src/mod_n_counter_10bit.v
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L0 1
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@@ -37,7 +56,11 @@ R7
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r1
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!s85 0
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31
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!s108 1708639474.750000
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<<<<<<< HEAD
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!s108 1708618419.009000
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=======
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!s108 1708681485.276000
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>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
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!s107 ../src/mod_n_counter_10bit.v|
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!s90 -reportprogress|300|../src/mod_n_counter_10bit.v|
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!s101 -O0
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@@ -55,7 +78,11 @@ r1
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31
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o-O0
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Z18 !s100 1oY2jolgFK??ee;z]EH8c2
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Z19 !s108 1708639474.609000
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<<<<<<< HEAD
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Z19 !s108 1708618418.897000
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=======
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Z19 !s108 1708681485.163000
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>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
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Z20 !s107 tb_ampel.v|
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Z21 !s90 -reportprogress|300|tb_ampel.v|
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!i10b 1
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@@ -52,14 +52,24 @@ wire en_div_1;
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wire en_div_2;
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wire en_div_3;
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wire [9:0] q_div_1;
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wire [9:0] q_div_2;
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wire [9:0] q_div_3;
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<<<<<<< HEAD
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wire tc_div_1;
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wire tc_div_2;
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wire tc_div_3;
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=======
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>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
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wire [9:0] q_div_1;
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wire [9:0] q_div_2;
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wire [9:0] q_div_3;
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<<<<<<< HEAD
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=======
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wire tc_div_1;
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wire tc_div_2;
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wire tc_div_3;
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>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
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// R Gr
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parameter FUSS_AUS = 2'b00;
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parameter FUSS_ROT = 2'b10;
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@@ -99,18 +109,31 @@ assign LEDF_R = FUSSGAENGER;
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`define PHASEVAL 8
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//clock divider to generate 1 Hz
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<<<<<<< HEAD
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//
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=======
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//Clock Enable Generation
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>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
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assign en_div_1 = 1'b1;
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assign en_div_2 = tc_div_1;
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assign en_div_3 = tc_div_1 & tc_div_2;
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always @(en_div_3) begin
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CLOCK_ENABLE <= en_div_3;
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<<<<<<< HEAD
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always begin
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CLOCK_ENABLE = tc_div_3;
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end
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// synchronisze KEY to CLOCK_50
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always @(posedge CLOCK_50) begin
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=======
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always @(tc_div_3) begin
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CLOCK_ENABLE <= tc_div_3;
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end
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// synchronisze KEY to CLOCK_50
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always @(posedge CLOCK_50 or posedge ~KEY[0]) begin
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>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
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MELDER_Q = ~KEY[0];
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MELDER_QQ = MELDER_Q;
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end
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@@ -119,6 +142,38 @@ end
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// Melder zuruecksetzen wenn die Anforderung von der Statemachine verarbeitet
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// wurde. Die Ampelanlage gibt den FUSSGAENGERn nur dann gruen wenn
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// ein Melder anstehst...
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<<<<<<< HEAD
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always @(posedge CLOCK_50 or negedge RESET) begin
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if (RESET)
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MELDER <= 1'b0;
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else begin
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case ({MELDER_QQ, MELDER_ACK})
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2'b01: MELDER <= 1'b0;
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2'b10: MELDER <= 1'b1;
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2'b11: MELDER <= ~MELDER;
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default: ;
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endcase
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end
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end
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assign WARTEN_FERTIG = (WARTEZAEHLER == 4'b0000);
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//Wartezaehler
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always @(posedge CLOCK_50 or RESET) begin
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if(RESET) begin
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WARTEZAEHLER <= WARTEWERT;
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end
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else if(CLOCK_ENABLE) begin
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if (START_WARTEN)
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WARTEZAEHLER <= WARTEWERT;
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START_WARTEN <= 1'b0;
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if (~WARTEN_FERTIG)
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WARTEZAEHLER <= WARTEZAEHLER - 1'b1;
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end
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end
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always @(posedge CLOCK_50 or negedge RESET)
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=======
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always @(posedge CLOCK_50 or posedge RESET) begin
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if (RESET)
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MELDER <= 1'b0;
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@@ -153,6 +208,7 @@ end
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always @(posedge CLOCK_50 or posedge RESET)
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>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
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if (RESET)
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begin
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HAUPTSTR <= AUTO_GRUEN;
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@@ -166,16 +222,29 @@ always @(posedge CLOCK_50 or posedge RESET)
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if (CLOCK_ENABLE)
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case (STATE)
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4'd0: begin
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<<<<<<< HEAD
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if(WARTEN_FERTIG) begin
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=======
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if (~WARTEN_FERTIG) begin
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START_WARTEN <= 1'b0;
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STATE <= 4'd0;
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end
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else begin
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>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
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HAUPTSTR <= AUTO_GRUEN;
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NEBENSTR <= AUTO_ROT;
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FUSSGAENGER <= FUSS_ROT;
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START_WARTEN <= 1'b1;
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WARTEWERT <= `HAUPT_GRUEN_DAUER;
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<<<<<<< HEAD
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end else begin
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START_WARTEN <= 1'b0;
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end
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end
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4'd1: begin
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if(WARTEN_FERTIG) begin
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HAUPTSTR = AUTO_GELB;
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=======
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STATE <= 4'd1;
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end
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end
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@@ -187,10 +256,19 @@ always @(posedge CLOCK_50 or posedge RESET)
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end
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else begin
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HAUPTSTR <= AUTO_GELB;
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>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
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NEBENSTR <= AUTO_ROT;
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FUSSGAENGER <= FUSS_ROT;
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START_WARTEN <= 1'b1;
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WARTEWERT <= `GELB_DAUER;
|
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<<<<<<< HEAD
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end else begin
|
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START_WARTEN <= 1'b0;
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end
|
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end
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4'd2: begin
|
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if(WARTEN_FERTIG && MELDER) begin
|
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=======
|
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STATE <= 4'd2;
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end
|
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|
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@@ -201,20 +279,36 @@ always @(posedge CLOCK_50 or posedge RESET)
|
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STATE <= 4'd2;
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end
|
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else if (WARTEN_FERTIG && MELDER) begin
|
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>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
|
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HAUPTSTR <= AUTO_ROT;
|
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NEBENSTR <= AUTO_ROT;
|
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FUSSGAENGER <= FUSS_ROT;
|
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START_WARTEN <= 1'b1;
|
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WARTEWERT <= `FUSS_WARTEN;
|
||||
<<<<<<< HEAD
|
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MELDER_ACK <= 1'b1;
|
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|
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end else if (WARTEN_FERTIG && ~MELDER) begin
|
||||
=======
|
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MELDER_ACK <= 1'b1;
|
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STATE <= 4'd3;
|
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end
|
||||
else if (WARTEN_FERTIG && ~MELDER) begin
|
||||
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
|
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HAUPTSTR <= AUTO_ROT;
|
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NEBENSTR <= AUTO_ROT;
|
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FUSSGAENGER <= FUSS_ROT;
|
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START_WARTEN <= 1'b1;
|
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WARTEWERT <= `ALLE_ROT_DAUER;
|
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<<<<<<< HEAD
|
||||
|
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end else if(~WARTEN_FERTIG) begin
|
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START_WARTEN <= 1'b0;
|
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end
|
||||
end
|
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4'd3: begin
|
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if(WARTEN_FERTIG) begin
|
||||
=======
|
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STATE <= 4'd4;
|
||||
end
|
||||
|
||||
@@ -225,12 +319,34 @@ always @(posedge CLOCK_50 or posedge RESET)
|
||||
STATE <= 4'd3;
|
||||
end
|
||||
else begin
|
||||
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
|
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HAUPTSTR <= AUTO_ROT;
|
||||
NEBENSTR <= AUTO_ROT;
|
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FUSSGAENGER <= FUSS_GRUEN;
|
||||
START_WARTEN <= 1'b1;
|
||||
WARTEWERT <= `FUSS_GRUEN_DAUER;
|
||||
MELDER_ACK <= 1'b0;
|
||||
<<<<<<< HEAD
|
||||
|
||||
end else begin
|
||||
START_WARTEN <= 1'b0;
|
||||
end
|
||||
end
|
||||
4'd4: begin
|
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if(WARTEN_FERTIG) begin
|
||||
HAUPTSTR <= AUTO_ROT;
|
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NEBENSTR <= AUTO_GELB|AUTO_ROT;
|
||||
FUSSGAENGER <= FUSS_ROT;
|
||||
START_WARTEN <= 1'b1;
|
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WARTEWERT <= `GELB_DAUER;
|
||||
|
||||
end else begin
|
||||
START_WARTEN <= 1'b0;
|
||||
end
|
||||
end
|
||||
4'd5: begin
|
||||
if(WARTEN_FERTIG) begin
|
||||
=======
|
||||
STATE <= 4'd2;
|
||||
end
|
||||
end
|
||||
@@ -254,11 +370,21 @@ always @(posedge CLOCK_50 or posedge RESET)
|
||||
STATE <= 4'd5;
|
||||
end
|
||||
else begin
|
||||
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
|
||||
HAUPTSTR <= AUTO_ROT;
|
||||
NEBENSTR <= AUTO_GRUEN;
|
||||
FUSSGAENGER <= FUSS_ROT;
|
||||
START_WARTEN <= 1'b1;
|
||||
WARTEWERT <= `NEBEN_GRUEN_DAUER;
|
||||
<<<<<<< HEAD
|
||||
|
||||
end else begin
|
||||
START_WARTEN <= 1'b0;
|
||||
end
|
||||
end
|
||||
4'd6: begin
|
||||
if(WARTEN_FERTIG) begin
|
||||
=======
|
||||
STATE <= 4'd6;
|
||||
end
|
||||
end
|
||||
@@ -268,11 +394,21 @@ always @(posedge CLOCK_50 or posedge RESET)
|
||||
STATE <= 4'd6;
|
||||
end
|
||||
else begin
|
||||
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
|
||||
HAUPTSTR <= AUTO_ROT;
|
||||
NEBENSTR <= AUTO_GELB;
|
||||
FUSSGAENGER <= FUSS_ROT;
|
||||
START_WARTEN <= 1'b1;
|
||||
WARTEWERT <= `GELB_DAUER;
|
||||
<<<<<<< HEAD
|
||||
|
||||
end else begin
|
||||
START_WARTEN <= 1'b0;
|
||||
end
|
||||
end
|
||||
4'd7: begin
|
||||
if(WARTEN_FERTIG) begin
|
||||
=======
|
||||
STATE <= 4'd7;
|
||||
end
|
||||
end
|
||||
@@ -282,11 +418,22 @@ always @(posedge CLOCK_50 or posedge RESET)
|
||||
STATE <= 4'd7;
|
||||
end
|
||||
else begin
|
||||
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
|
||||
HAUPTSTR <= AUTO_ROT;
|
||||
NEBENSTR <= AUTO_ROT;
|
||||
FUSSGAENGER <= FUSS_ROT;
|
||||
START_WARTEN <= 1'b1;
|
||||
WARTEWERT <= `ALLE_ROT_DAUER;
|
||||
<<<<<<< HEAD
|
||||
|
||||
end else begin
|
||||
START_WARTEN <= 1'b0;
|
||||
end
|
||||
end
|
||||
4'd8: begin
|
||||
if(WARTEN_FERTIG) begin
|
||||
HAUPTSTR <= AUTO_GELB|AUTO_ROT;
|
||||
=======
|
||||
STATE <= 4'd8;
|
||||
end
|
||||
end
|
||||
@@ -297,18 +444,29 @@ always @(posedge CLOCK_50 or posedge RESET)
|
||||
end
|
||||
else begin
|
||||
HAUPTSTR <= AUTO_GELB | AUTO_ROT;
|
||||
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
|
||||
NEBENSTR <= AUTO_ROT;
|
||||
FUSSGAENGER <= FUSS_ROT;
|
||||
START_WARTEN <= 1'b1;
|
||||
WARTEWERT <= `GELB_DAUER;
|
||||
<<<<<<< HEAD
|
||||
|
||||
end else begin
|
||||
START_WARTEN <= 1'b0;
|
||||
=======
|
||||
STATE <= 4'd0;
|
||||
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
|
||||
end
|
||||
end
|
||||
default:
|
||||
STATE <= 4'd1;
|
||||
endcase
|
||||
|
||||
<<<<<<< HEAD
|
||||
mod_n_counter_10bit #(.N(`DIVVAL1)) clock_divider_1(
|
||||
=======
|
||||
mod_n_counter_10bit #(.N(`DIVVAL1)) divider_1(
|
||||
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
|
||||
.CLK(CLOCK_50),
|
||||
.RST(RESET),
|
||||
.EN(en_div_1),
|
||||
@@ -316,7 +474,11 @@ mod_n_counter_10bit #(.N(`DIVVAL1)) divider_1(
|
||||
.TC(tc_div_1)
|
||||
);
|
||||
|
||||
<<<<<<< HEAD
|
||||
mod_n_counter_10bit #(.N(`DIVVAL1)) clock_divider_2(
|
||||
=======
|
||||
mod_n_counter_10bit #(.N(`DIVVAL1)) divider_2(
|
||||
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
|
||||
.CLK(CLOCK_50),
|
||||
.RST(RESET),
|
||||
.EN(en_div_2),
|
||||
@@ -324,7 +486,11 @@ mod_n_counter_10bit #(.N(`DIVVAL1)) divider_2(
|
||||
.TC(tc_div_2)
|
||||
);
|
||||
|
||||
<<<<<<< HEAD
|
||||
mod_n_counter_10bit #(.N(`DIVVAL3)) clock_divider_3(
|
||||
=======
|
||||
mod_n_counter_10bit #(.N(`DIVVAL3)) divider_3(
|
||||
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
|
||||
.CLK(CLOCK_50),
|
||||
.RST(RESET),
|
||||
.EN(en_div_3),
|
||||
@@ -332,4 +498,8 @@ mod_n_counter_10bit #(.N(`DIVVAL3)) divider_3(
|
||||
.TC(tc_div_3)
|
||||
);
|
||||
|
||||
<<<<<<< HEAD
|
||||
endmodule
|
||||
=======
|
||||
endmodule
|
||||
>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
|
||||
|
||||
307
labor_3/Übungen/ampel/src/ampel.v.bak
Normal file
307
labor_3/Übungen/ampel/src/ampel.v.bak
Normal file
@@ -0,0 +1,307 @@
|
||||
/******************************************************
|
||||
*
|
||||
* Description: Vorlage Ampelsteurerung
|
||||
* Date: 05.01.2018
|
||||
* File Name: ampel_wo_src.v
|
||||
* Version: 1.2
|
||||
* Target: Simulation and Synthesis
|
||||
* Technology:
|
||||
*
|
||||
* Rev Author Date Changes
|
||||
* -----------------------------------------------------
|
||||
* 1.0 RHK 10.10.2011 Initial Release
|
||||
* 1.1 JZ 10.03.2016 several bugfixes
|
||||
* 1.2 JZ 05.01.2018 angepasst auf neues Ampelboard
|
||||
* 1.3 MW 07.03.2019 STATE Konstanten angepasst
|
||||
*******************************************************/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module ampel (
|
||||
input CLOCK_50,
|
||||
input [1:0] KEY,
|
||||
output [2:0] LEDH_L,
|
||||
output [2:0] LEDH_R,
|
||||
output [2:0] LEDN_L,
|
||||
output [2:0] LEDN_R,
|
||||
output [1:0] LEDF_L,
|
||||
output [1:0] LEDF_R,
|
||||
output reg DBG
|
||||
);
|
||||
|
||||
reg [9:0] CLKDIV1;
|
||||
reg [9:0] CLKDIV2;
|
||||
reg [9:0] CLKDIV3;
|
||||
|
||||
reg MELDER;
|
||||
reg MELDER_Q;
|
||||
reg MELDER_QQ;
|
||||
reg MELDER_ACK;
|
||||
reg CLOCK_ENABLE;
|
||||
|
||||
reg START_WARTEN;
|
||||
reg [3:0] STATE;
|
||||
reg [2:0] HAUPTSTR;
|
||||
reg [2:0] NEBENSTR;
|
||||
reg [1:0] FUSSGAENGER;
|
||||
|
||||
reg [3:0] WARTEZAEHLER;
|
||||
reg [3:0] WARTEWERT;
|
||||
|
||||
wire en_div_1;
|
||||
wire en_div_2;
|
||||
wire en_div_3;
|
||||
|
||||
wire tc_div_1;
|
||||
wire tc_div_2;
|
||||
wire tc_div_3;
|
||||
|
||||
wire [9:0] q_div_1;
|
||||
wire [9:0] q_div_2;
|
||||
wire [9:0] q_div_3;
|
||||
|
||||
// R Gr
|
||||
parameter FUSS_AUS = 2'b00;
|
||||
parameter FUSS_ROT = 2'b10;
|
||||
parameter FUSS_GRUEN = 2'b01;
|
||||
// R Ge Gr
|
||||
parameter AUTO_AUS = 3'b000;
|
||||
parameter AUTO_ROT = 3'b100;
|
||||
parameter AUTO_GELB = 3'b010;
|
||||
parameter AUTO_GRUEN = 3'b001;
|
||||
|
||||
assign RESET = ~KEY[1];
|
||||
|
||||
assign LEDH_L = HAUPTSTR;
|
||||
assign LEDH_R = HAUPTSTR;
|
||||
assign LEDN_L = NEBENSTR;
|
||||
assign LEDN_R = NEBENSTR;
|
||||
assign LEDF_L = FUSSGAENGER;
|
||||
assign LEDF_R = FUSSGAENGER;
|
||||
|
||||
`ifdef SIMULATION
|
||||
`define DIVVAL1 10-1
|
||||
`define DIVVAL3 5-1
|
||||
`else
|
||||
`define DIVVAL1 1000-1
|
||||
`define DIVVAL3 50-1
|
||||
`endif
|
||||
|
||||
`define FUSS_WARTEN 4 //Wartezeit
|
||||
`define GELB_DAUER 4 //Wartezeit
|
||||
`define FUSS_GRUEN_DAUER 4 //Wartezeit
|
||||
`define ALLE_ROT_DAUER 4 //Wartezeit
|
||||
|
||||
`define HAUPT_GRUEN_DAUER 4 //Wartezeit
|
||||
`define NEBEN_GRUEN_DAUER 4 //Wartezeit
|
||||
|
||||
|
||||
`define PHASEVAL 8
|
||||
|
||||
//clock divider to generate 1 Hz
|
||||
//
|
||||
|
||||
assign en_div_1 = 1'b1;
|
||||
assign en_div_2 = tc_div_1;
|
||||
assign en_div_3 = tc_div_1 & tc_div_2;
|
||||
|
||||
always begin
|
||||
CLOCK_ENABLE = tc_div_3;
|
||||
end
|
||||
|
||||
// synchronisze KEY to CLOCK_50
|
||||
always @(posedge CLOCK_50) begin
|
||||
MELDER_Q = ~KEY[0];
|
||||
MELDER_QQ = MELDER_Q;
|
||||
end
|
||||
|
||||
// Melder sofort setzen
|
||||
// Melder zuruecksetzen wenn die Anforderung von der Statemachine verarbeitet
|
||||
// wurde. Die Ampelanlage gibt den FUSSGAENGERn nur dann gruen wenn
|
||||
// ein Melder anstehst...
|
||||
always @(posedge CLOCK_50 or negedge RESET) begin
|
||||
if (RESET)
|
||||
MELDER <= 1'b0;
|
||||
else begin
|
||||
case ({MELDER_QQ, MELDER_ACK})
|
||||
2'b01: MELDER <= 1'b0;
|
||||
2'b10: MELDER <= 1'b1;
|
||||
2'b11: MELDER <= ~MELDER;
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
assign WARTEN_FERTIG = (WARTEZAEHLER == 4'b0000);
|
||||
|
||||
//Wartezaehler
|
||||
always @(posedge CLOCK_50 or RESET) begin
|
||||
if(RST) begin
|
||||
WARTEZAEHLER <= WARTEWERT;
|
||||
end
|
||||
else if(CLOCK_ENABLE) begin
|
||||
if (START_WARTEN)
|
||||
WARTEZAEHLER <= WARTEWERT;
|
||||
START_WARTEN <= 1'b0;
|
||||
if (~WARTEN_FERTIG)
|
||||
WARTEZAEHLER <= WARTEZAEHLER - 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLOCK_50 or negedge RESET)
|
||||
if (RESET)
|
||||
begin
|
||||
HAUPTSTR <= AUTO_GRUEN;
|
||||
NEBENSTR <= AUTO_ROT;
|
||||
FUSSGAENGER <= FUSS_ROT;
|
||||
START_WARTEN <= 1'b0;
|
||||
STATE <= 4'd0;
|
||||
MELDER_ACK <= 1'b0;
|
||||
end
|
||||
else
|
||||
if (CLOCK_ENABLE)
|
||||
case (STATE)
|
||||
4'd0: begin
|
||||
if(WARTEN_FERTIG) begin
|
||||
HAUPTSTR <= AUTO_GRUEN;
|
||||
NEBENSTR <= AUTO_ROT;
|
||||
FUSSGAENGER <= FUSS_ROT;
|
||||
START_WARTEN <= 1'b1;
|
||||
WARTEWERT <= HAUPT_GRUEN_DAUER;
|
||||
end else begin
|
||||
START_WARTEN <= 1'b0;
|
||||
end
|
||||
end
|
||||
4'd1: begin
|
||||
if(WARTEN_FERTIG) begin
|
||||
HAUPTSTR = AUTO_GELB;
|
||||
NEBENSTR <= AUTO_ROT;
|
||||
FUSSGAENGER <= FUSS_ROT;
|
||||
START_WARTEN <= 1'b1;
|
||||
WARTEWERT <= GELB_DAUER;
|
||||
end else begin
|
||||
START_WARTEN <= 1'b0;
|
||||
end
|
||||
end
|
||||
4'd2: begin
|
||||
if(WARTEN_FERTIG && MELDER) begin
|
||||
HAUPTSTR <= AUTO_ROT;
|
||||
NEBENSTR <= AUTO_ROT;
|
||||
FUSSGAENGER <= FUSS_ROT;
|
||||
START_WARTEN <= 1'b1;
|
||||
WARTEWERT <= FUSS_WARTEN;
|
||||
MELDER_ACK <= 1'b1;
|
||||
|
||||
end else if (WARTEN_FERTIG && ~MELDER) begin
|
||||
HAUPTSTR <= AUTO_ROT;
|
||||
NEBENSTR <= AUTO_ROT;
|
||||
FUSSGAENGER <= FUSS_ROT;
|
||||
START_WARTEN <= 1'b1;
|
||||
WARTEWERT <= ALLE_ROT_DAUER;
|
||||
|
||||
end else if(~WARTEN_FERTIG) begin
|
||||
START_WARTEN <= 1'b0;
|
||||
end
|
||||
end
|
||||
4'd3: begin
|
||||
if(WARTEN_FERTIG) begin
|
||||
HAUPTSTR <= AUTO_ROT;
|
||||
NEBENSTR <= AUTO_ROT;
|
||||
FUSSGAENGER <= FUSS_GRUEN;
|
||||
START_WARTEN <= 1'b1;
|
||||
WARTEWERT <= FUSS_GRUEN_DAUER;
|
||||
MELDER_ACK <= 1'b0;
|
||||
|
||||
end else begin
|
||||
START_WARTEN <= 1'b0;
|
||||
end
|
||||
end
|
||||
4'd4: begin
|
||||
if(WARTEN_FERTIG) begin
|
||||
HAUPTSTR <= AUTO_ROT;
|
||||
NEBENSTR <= AUTO_GELB|AUTO_ROT;
|
||||
FUSSGAENGER <= FUSS_ROT;
|
||||
START_WARTEN <= 1'b1;
|
||||
WARTEWERT <= GELB_DAUER;
|
||||
|
||||
end else begin
|
||||
START_WARTEN <= 1'b0;
|
||||
end
|
||||
end
|
||||
4'd5: begin
|
||||
if(WARTEN_FERTIG) begin
|
||||
HAUPTSTR <= AUTO_ROT;
|
||||
NEBENSTR <= AUTO_GRUEN;
|
||||
FUSSGAENGER <= FUSS_ROT;
|
||||
START_WARTEN <= 1'b1;
|
||||
WARTEWERT = NEBEN_GRUEN_DAUER;
|
||||
|
||||
end else begin
|
||||
START_WARTEN <= 1'b0;
|
||||
end
|
||||
end
|
||||
4'd6: begin
|
||||
if(WARTEN_FERTIG) begin
|
||||
HAUPTSTR = AUTO_ROT;
|
||||
NEBENSTR = AUTO_GELB;
|
||||
FUSSGAENGER = FUSS_ROT;
|
||||
START_WARTEN = 1'b1;
|
||||
WARTEWERT = GELB_DAUER;
|
||||
|
||||
end else begin
|
||||
START_WARTEN <= 1'b0;
|
||||
end
|
||||
end
|
||||
4'd7: begin
|
||||
if(WARTEN_FERTIG) begin
|
||||
HAUPTSTR = AUTO_ROT;
|
||||
NEBENSTR = AUTO_ROT;
|
||||
FUSSGAENGER = FUSS_ROT;
|
||||
START_WARTEN = 1'b1;
|
||||
WARTEWERT = ALLE_ROT_DAUER;
|
||||
|
||||
end else begin
|
||||
START_WARTEN <= 1'b0;
|
||||
end
|
||||
end
|
||||
4'd8: begin
|
||||
if(WARTEN_FERTIG) begin
|
||||
HAUPTSTR = AUTO_GELB|AUTO_ROT;
|
||||
NEBENSTR = AUTO_ROT;
|
||||
FUSSGAENGER = FUSS_ROT;
|
||||
START_WARTEN = 1'b1;
|
||||
WARTEWERT = GELB_DAUER;
|
||||
|
||||
end else begin
|
||||
START_WARTEN <= 1'b0;
|
||||
end
|
||||
end
|
||||
default:
|
||||
STATE <= 4'd1;
|
||||
endcase
|
||||
|
||||
mod_n_counter_10bit #(.N(DIVVAL1)) clock_divider_1(
|
||||
.CLK(CLOCK_50),
|
||||
.RST(RESET),
|
||||
.EN(en_div_1),
|
||||
.Q(q_div_1),
|
||||
.TC(tc_div_1)
|
||||
);
|
||||
|
||||
mod_n_counter_10bit #(.N(DIVVAL1)) clock_divider_2(
|
||||
.CLK(CLOCK_50),
|
||||
.RST(RESET),
|
||||
.EN(en_div_2),
|
||||
.Q(q_div_2),
|
||||
.TC(tc_div_2)
|
||||
);
|
||||
|
||||
mod_n_counter_10bit #(.N(DIVVAL3)) clock_divider_3(
|
||||
.CLK(CLOCK_50),
|
||||
.RST(RESET),
|
||||
.EN(en_div_3),
|
||||
.Q(q_div_3),
|
||||
.TC(tc_div_3)
|
||||
);
|
||||
|
||||
endmodule
|
||||
38
labor_3/Übungen/ampel/src/jk_ff.v
Normal file
38
labor_3/Übungen/ampel/src/jk_ff.v
Normal file
@@ -0,0 +1,38 @@
|
||||
//Modellierung eines jk-ff
|
||||
//Autor: M. Erdem
|
||||
//Mat.-Nr.: 8757524
|
||||
//Datum: 21.02.2024
|
||||
|
||||
module jk_ff (
|
||||
//Ein- und Ausgänge anlegen
|
||||
R,
|
||||
CLK,
|
||||
EN,
|
||||
J,
|
||||
K,
|
||||
Q
|
||||
);
|
||||
input R, CLK, EN, J, K;
|
||||
output reg Q;
|
||||
|
||||
//Verhaltensbeschreibung
|
||||
always @(R or posedge CLK) begin
|
||||
|
||||
//Bei einem Reset soll Q auf 0 gesetzt werden
|
||||
if(R) begin
|
||||
Q <= 1'b0;
|
||||
|
||||
//Wenn EN = 1 dann soll das Modul aktiv sein
|
||||
end else if (EN) begin
|
||||
|
||||
//Zustände von J und K werden analysiert und entsprechend Q angesteuert.
|
||||
//Hierbei ist J Bit Nr. 1 und K ist Bit Nr. 0. (Von Rechts nach Links.)
|
||||
case ({J, K})
|
||||
2'b01: Q <= 1'b0;
|
||||
2'b10: Q <= 1'b1;
|
||||
2'b11: Q <= ~Q;
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
Reference in New Issue
Block a user