Merge branch 'working' of https://gitea.msb24.duckdns.org/musabe24/labor_eds into working

Der Zustandsdiagramm zu der Ampelanlage wurde anhand der falschen Simulation beschrieben.

labor_3/res/ampel/sim __quartus13.1__/work/_info

@@ -17,7 +17,7 @@ OV;L;10.1d;51
 r1
 !s85 0
 31
-!s108 1708549845.999000
+!s108 1708601791.092000
 !s107 tb_ampel.v|
 !s90 -reportprogress|300|tb_ampel.v|
 !s101 -O0

labor_3/res/ampel/sim/modelsim.ini

@@ -17,6 +17,7 @@ others = $MODEL_TECH/../modelsim.ini
 ; Verilog Section
 ;
 
+ampel = designlib/ampel
 work = work
 [vcom]
 ; VHDL93 variable selects language version as the default. 

labor_3/res/ampel/sim/wave.do

@@ -1,12 +1,14 @@
 onerror {resume}
 quietly WaveActivateNextPane {} 0
-add wave -noupdate /sclk_gen_tb/ENA
+add wave -noupdate /tb_ampel/CLK
-add wave -noupdate /sclk_gen_tb/SYNC
+add wave -noupdate /tb_ampel/RSTn
-add wave -noupdate /sclk_gen_tb/RESETn
+add wave -noupdate /tb_ampel/SW
-add wave -noupdate /sclk_gen_tb/CPHA
+add wave -noupdate /tb_ampel/HAUPTSTR_LINKS
-add wave -noupdate /sclk_gen_tb/CLK
+add wave -noupdate /tb_ampel/NEBENSTR_LINKS
-add wave -noupdate /sclk_gen_tb/CPOL
+add wave -noupdate /tb_ampel/FUSSGAENGER_LINKS
-add wave -noupdate /sclk_gen_tb/SCLK
+add wave -noupdate /tb_ampel/HAUPTSTR_RECHTS
+add wave -noupdate /tb_ampel/NEBENSTR_RECHTS
+add wave -noupdate /tb_ampel/FUSSGAENGER_RECHTS
 TreeUpdate [SetDefaultTree]
 WaveRestoreCursors {{Cursor 1} {0 ps} 0}
 quietly wave cursor active 0
@@ -19,9 +21,9 @@ configure wave -datasetprefix 0
 configure wave -rowmargin 4
 configure wave -childrowmargin 2
 configure wave -gridoffset 0
-configure wave -gridperiod 1
+configure wave -gridperiod 5000
 configure wave -griddelta 40
 configure wave -timeline 0
-configure wave -timelineunits ps
+configure wave -timelineunits ns
 update
-WaveRestoreZoom {0 ps} {420 ns}
+WaveRestoreZoom {0 ps} {1 ns}

labor_3/res/ampel/sim/work/_info

@@ -0,0 +1,24 @@
+m255
+K3
+13
+cModel Technology
+Z0 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_3\res\ampel\sim
+vtb_ampel
+!i10b 1
+!s100 1oY2jolgFK??ee;z]EH8c2
+I:0IMZj9F7dM=NBGQ@:fYS0
+V6nf?5m:3VQD@E=_a?l5VH1
+Z1 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_3\res\ampel\sim
+w1708542298
+8tb_ampel.v
+Ftb_ampel.v
+L0 17
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1708602285.106000
+!s107 tb_ampel.v|
+!s90 -reportprogress|300|tb_ampel.v|
+!s101 -O0
+o-O0

labor_3/res/ampel/sim/work/tb_ampel/_primary.vhd

@@ -1,4 +1,4 @@
 library verilog;
 use verilog.vl_types.all;
-entity sclk_gen_tb is
+entity tb_ampel is
-end sclk_gen_tb;
+end tb_ampel;

labor_3/Übungen/ampel/sim/sim.tcl

@@ -0,0 +1,24 @@
+#JZ 2020
+
+#remove working directory
+file delete -force work
+
+#Creating the work lib
+vlib work
+#vmap ampel "designlib/ampel"
+vmap work work
+
+#Top level testbench
+vlog tb_ampel.v
+vlog ../src/ampel.v +define+SIMULATION
+vlog ../src/mod_n_counter_10bit.v
+
+#Simulate
+#vsim -c -t ps -L ampel tb_ampel
+vsim -c -t ps tb_ampel
+
+#get wave
+do wave.do
+
+run 1500 us
+#run 400 us

labor_3/Übungen/ampel/sim/tb_ampel.v

@@ -0,0 +1,67 @@
+/******************************************************
+*                                                     
+*  Description:  tb_ampel                                
+*         Date:  13.01.2018                           
+*    File Name:  tb_ampel.v                              
+*      Version:  1.0                                  
+*       Target:  Simulation             
+*   Technology:                                       
+*                                                     
+* Rev   Author   Date          Changes                
+* -----------------------------------------------------        
+* 1.0   JZ       13.01.2018    Testbench zur Ampelsteuerung
+*******************************************************/
+
+`timescale 1ns / 1ps
+
+module tb_ampel;
+
+reg CLK;
+reg RSTn;
+reg SW;
+
+wire [2:0] HAUPTSTR_LINKS;
+wire [2:0] NEBENSTR_LINKS;
+wire [1:0] FUSSGAENGER_LINKS;
+wire [2:0] HAUPTSTR_RECHTS;
+wire [2:0] NEBENSTR_RECHTS;
+wire [1:0] FUSSGAENGER_RECHTS;
+
+//50 MHz clock
+initial
+  begin
+  CLK  = 1'b0;
+  end
+
+always
+  CLK = #10 ~CLK;
+
+//push buttons
+initial
+  begin
+  RSTn = 1'b1;
+  SW = 1'b1;
+  #100;
+  RSTn = 1'b0;
+  #10;
+  RSTn = 1'b1;
+  #50_000;
+  SW = 1'b0;
+  #100;
+  SW = 1'b1;
+  end
+
+ampel ampel(
+.CLOCK_50 (CLK),
+.KEY ({RSTn, SW}),
+.LEDH_L(HAUPTSTR_LINKS),
+.LEDN_L(NEBENSTR_LINKS),
+.LEDF_L(FUSSGAENGER_LINKS),
+.LEDH_R(HAUPTSTR_RECHTS),
+.LEDN_R(NEBENSTR_RECHTS),
+.LEDF_R(FUSSGAENGER_RECHTS)
+);
+
+
+
+endmodule

labor_3/Übungen/ampel/sim/wave.do

@@ -0,0 +1,64 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /tb_ampel/CLK
+add wave -noupdate /tb_ampel/RSTn
+add wave -noupdate /tb_ampel/SW
+add wave -noupdate -subitemconfig {{/tb_ampel/HAUPTSTR_LINKS[2]} {-color Red -height 15} {/tb_ampel/HAUPTSTR_LINKS[1]} {-color Gold -height 15}} /tb_ampel/HAUPTSTR_LINKS
+add wave -noupdate -subitemconfig {{/tb_ampel/NEBENSTR_LINKS[2]} {-color Red -height 15} {/tb_ampel/NEBENSTR_LINKS[1]} {-color Gold -height 15}} /tb_ampel/NEBENSTR_LINKS
+add wave -noupdate -subitemconfig {{/tb_ampel/FUSSGAENGER_LINKS[1]} {-color Red -height 15}} /tb_ampel/FUSSGAENGER_LINKS
+add wave -noupdate -subitemconfig {{/tb_ampel/HAUPTSTR_RECHTS[2]} {-color Red -height 15} {/tb_ampel/HAUPTSTR_RECHTS[1]} {-color Gold -height 15}} /tb_ampel/HAUPTSTR_RECHTS
+add wave -noupdate -subitemconfig {{/tb_ampel/NEBENSTR_RECHTS[2]} {-color Red -height 15} {/tb_ampel/NEBENSTR_RECHTS[1]} {-color Gold -height 15}} /tb_ampel/NEBENSTR_RECHTS
+add wave -noupdate -subitemconfig {{/tb_ampel/FUSSGAENGER_RECHTS[1]} {-color Red -height 15}} /tb_ampel/FUSSGAENGER_RECHTS
+add wave -noupdate /tb_ampel/ampel/CLOCK_50
+add wave -noupdate /tb_ampel/ampel/KEY
+add wave -noupdate /tb_ampel/ampel/LEDH_L
+add wave -noupdate /tb_ampel/ampel/LEDH_R
+add wave -noupdate /tb_ampel/ampel/LEDN_L
+add wave -noupdate /tb_ampel/ampel/LEDN_R
+add wave -noupdate /tb_ampel/ampel/LEDF_L
+add wave -noupdate /tb_ampel/ampel/LEDF_R
+add wave -noupdate /tb_ampel/ampel/DBG
+add wave -noupdate /tb_ampel/ampel/CLKDIV1
+add wave -noupdate /tb_ampel/ampel/CLKDIV2
+add wave -noupdate /tb_ampel/ampel/CLKDIV3
+add wave -noupdate /tb_ampel/ampel/MELDER
+add wave -noupdate /tb_ampel/ampel/MELDER_Q
+add wave -noupdate /tb_ampel/ampel/MELDER_QQ
+add wave -noupdate /tb_ampel/ampel/MELDER_ACK
+add wave -noupdate /tb_ampel/ampel/CLOCK_ENABLE
+add wave -noupdate /tb_ampel/ampel/START_WARTEN
+add wave -noupdate /tb_ampel/ampel/STATE
+add wave -noupdate /tb_ampel/ampel/HAUPTSTR
+add wave -noupdate /tb_ampel/ampel/NEBENSTR
+add wave -noupdate /tb_ampel/ampel/FUSSGAENGER
+add wave -noupdate /tb_ampel/ampel/WARTEZAEHLER
+add wave -noupdate /tb_ampel/ampel/WARTEWERT
+add wave -noupdate /tb_ampel/ampel/en_div_1
+add wave -noupdate /tb_ampel/ampel/en_div_2
+add wave -noupdate /tb_ampel/ampel/en_div_3
+add wave -noupdate /tb_ampel/ampel/q_div_1
+add wave -noupdate /tb_ampel/ampel/q_div_2
+add wave -noupdate /tb_ampel/ampel/q_div_3
+add wave -noupdate /tb_ampel/ampel/tc_div_1
+add wave -noupdate /tb_ampel/ampel/tc_div_2
+add wave -noupdate /tb_ampel/ampel/tc_div_3
+add wave -noupdate /tb_ampel/ampel/RESET
+add wave -noupdate /tb_ampel/ampel/WARTEN_FERTIG
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {157723025 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 39
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 5000
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {420 us}

labor_3/Übungen/ampel/sim/work/_info

@@ -0,0 +1,90 @@
+m255
+K3
+13
+cModel Technology
+<<<<<<< HEAD
+Z0 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_3\Übungen\ampel\sim
+vampel
+Z1 IAVFK:UCi>e]M?9Rf^BY>j0
+Z2 VRO2_FXGbKEQ9T<W2M?dVH1
+Z3 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_3\Übungen\ampel\sim
+Z4 w1708618307
+=======
+Z0 dC:\Users\Erdem\Desktop\labor_eds\labor_3\Übungen\ampel\sim
+vampel
+Z1 IaQGYY?BdBf@agb6lTWYkz3
+Z2 VRO2_FXGbKEQ9T<W2M?dVH1
+Z3 dC:\Users\Erdem\Desktop\labor_eds\labor_3\Übungen\ampel\sim
+Z4 w1708681481
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+Z5 8../src/ampel.v
+Z6 F../src/ampel.v
+L0 20
+Z7 OV;L;10.1d;51
+r1
+31
+o-O0
+!i10b 1
+<<<<<<< HEAD
+Z8 !s100 S?HeNBV[mV3T>a:hdNfS10
+!s85 0
+Z9 !s108 1708618418.950000
+=======
+Z8 !s100 V^If:`L@9b]?^9XGzD5z@3
+!s85 0
+Z9 !s108 1708681485.221000
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+Z10 !s107 ../src/ampel.v|
+Z11 !s90 -reportprogress|300|../src/ampel.v|+define+SIMULATION|
+!s101 -O0
+Z12 !s92 +define+SIMULATION -O0
+vmod_n_counter_10bit
+!i10b 1
+!s100 9e`GV_]:ML:l92jkefb>Q0
+IlLNUY`h`GTJ1?TjLj1BUS2
+VOCKRzhG[H7hm^_`n>48^e3
+R3
+<<<<<<< HEAD
+Z13 w1708542298
+=======
+Z13 w1708675165
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+8../src/mod_n_counter_10bit.v
+F../src/mod_n_counter_10bit.v
+L0 1
+R7
+r1
+!s85 0
+31
+<<<<<<< HEAD
+!s108 1708618419.009000
+=======
+!s108 1708681485.276000
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+!s107 ../src/mod_n_counter_10bit.v|
+!s90 -reportprogress|300|../src/mod_n_counter_10bit.v|
+!s101 -O0
+o-O0
+vtb_ampel
+Z14 I:0IMZj9F7dM=NBGQ@:fYS0
+Z15 V6nf?5m:3VQD@E=_a?l5VH1
+R3
+R13
+Z16 8tb_ampel.v
+Z17 Ftb_ampel.v
+L0 17
+R7
+r1
+31
+o-O0
+Z18 !s100 1oY2jolgFK??ee;z]EH8c2
+<<<<<<< HEAD
+Z19 !s108 1708618418.897000
+=======
+Z19 !s108 1708681485.163000
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+Z20 !s107 tb_ampel.v|
+Z21 !s90 -reportprogress|300|tb_ampel.v|
+!i10b 1
+!s85 0
+!s101 -O0

labor_3/Übungen/ampel/sim/work/ampel/_primary.vhd

@@ -0,0 +1,32 @@
+library verilog;
+use verilog.vl_types.all;
+entity ampel is
+    generic(
+        FUSS_AUS        : vl_logic_vector(0 to 1) := (Hi0, Hi0);
+        FUSS_ROT        : vl_logic_vector(0 to 1) := (Hi1, Hi0);
+        FUSS_GRUEN      : vl_logic_vector(0 to 1) := (Hi0, Hi1);
+        AUTO_AUS        : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi0);
+        AUTO_ROT        : vl_logic_vector(0 to 2) := (Hi1, Hi0, Hi0);
+        AUTO_GELB       : vl_logic_vector(0 to 2) := (Hi0, Hi1, Hi0);
+        AUTO_GRUEN      : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi1)
+    );
+    port(
+        CLOCK_50        : in     vl_logic;
+        KEY             : in     vl_logic_vector(1 downto 0);
+        LEDH_L          : out    vl_logic_vector(2 downto 0);
+        LEDH_R          : out    vl_logic_vector(2 downto 0);
+        LEDN_L          : out    vl_logic_vector(2 downto 0);
+        LEDN_R          : out    vl_logic_vector(2 downto 0);
+        LEDF_L          : out    vl_logic_vector(1 downto 0);
+        LEDF_R          : out    vl_logic_vector(1 downto 0);
+        DBG             : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of FUSS_AUS : constant is 1;
+    attribute mti_svvh_generic_type of FUSS_ROT : constant is 1;
+    attribute mti_svvh_generic_type of FUSS_GRUEN : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_AUS : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_ROT : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_GELB : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_GRUEN : constant is 1;
+end ampel;

labor_3/Übungen/ampel/sim/work/mod_n_counter_10bit/_primary.vhd

@@ -0,0 +1,16 @@
+library verilog;
+use verilog.vl_types.all;
+entity mod_n_counter_10bit is
+    generic(
+        N               : integer := 10
+    );
+    port(
+        CLK             : in     vl_logic;
+        RST             : in     vl_logic;
+        EN              : in     vl_logic;
+        Q               : out    vl_logic_vector(9 downto 0);
+        TC              : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of N : constant is 1;
+end mod_n_counter_10bit;

labor_3/Übungen/ampel/sim/work/tb_ampel/_primary.vhd

@@ -1,4 +1,4 @@
 library verilog;
 use verilog.vl_types.all;
-entity spi_master_tb is
+entity tb_ampel is
-end spi_master_tb;
+end tb_ampel;

labor_3/Übungen/ampel/src/ampel.v

@@ -0,0 +1,505 @@
+/******************************************************
+*                                                     
+*  Description:  Vorlage Ampelsteurerung                                
+*         Date:  05.01.2018                          
+*    File Name:  ampel_wo_src.v                              
+*      Version:  1.2                                  
+*       Target:  Simulation and Synthesis             
+*   Technology:                                       
+*                                                     
+* Rev   Author   Date          Changes                
+* -----------------------------------------------------
+* 1.0   RHK      10.10.2011    Initial Release        
+* 1.1   JZ       10.03.2016    several bugfixes
+* 1.2   JZ       05.01.2018    angepasst auf neues Ampelboard
+* 1.3   MW       07.03.2019    STATE Konstanten angepasst
+*******************************************************/
+
+`timescale 1ns / 1ps
+
+module ampel (
+  input              CLOCK_50,
+  input        [1:0] KEY,
+  output       [2:0] LEDH_L,
+  output       [2:0] LEDH_R,
+  output       [2:0] LEDN_L,
+  output       [2:0] LEDN_R,
+  output       [1:0] LEDF_L,
+  output       [1:0] LEDF_R, 
+  output reg			DBG  
+);
+
+reg [9:0] CLKDIV1;
+reg [9:0] CLKDIV2;
+reg [9:0] CLKDIV3;
+
+reg MELDER;
+reg MELDER_Q;
+reg MELDER_QQ;
+reg MELDER_ACK;
+reg CLOCK_ENABLE;
+
+reg START_WARTEN;
+reg [3:0] STATE;
+reg [2:0] HAUPTSTR;
+reg [2:0] NEBENSTR;
+reg [1:0] FUSSGAENGER;
+
+reg [3:0] WARTEZAEHLER;
+reg [3:0] WARTEWERT;
+
+wire en_div_1;
+wire en_div_2;
+wire en_div_3;
+
+<<<<<<< HEAD
+wire tc_div_1;
+wire tc_div_2;
+wire tc_div_3;
+
+=======
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+wire [9:0] q_div_1;
+wire [9:0] q_div_2;
+wire [9:0] q_div_3;
+
+<<<<<<< HEAD
+=======
+wire tc_div_1;
+wire tc_div_2;
+wire tc_div_3;
+
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+//                       R Gr
+parameter FUSS_AUS   = 2'b00;
+parameter FUSS_ROT   = 2'b10;
+parameter FUSS_GRUEN = 2'b01;
+//                      R Ge Gr
+parameter AUTO_AUS   = 3'b000;
+parameter AUTO_ROT   = 3'b100;
+parameter AUTO_GELB  = 3'b010;
+parameter AUTO_GRUEN = 3'b001;
+
+assign RESET                     = ~KEY[1];
+
+assign LEDH_L  = HAUPTSTR;
+assign LEDH_R  = HAUPTSTR;
+assign LEDN_L = NEBENSTR;
+assign LEDN_R = NEBENSTR;
+assign LEDF_L = FUSSGAENGER;
+assign LEDF_R = FUSSGAENGER;
+
+`ifdef SIMULATION
+`define DIVVAL1 10-1
+`define DIVVAL3 5-1
+`else
+`define DIVVAL1 1000-1
+`define DIVVAL3 50-1
+`endif
+
+`define FUSS_WARTEN       4  //Wartezeit
+`define GELB_DAUER        4  //Wartezeit 
+`define FUSS_GRUEN_DAUER  4  //Wartezeit
+`define ALLE_ROT_DAUER    4  //Wartezeit
+
+`define HAUPT_GRUEN_DAUER 4  //Wartezeit
+`define NEBEN_GRUEN_DAUER 4  //Wartezeit
+
+
+`define PHASEVAL 8
+
+//clock divider to generate 1 Hz
+<<<<<<< HEAD
+//
+
+=======
+//Clock Enable Generation
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+assign en_div_1 = 1'b1;
+assign en_div_2 = tc_div_1;
+assign en_div_3 = tc_div_1 & tc_div_2;
+
+<<<<<<< HEAD
+always  begin
+      CLOCK_ENABLE = tc_div_3;
+end
+
+// synchronisze KEY to CLOCK_50
+always @(posedge CLOCK_50) begin
+=======
+always @(tc_div_3) begin
+      CLOCK_ENABLE <= tc_div_3;
+end
+
+// synchronisze KEY to CLOCK_50
+always @(posedge CLOCK_50 or posedge ~KEY[0]) begin
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+      MELDER_Q = ~KEY[0];
+      MELDER_QQ = MELDER_Q;
+end
+
+// Melder sofort setzen 
+// Melder zuruecksetzen wenn die Anforderung von der Statemachine verarbeitet
+// wurde. Die Ampelanlage gibt den FUSSGAENGERn nur dann gruen wenn
+// ein Melder anstehst...			
+<<<<<<< HEAD
+always @(posedge CLOCK_50 or negedge RESET) begin
+  if (RESET)
+    MELDER <= 1'b0;
+  else begin
+      case ({MELDER_QQ, MELDER_ACK})
+            2'b01: MELDER <= 1'b0;
+            2'b10: MELDER <= 1'b1;
+            2'b11: MELDER <= ~MELDER;
+            default: ;
+      endcase
+  end 	
+end   
+
+assign WARTEN_FERTIG = (WARTEZAEHLER == 4'b0000);
+
+//Wartezaehler
+always @(posedge CLOCK_50 or RESET) begin
+      if(RESET) begin
+            WARTEZAEHLER <= WARTEWERT;
+      end
+      else if(CLOCK_ENABLE)  begin
+            if (START_WARTEN)
+                  WARTEZAEHLER <= WARTEWERT;
+                  START_WARTEN <= 1'b0;
+            if (~WARTEN_FERTIG)
+                  WARTEZAEHLER <= WARTEZAEHLER - 1'b1;
+      end
+end
+
+always @(posedge CLOCK_50 or negedge RESET)
+=======
+always @(posedge CLOCK_50 or posedge RESET) begin
+  if (RESET)
+    MELDER <= 1'b0;
+  else begin
+      case ({MELDER_QQ,MELDER_ACK})
+            2'b00: ;
+            2'b01: MELDER <= 1'b0;
+            2'b10: MELDER <= 1'b1;
+            2'b11: MELDER <= ~MELDER;
+      endcase
+  end 	
+end            
+
+//Wartezaehler
+
+assign WARTEN_FERTIG = (WARTEZAEHLER == 1'b0);
+
+always @(posedge CLOCK_50 or posedge RESET) begin
+      if (RESET) begin
+            WARTEZAEHLER <= WARTEWERT;
+      end
+      else if (CLOCK_ENABLE) begin
+            if (~WARTEN_FERTIG) begin
+                  WARTEZAEHLER <= WARTEZAEHLER - 1'b1;
+            end
+            else if (START_WARTEN) begin
+                  START_WARTEN <= ~START_WARTEN;
+                  WARTEZAEHLER <= WARTEWERT;
+            end
+      end
+end
+
+
+always @(posedge CLOCK_50 or posedge RESET)
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+  if (RESET)
+    begin
+    HAUPTSTR     <= AUTO_GRUEN;
+    NEBENSTR     <= AUTO_ROT;
+    FUSSGAENGER  <= FUSS_ROT;
+    START_WARTEN <= 1'b0;
+    STATE        <= 4'd0;
+    MELDER_ACK   <= 1'b0;
+    end
+  else
+  if (CLOCK_ENABLE)
+  case (STATE)
+    4'd0: begin
+<<<<<<< HEAD
+            if(WARTEN_FERTIG) begin
+=======
+            if (~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd0;
+            end
+            else begin
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+                  HAUPTSTR <= AUTO_GRUEN;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `HAUPT_GRUEN_DAUER;
+<<<<<<< HEAD
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end        
+    4'd1: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR = AUTO_GELB;
+=======
+                  STATE <= 4'd1;
+            end
+          end        
+
+    4'd1: begin
+            if(~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd1;
+            end
+            else begin
+                  HAUPTSTR <= AUTO_GELB;
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `GELB_DAUER;
+<<<<<<< HEAD
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end
+    4'd2: begin
+            if(WARTEN_FERTIG && MELDER) begin
+=======
+                  STATE <= 4'd2;
+            end
+
+          end
+    4'd2: begin
+            if (~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd2;
+            end
+            else if (WARTEN_FERTIG && MELDER) begin
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `FUSS_WARTEN;
+<<<<<<< HEAD
+                  MELDER_ACK <= 1'b1; 
+
+            end else if (WARTEN_FERTIG && ~MELDER) begin
+=======
+                  MELDER_ACK <= 1'b1;
+                  STATE <= 4'd3;
+            end
+            else if (WARTEN_FERTIG && ~MELDER) begin
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `ALLE_ROT_DAUER;
+<<<<<<< HEAD
+
+            end else if(~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+            end
+          end
+    4'd3: begin
+            if(WARTEN_FERTIG) begin
+=======
+                  STATE <= 4'd4;
+            end
+
+          end
+    4'd3: begin
+            if (~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd3;
+            end
+            else begin
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_GRUEN;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `FUSS_GRUEN_DAUER;
+                  MELDER_ACK <= 1'b0;
+<<<<<<< HEAD
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end 
+    4'd4: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_GELB|AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `GELB_DAUER;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end
+    4'd5: begin
+            if(WARTEN_FERTIG) begin
+=======
+                  STATE <= 4'd2;
+            end
+          end 
+    4'd4: begin
+            if (~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd4;
+            end
+            else begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_GELB | AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `GELB_DAUER;
+                  STATE <= 4'd5;
+            end
+          end
+    4'd5: begin
+            if (~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd5;
+            end
+            else begin
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_GRUEN;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `NEBEN_GRUEN_DAUER;
+<<<<<<< HEAD
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end
+    4'd6: begin
+            if(WARTEN_FERTIG) begin
+=======
+                  STATE <= 4'd6;
+            end
+          end
+    4'd6: begin
+            if (~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd6;
+            end
+            else begin
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_GELB;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `GELB_DAUER;
+<<<<<<< HEAD
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end     
+    4'd7: begin
+            if(WARTEN_FERTIG) begin
+=======
+                  STATE <= 4'd7;
+            end
+          end     
+    4'd7: begin
+            if (~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd7;
+            end
+            else begin
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `ALLE_ROT_DAUER;
+<<<<<<< HEAD
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end     
+    4'd8: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR <= AUTO_GELB|AUTO_ROT;
+=======
+                  STATE <= 4'd8;
+            end
+          end         
+    4'd8: begin
+            if (~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd8;
+            end
+            else begin
+                  HAUPTSTR <= AUTO_GELB | AUTO_ROT;
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `GELB_DAUER;
+<<<<<<< HEAD
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+=======
+                  STATE <= 4'd0;
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+            end
+          end     
+    default:                      
+          STATE <= 4'd1;
+  endcase
+
+<<<<<<< HEAD
+mod_n_counter_10bit #(.N(`DIVVAL1)) clock_divider_1(
+=======
+mod_n_counter_10bit #(.N(`DIVVAL1)) divider_1(
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+      .CLK(CLOCK_50),
+      .RST(RESET),
+      .EN(en_div_1),
+      .Q(q_div_1),
+      .TC(tc_div_1)
+);
+
+<<<<<<< HEAD
+mod_n_counter_10bit #(.N(`DIVVAL1)) clock_divider_2(
+=======
+mod_n_counter_10bit #(.N(`DIVVAL1)) divider_2(
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+      .CLK(CLOCK_50),
+      .RST(RESET),
+      .EN(en_div_2),
+      .Q(q_div_2),
+      .TC(tc_div_2)
+);
+
+<<<<<<< HEAD
+mod_n_counter_10bit #(.N(`DIVVAL3)) clock_divider_3(
+=======
+mod_n_counter_10bit #(.N(`DIVVAL3)) divider_3(
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45
+      .CLK(CLOCK_50),
+      .RST(RESET),
+      .EN(en_div_3),
+      .Q(q_div_3),
+      .TC(tc_div_3)
+);
+                        
+<<<<<<< HEAD
+endmodule
+=======
+endmodule
+>>>>>>> 1b9840c27cab5a0b6374c25e1f14bde0476c9b45

labor_3/Übungen/ampel/src/ampel.v.bak

@@ -0,0 +1,307 @@
+/******************************************************
+*                                                     
+*  Description:  Vorlage Ampelsteurerung                                
+*         Date:  05.01.2018                          
+*    File Name:  ampel_wo_src.v                              
+*      Version:  1.2                                  
+*       Target:  Simulation and Synthesis             
+*   Technology:                                       
+*                                                     
+* Rev   Author   Date          Changes                
+* -----------------------------------------------------
+* 1.0   RHK      10.10.2011    Initial Release        
+* 1.1   JZ       10.03.2016    several bugfixes
+* 1.2   JZ       05.01.2018    angepasst auf neues Ampelboard
+* 1.3   MW       07.03.2019    STATE Konstanten angepasst
+*******************************************************/
+
+`timescale 1ns / 1ps
+
+module ampel (
+  input              CLOCK_50,
+  input        [1:0] KEY,
+  output       [2:0] LEDH_L,
+  output       [2:0] LEDH_R,
+  output       [2:0] LEDN_L,
+  output       [2:0] LEDN_R,
+  output       [1:0] LEDF_L,
+  output       [1:0] LEDF_R, 
+  output reg			DBG  
+);
+
+reg [9:0] CLKDIV1;
+reg [9:0] CLKDIV2;
+reg [9:0] CLKDIV3;
+
+reg MELDER;
+reg MELDER_Q;
+reg MELDER_QQ;
+reg MELDER_ACK;
+reg CLOCK_ENABLE;
+
+reg START_WARTEN;
+reg [3:0] STATE;
+reg [2:0] HAUPTSTR;
+reg [2:0] NEBENSTR;
+reg [1:0] FUSSGAENGER;
+
+reg [3:0] WARTEZAEHLER;
+reg [3:0] WARTEWERT;
+
+wire en_div_1;
+wire en_div_2;
+wire en_div_3;
+
+wire tc_div_1;
+wire tc_div_2;
+wire tc_div_3;
+
+wire [9:0] q_div_1;
+wire [9:0] q_div_2;
+wire [9:0] q_div_3;
+
+//                       R Gr
+parameter FUSS_AUS   = 2'b00;
+parameter FUSS_ROT   = 2'b10;
+parameter FUSS_GRUEN = 2'b01;
+//                      R Ge Gr
+parameter AUTO_AUS   = 3'b000;
+parameter AUTO_ROT   = 3'b100;
+parameter AUTO_GELB  = 3'b010;
+parameter AUTO_GRUEN = 3'b001;
+
+assign RESET                     = ~KEY[1];
+
+assign LEDH_L  = HAUPTSTR;
+assign LEDH_R  = HAUPTSTR;
+assign LEDN_L = NEBENSTR;
+assign LEDN_R = NEBENSTR;
+assign LEDF_L = FUSSGAENGER;
+assign LEDF_R = FUSSGAENGER;
+
+`ifdef SIMULATION
+`define DIVVAL1 10-1
+`define DIVVAL3 5-1
+`else
+`define DIVVAL1 1000-1
+`define DIVVAL3 50-1
+`endif
+
+`define FUSS_WARTEN       4  //Wartezeit
+`define GELB_DAUER        4  //Wartezeit 
+`define FUSS_GRUEN_DAUER  4  //Wartezeit
+`define ALLE_ROT_DAUER    4  //Wartezeit
+
+`define HAUPT_GRUEN_DAUER 4  //Wartezeit
+`define NEBEN_GRUEN_DAUER 4  //Wartezeit
+
+
+`define PHASEVAL 8
+
+//clock divider to generate 1 Hz
+//
+
+assign en_div_1 = 1'b1;
+assign en_div_2 = tc_div_1;
+assign en_div_3 = tc_div_1 & tc_div_2;
+
+always  begin
+      CLOCK_ENABLE = tc_div_3;
+end
+
+// synchronisze KEY to CLOCK_50
+always @(posedge CLOCK_50) begin
+      MELDER_Q = ~KEY[0];
+      MELDER_QQ = MELDER_Q;
+end
+
+// Melder sofort setzen 
+// Melder zuruecksetzen wenn die Anforderung von der Statemachine verarbeitet
+// wurde. Die Ampelanlage gibt den FUSSGAENGERn nur dann gruen wenn
+// ein Melder anstehst...			
+always @(posedge CLOCK_50 or negedge RESET) begin
+  if (RESET)
+    MELDER <= 1'b0;
+  else begin
+      case ({MELDER_QQ, MELDER_ACK})
+            2'b01: MELDER <= 1'b0;
+            2'b10: MELDER <= 1'b1;
+            2'b11: MELDER <= ~MELDER;
+            default: ;
+      endcase
+  end 	
+end   
+
+assign WARTEN_FERTIG = (WARTEZAEHLER == 4'b0000);
+
+//Wartezaehler
+always @(posedge CLOCK_50 or RESET) begin
+      if(RST) begin
+            WARTEZAEHLER <= WARTEWERT;
+      end
+      else if(CLOCK_ENABLE)  begin
+            if (START_WARTEN)
+                  WARTEZAEHLER <= WARTEWERT;
+                  START_WARTEN <= 1'b0;
+            if (~WARTEN_FERTIG)
+                  WARTEZAEHLER <= WARTEZAEHLER - 1'b1;
+      end
+end
+
+always @(posedge CLOCK_50 or negedge RESET)
+  if (RESET)
+    begin
+    HAUPTSTR     <= AUTO_GRUEN;
+    NEBENSTR     <= AUTO_ROT;
+    FUSSGAENGER  <= FUSS_ROT;
+    START_WARTEN <= 1'b0;
+    STATE        <= 4'd0;
+    MELDER_ACK   <= 1'b0;
+    end
+  else
+  if (CLOCK_ENABLE)
+  case (STATE)
+    4'd0: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR <= AUTO_GRUEN;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= HAUPT_GRUEN_DAUER;
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end        
+    4'd1: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR = AUTO_GELB;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= GELB_DAUER;
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end
+    4'd2: begin
+            if(WARTEN_FERTIG && MELDER) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= FUSS_WARTEN;
+                  MELDER_ACK <= 1'b1; 
+
+            end else if (WARTEN_FERTIG && ~MELDER) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= ALLE_ROT_DAUER;
+
+            end else if(~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+            end
+          end
+    4'd3: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_GRUEN;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= FUSS_GRUEN_DAUER;
+                  MELDER_ACK <= 1'b0;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end 
+    4'd4: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_GELB|AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= GELB_DAUER;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end
+    4'd5: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_GRUEN;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT = NEBEN_GRUEN_DAUER;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end
+    4'd6: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR = AUTO_ROT;
+                  NEBENSTR = AUTO_GELB;
+                  FUSSGAENGER = FUSS_ROT;
+                  START_WARTEN = 1'b1;
+                  WARTEWERT = GELB_DAUER;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end     
+    4'd7: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR = AUTO_ROT;
+                  NEBENSTR = AUTO_ROT;
+                  FUSSGAENGER = FUSS_ROT;
+                  START_WARTEN = 1'b1;
+                  WARTEWERT = ALLE_ROT_DAUER;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end     
+    4'd8: begin
+            if(WARTEN_FERTIG) begin
+                  HAUPTSTR = AUTO_GELB|AUTO_ROT;
+                  NEBENSTR = AUTO_ROT;
+                  FUSSGAENGER = FUSS_ROT;
+                  START_WARTEN = 1'b1;
+                  WARTEWERT = GELB_DAUER;
+
+            end else begin
+                  START_WARTEN <= 1'b0;
+            end
+          end     
+    default:                      
+          STATE <= 4'd1;
+  endcase
+
+mod_n_counter_10bit #(.N(DIVVAL1)) clock_divider_1(
+      .CLK(CLOCK_50),
+      .RST(RESET),
+      .EN(en_div_1),
+      .Q(q_div_1),
+      .TC(tc_div_1)
+);
+
+mod_n_counter_10bit #(.N(DIVVAL1)) clock_divider_2(
+      .CLK(CLOCK_50),
+      .RST(RESET),
+      .EN(en_div_2),
+      .Q(q_div_2),
+      .TC(tc_div_2)
+);
+
+mod_n_counter_10bit #(.N(DIVVAL3)) clock_divider_3(
+      .CLK(CLOCK_50),
+      .RST(RESET),
+      .EN(en_div_3),
+      .Q(q_div_3),
+      .TC(tc_div_3)
+);
+                        
+endmodule

labor_3/Übungen/ampel/src/jk_ff.v

@@ -0,0 +1,38 @@
+//Modellierung eines jk-ff
+//Autor: M. Erdem
+//Mat.-Nr.: 8757524
+//Datum: 21.02.2024
+
+module jk_ff (
+    //Ein- und Ausgänge anlegen
+    R,
+    CLK,
+    EN,
+    J,
+    K,
+    Q
+);    
+    input R, CLK, EN, J, K;
+    output reg Q;
+
+    //Verhaltensbeschreibung
+    always @(R or posedge CLK) begin
+
+        //Bei einem Reset soll Q auf 0 gesetzt werden
+        if(R) begin
+            Q <= 1'b0;
+
+            //Wenn EN = 1 dann soll das Modul aktiv sein
+        end else if (EN) begin
+
+            //Zustände von J und K werden analysiert und entsprechend Q angesteuert.
+            //Hierbei ist J Bit Nr. 1 und K ist Bit Nr. 0. (Von Rechts nach Links.)
+            case ({J, K})
+                2'b01: Q <= 1'b0;
+                2'b10: Q <= 1'b1;
+                2'b11: Q <= ~Q;
+                default: ;
+            endcase
+        end
+    end
+endmodule

labor_3/Übungen/ampel/src/mod_n_counter_10bit.v

@@ -0,0 +1,31 @@
+module mod_n_counter_10bit
+# (parameter N = 10)
+(
+  // module inputs
+  input CLK,
+  input RST,
+  input EN,
+  // module outputs
+  output reg [9:0] Q,
+  output TC
+);
+
+localparam TERMINAL_COUNT = N-1;
+
+always @ (posedge CLK or posedge RST) begin
+  if (RST) begin
+    Q <= 10'd0;
+  end else if (EN) begin
+    if (Q == TERMINAL_COUNT) begin
+      Q <= 10'd0;
+    end else begin
+      Q <= Q + 10'd1;
+    end
+  end else begin
+    Q <= Q;
+  end
+end
+
+assign TC = (Q == TERMINAL_COUNT);
+
+endmodule

labor_4/Aufgabe_6-3/quartus/db/prev_cmp_sclk_gen.qmsg

@@ -1,9 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1709148267302 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1709148267302 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 28 20:24:27 2024 " "Processing started: Wed Feb 28 20:24:27 2024" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1709148267302 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1709148267302 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sclk_gen -c sclk_gen " "Command: quartus_map --read_settings_files=on --write_settings_files=off sclk_gen -c sclk_gen" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1709148267302 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1709148267633 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/erdem/desktop/labor_eds/labor_4/aufgabe_6-3/src/sclk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/erdem/desktop/labor_eds/labor_4/aufgabe_6-3/src/sclk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 SCLK_gen " "Found entity 1: SCLK_gen" {  } { { "../src/sclk_gen.v" "" { Text "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/src/sclk_gen.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1709148267664 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1709148267664 ""}
-{ "Warning" "WSGN_FILE_IS_MISSING" "../src/d_ff.v " "Can't analyze file -- file ../src/d_ff.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1709148267680 ""}
-{ "Error" "ESGN_TOP_ENTITY_IS_MISSING" "sclk_gen " "Top-level design entity \"sclk_gen\" is undefined" {  } {  } 0 12007 "Top-level design entity \"%1!s!\" is undefined" 0 0 "Quartus II" 0 -1 1709148267711 ""}
-{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  2 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was unsuccessful. 1 error, 2 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "373 " "Peak virtual memory: 373 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1709148267758 ""} { "Error" "EQEXE_END_BANNER_TIME" "Wed Feb 28 20:24:27 2024 " "Processing ended: Wed Feb 28 20:24:27 2024" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1709148267758 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1709148267758 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1709148267758 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1709148267758 ""}
-{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 2 s " "Quartus II Full Compilation was unsuccessful. 3 errors, 2 warnings" {  } {  } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1709148268356 ""}

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.asm.qmsg

@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1709148352099 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1709148352099 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 28 20:25:51 2024 " "Processing started: Wed Feb 28 20:25:51 2024" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1709148352099 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1709148352099 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off sclk_gen -c sclk_gen " "Command: quartus_asm --read_settings_files=off --write_settings_files=off sclk_gen -c sclk_gen" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1709148352099 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1709148352831 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1709148352862 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "379 " "Peak virtual memory: 379 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1709148353177 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 28 20:25:53 2024 " "Processing ended: Wed Feb 28 20:25:53 2024" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1709148353177 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1709148353177 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1709148353177 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1709148353177 ""}

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.cbx.xml

@@ -1,5 +0,0 @@
-<?xml version="1.0" ?>
-<LOG_ROOT>
-	<PROJECT NAME="sclk_gen">
-	</PROJECT>
-</LOG_ROOT>

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.cmp.logdb

@@ -1,49 +0,0 @@
-v1
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,0;0;0;0;0;7;0;0;7;7;0;1;0;0;6;0;1;6;0;0;0;1;0;0;0;0;0;7;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,7;7;7;7;7;0;7;7;0;0;7;6;7;7;1;7;6;1;7;7;7;6;7;7;7;7;7;0;7;7,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,SCLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,CPHA,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,CPOL,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,RESETn,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,SYNC,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,ENA,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.db_info

@@ -1,3 +0,0 @@
-Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-Version_Index = 302049280
-Creation_Time = Wed Feb 28 19:17:51 2024

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.fit.qmsg

@@ -1,46 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1709148346155 ""}
-{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "sclk_gen EP4CGX15BF14C6 " "Automatically selected device EP4CGX15BF14C6 for design sclk_gen" {  } {  } 0 119004 "Automatically selected device %2!s! for design %1!s!" 0 0 "Fitter" 0 -1 1709148346255 ""}
-{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1709148346287 ""}
-{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1709148346287 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1709148346366 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1709148346386 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX30BF14C6 " "Device EP4CGX30BF14C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1709148346570 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX22BF14C6 " "Device EP4CGX22BF14C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1709148346570 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1709148346570 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCEO~ N5 " "Pin ~ALTERA_NCEO~ is reserved at location N5" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { ~ALTERA_NCEO~ } } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/" { { 0 { 0 ""} 0 26 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1709148346570 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ A5 " "Pin ~ALTERA_DATA0~ is reserved at location A5" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/" { { 0 { 0 ""} 0 28 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1709148346570 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO~ B5 " "Pin ~ALTERA_ASDO~ is reserved at location B5" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { ~ALTERA_ASDO~ } } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/" { { 0 { 0 ""} 0 30 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1709148346570 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCSO~ C5 " "Pin ~ALTERA_NCSO~ is reserved at location C5" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { ~ALTERA_NCSO~ } } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/" { { 0 { 0 ""} 0 32 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1709148346570 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ A4 " "Pin ~ALTERA_DCLK~ is reserved at location A4" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/" { { 0 { 0 ""} 0 34 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1709148346570 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1709148346570 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1709148346570 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "7 7 " "No exact pin location assignment(s) for 7 pins of 7 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SCLK " "Pin SCLK not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SCLK } } } { "../src/sclk_gen.v" "" { Text "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/src/sclk_gen.v" 9 0 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/" { { 0 { 0 ""} 0 9 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1709148346821 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CPHA " "Pin CPHA not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { CPHA } } } { "../src/sclk_gen.v" "" { Text "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/src/sclk_gen.v" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CPHA } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/" { { 0 { 0 ""} 0 6 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1709148346821 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CPOL " "Pin CPOL not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { CPOL } } } { "../src/sclk_gen.v" "" { Text "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/src/sclk_gen.v" 7 0 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CPOL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/" { { 0 { 0 ""} 0 8 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1709148346821 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLK " "Pin CLK not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { CLK } } } { "../src/sclk_gen.v" "" { Text "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/src/sclk_gen.v" 6 0 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/" { { 0 { 0 ""} 0 7 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1709148346821 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RESETn " "Pin RESETn not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RESETn } } } { "../src/sclk_gen.v" "" { Text "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/src/sclk_gen.v" 4 0 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RESETn } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/" { { 0 { 0 ""} 0 5 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1709148346821 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SYNC " "Pin SYNC not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SYNC } } } { "../src/sclk_gen.v" "" { Text "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/src/sclk_gen.v" 3 0 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SYNC } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/" { { 0 { 0 ""} 0 4 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1709148346821 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ENA " "Pin ENA not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/binLine truncated
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "sclk_gen.sdc " "Synopsys Design Constraints File file not found: 'sclk_gen.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1709148347042 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1709148347042 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1709148347042 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1709148347042 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1709148347042 ""}
-{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK~input (placed in PIN J7 (CLK13, DIFFCLK_7n, REFCLK0n)) " "Automatically promoted node CLK~input (placed in PIN J7 (CLK13, DIFFCLK_7n, REFCLK0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1709148347042 ""}  } { { "../src/sclk_gen.v" "" { Text "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/src/sclk_gen.v" 6 0 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/" { { 0 { 0 ""} 0 18 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1709148347042 ""}
-{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "RESETn~input (placed in PIN J6 (CLK12, DIFFCLK_7p, REFCLK0p)) " "Automatically promoted node RESETn~input (placed in PIN J6 (CLK12, DIFFCLK_7p, REFCLK0p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1709148347042 ""}  } { { "../src/sclk_gen.v" "" { Text "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/src/sclk_gen.v" 4 0 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RESETn~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/" { { 0 { 0 ""} 0 19 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1709148347042 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1709148347388 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1709148347388 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1709148347388 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1709148347388 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1709148347388 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1709148347388 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1709148347388 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1709148347388 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1709148347388 ""}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "5 unused 2.5V 4 1 0 " "Number of I/O pins in group: 5 (unused VREF, 2.5V VCCIO, 4 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1709148347388 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1709148347388 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1709148347388 ""}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL0 does not use undetermined 0 0 " "I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1709148347388 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 7 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  7 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1709148347388 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3A does not use undetermined 2 0 " "I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1709148347388 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 14 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1709148347388 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 12 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1709148347388 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 12 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1709148347388 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 14 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1709148347388 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8A does not use undetermined 0 2 " "I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1709148347388 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 5 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  5 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1709148347388 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 4 0 " "I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1709148347388 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1709148347388 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1709148347388 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1709148347388 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1709148348505 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1709148348551 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1709148348551 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1709148348756 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1709148348756 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1709148349119 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" {  } { { "loc" "" { Generic "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9"} 0 0 11 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1709148349654 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1709148349654 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1709148349841 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1709148349841 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1709148349841 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.02 " "Total time spent on timing analysis during the Fitter is 0.02 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1709148349841 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1709148349935 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1709148350093 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1709148350186 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1709148350296 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1709148350642 ""}
-{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "2 Cyclone IV GX " "2 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV GX Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLK 2.5 V J7 " "Pin CLK uses I/O standard 2.5 V at J7" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { CLK } } } { "../src/sclk_gen.v" "" { Text "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/src/sclk_gen.v" 6 0 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/" { { 0 { 0 ""} 0 7 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1709148350895 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "RESETn 2.5 V J6 " "Pin RESETn uses I/O standard 2.5 V at J6" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RESETn } } } { "../src/sclk_gen.v" "" { Text "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/src/sclk_gen.v" 4 0 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RESETn } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/" { { 0 { 0 ""} 0 5 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1709148350895 ""}  } {  } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1709148350895 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/output_files/sclk_gen.fit.smsg " "Generated suppressed messages file C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/quartus/output_files/sclk_gen.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1709148350956 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "577 " "Peak virtual memory: 577 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1709148351238 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 28 20:25:51 2024 " "Processing ended: Wed Feb 28 20:25:51 2024" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1709148351238 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1709148351238 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1709148351238 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1709148351238 ""}

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.hier_info

@@ -1,14 +0,0 @@
-|sclk_gen
-ENA => T1.IN1
-SYNC => Q1.ENA
-SYNC => T1.ENA
-RESETn => Q1.ACLR
-RESETn => T1.ACLR
-CPHA => SCLK_1.IN1
-CPHA => SCLK_0.IN1
-CLK => Q1.CLK
-CLK => T1.CLK
-CPOL => SCLK_3.IN1
-SCLK <= SCLK_3.DB_MAX_OUTPUT_PORT_TYPE
-
-

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.lpc.html

@@ -1,18 +0,0 @@
-<TABLE>
-<TR  bgcolor="#C0C0C0">
-<TH>Hierarchy</TH>
-<TH>Input</TH>
-<TH>Constant Input</TH>
-<TH>Unused Input</TH>
-<TH>Floating Input</TH>
-<TH>Output</TH>
-<TH>Constant Output</TH>
-<TH>Unused Output</TH>
-<TH>Floating Output</TH>
-<TH>Bidir</TH>
-<TH>Constant Bidir</TH>
-<TH>Unused Bidir</TH>
-<TH>Input only Bidir</TH>
-<TH>Output only Bidir</TH>
-</TR>
-</TABLE>

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.lpc.txt

@@ -1,5 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates                                                                                                                                                                                     ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.map.logdb

@@ -1 +0,0 @@
-v1

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.map.qmsg

@@ -1,11 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1709148343874 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1709148343874 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 28 20:25:43 2024 " "Processing started: Wed Feb 28 20:25:43 2024" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1709148343874 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1709148343874 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sclk_gen -c sclk_gen " "Command: quartus_map --read_settings_files=on --write_settings_files=off sclk_gen -c sclk_gen" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1709148343874 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1709148344189 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/erdem/desktop/labor_eds/labor_4/aufgabe_6-3/src/sclk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/erdem/desktop/labor_eds/labor_4/aufgabe_6-3/src/sclk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 sclk_gen " "Found entity 1: sclk_gen" {  } { { "../src/sclk_gen.v" "" { Text "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/src/sclk_gen.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1709148344236 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1709148344236 ""}
-{ "Warning" "WSGN_FILE_IS_MISSING" "../src/d_ff.v " "Can't analyze file -- file ../src/d_ff.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1709148344236 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "sclk_gen " "Elaborating entity \"sclk_gen\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1709148344267 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1709148344755 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1709148344961 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1709148344961 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "10 " "Implemented 10 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1709148344977 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1709148344977 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3 " "Implemented 3 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1709148344977 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1709148344977 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "390 " "Peak virtual memory: 390 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1709148344993 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 28 20:25:44 2024 " "Processing ended: Wed Feb 28 20:25:44 2024" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1709148344993 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1709148344993 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1709148344993 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1709148344993 ""}

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.map_bb.logdb

@@ -1 +0,0 @@
-v1

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.rpp.qmsg

@@ -1,4 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1709148362091 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 32-bit " "Running Quartus II 32-bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1709148362091 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 28 20:26:01 2024 " "Processing started: Wed Feb 28 20:26:01 2024" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1709148362091 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1709148362091 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp sclk_gen -c sclk_gen --netlist_type=sgate " "Command: quartus_rpp sclk_gen -c sclk_gen --netlist_type=sgate" {  } {  } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1709148362091 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "245 " "Peak virtual memory: 245 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1709148362123 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 28 20:26:02 2024 " "Processing ended: Wed Feb 28 20:26:02 2024" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1709148362123 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1709148362123 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1709148362123 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1709148362123 ""}

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.smart_action.txt

@@ -1 +0,0 @@
-DONE

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.sta.qmsg

@@ -1,41 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1709148354172 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354172 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 28 20:25:53 2024 " "Processing started: Wed Feb 28 20:25:53 2024" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1709148354172 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1709148354172 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta sclk_gen -c sclk_gen " "Command: quartus_sta sclk_gen -c sclk_gen" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1709148354172 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1709148354251 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1709148354392 ""}
-{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1709148354424 ""}
-{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1709148354424 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "sclk_gen.sdc " "Synopsys Design Constraints File file not found: 'sclk_gen.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1709148354675 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1709148354675 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK CLK " "create_clock -period 1.000 -name CLK CLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354690 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354690 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1709148354769 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354769 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1709148354769 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1709148354785 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.092 " "Worst-case setup slack is 0.092" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.092         0.000 CLK  " "    0.092         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.359 " "Worst-case hold slack is 0.359" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.359         0.000 CLK  " "    0.359         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148354785 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148354785 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1709148354800 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1709148354800 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354800 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354800 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -5.000 CLK  " "   -3.000        -5.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354800 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148354800 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1709148354816 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1709148354832 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1709148355036 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.186 " "Worst-case setup slack is 0.186" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.186         0.000 CLK  " "    0.186         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.318 " "Worst-case hold slack is 0.318" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.318         0.000 CLK  " "    0.318         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148355067 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148355067 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1709148355067 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1709148355067 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -5.000 CLK  " "   -3.000        -5.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1709148355099 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.506 " "Worst-case setup slack is 0.506" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.506         0.000 CLK  " "    0.506         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.193         0.000 CLK  " "    0.193         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148355287 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148355287 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1709148355287 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1709148355287 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -5.052 CLK  " "   -3.000        -5.052 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355287 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355287 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1709148355776 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1709148355776 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "376 " "Peak virtual memory: 376 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1709148355823 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 28 20:25:55 2024 " "Processing ended: Wed Feb 28 20:25:55 2024" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1709148355823 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1709148355823 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1709148355823 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1709148355823 ""}