Versucht. näher an die Lösung zu kommen.

Der Zustandsdiagramm zu der Ampelanlage wurde anhand der falschen Simulation beschrieben.

labor_3/res/ampel/sim __quartus13.1__/work/_info

@@ -17,7 +17,7 @@ OV;L;10.1d;51
 r1
 !s85 0
 31
-!s108 1708549845.999000
+!s108 1708601791.092000
 !s107 tb_ampel.v|
 !s90 -reportprogress|300|tb_ampel.v|
 !s101 -O0

labor_3/res/ampel/sim/modelsim.ini

@@ -17,8 +17,8 @@ others = $MODEL_TECH/../modelsim.ini
 ; Verilog Section
 ;
 
+ampel = designlib/ampel
 work = work
-spi_master = libs/spi_master
 [vcom]
 ; VHDL93 variable selects language version as the default. 
 ; Default is VHDL-2002.

labor_3/res/ampel/sim/wave.do

@@ -0,0 +1,29 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /tb_ampel/CLK
+add wave -noupdate /tb_ampel/RSTn
+add wave -noupdate /tb_ampel/SW
+add wave -noupdate /tb_ampel/HAUPTSTR_LINKS
+add wave -noupdate /tb_ampel/NEBENSTR_LINKS
+add wave -noupdate /tb_ampel/FUSSGAENGER_LINKS
+add wave -noupdate /tb_ampel/HAUPTSTR_RECHTS
+add wave -noupdate /tb_ampel/NEBENSTR_RECHTS
+add wave -noupdate /tb_ampel/FUSSGAENGER_RECHTS
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+quietly wave cursor active 0
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 5000
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {1 ns}

labor_3/res/ampel/sim/work/_info

@@ -0,0 +1,24 @@
+m255
+K3
+13
+cModel Technology
+Z0 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_3\res\ampel\sim
+vtb_ampel
+!i10b 1
+!s100 1oY2jolgFK??ee;z]EH8c2
+I:0IMZj9F7dM=NBGQ@:fYS0
+V6nf?5m:3VQD@E=_a?l5VH1
+Z1 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_3\res\ampel\sim
+w1708542298
+8tb_ampel.v
+Ftb_ampel.v
+L0 17
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1708602285.106000
+!s107 tb_ampel.v|
+!s90 -reportprogress|300|tb_ampel.v|
+!s101 -O0
+o-O0

labor_3/res/ampel/sim/work/tb_ampel/_primary.vhd

@@ -1,4 +1,4 @@
 library verilog;
 use verilog.vl_types.all;
-entity spi_master_tb is
+entity tb_ampel is
-end spi_master_tb;
+end tb_ampel;

labor_3/Übungen/ampel/sim/modelsim.ini

@@ -0,0 +1,324 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+;
+; Verilog Section
+;
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license isn't available
+; viewsim	Try for viewer license but accept simulator license(s) instead
+;		of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type).  Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and 
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer).  The other settings
+; are to send messages only to the transcript or only to the 
+; wlf file.  The valid values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both

labor_3/Übungen/ampel/sim/sim.tcl

@@ -0,0 +1,24 @@
+#JZ 2020
+
+#remove working directory
+file delete -force work
+
+#Creating the work lib
+vlib work
+#vmap ampel "designlib/ampel"
+vmap work work
+
+#Top level testbench
+vlog tb_ampel.v
+vlog ../src/ampel.v +define+SIMULATION
+vlog ../src/mod_n_counter_10bit.v
+
+#Simulate
+#vsim -c -t ps -L ampel tb_ampel
+vsim -c -t ps tb_ampel
+
+#get wave
+do wave.do
+
+run 1500 us
+#run 400 us

labor_3/Übungen/ampel/sim/tb_ampel.v

@@ -0,0 +1,67 @@
+/******************************************************
+*                                                     
+*  Description:  tb_ampel                                
+*         Date:  13.01.2018                           
+*    File Name:  tb_ampel.v                              
+*      Version:  1.0                                  
+*       Target:  Simulation             
+*   Technology:                                       
+*                                                     
+* Rev   Author   Date          Changes                
+* -----------------------------------------------------        
+* 1.0   JZ       13.01.2018    Testbench zur Ampelsteuerung
+*******************************************************/
+
+`timescale 1ns / 1ps
+
+module tb_ampel;
+
+reg CLK;
+reg RSTn;
+reg SW;
+
+wire [2:0] HAUPTSTR_LINKS;
+wire [2:0] NEBENSTR_LINKS;
+wire [1:0] FUSSGAENGER_LINKS;
+wire [2:0] HAUPTSTR_RECHTS;
+wire [2:0] NEBENSTR_RECHTS;
+wire [1:0] FUSSGAENGER_RECHTS;
+
+//50 MHz clock
+initial
+  begin
+  CLK  = 1'b0;
+  end
+
+always
+  CLK = #10 ~CLK;
+
+//push buttons
+initial
+  begin
+  RSTn = 1'b1;
+  SW = 1'b1;
+  #100;
+  RSTn = 1'b0;
+  #10;
+  RSTn = 1'b1;
+  #50_000;
+  SW = 1'b0;
+  #100;
+  SW = 1'b1;
+  end
+
+ampel ampel(
+.CLOCK_50 (CLK),
+.KEY ({RSTn, SW}),
+.LEDH_L(HAUPTSTR_LINKS),
+.LEDN_L(NEBENSTR_LINKS),
+.LEDF_L(FUSSGAENGER_LINKS),
+.LEDH_R(HAUPTSTR_RECHTS),
+.LEDN_R(NEBENSTR_RECHTS),
+.LEDF_R(FUSSGAENGER_RECHTS)
+);
+
+
+
+endmodule

labor_3/Übungen/ampel/sim/wave.do

@@ -0,0 +1,64 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /tb_ampel/CLK
+add wave -noupdate /tb_ampel/RSTn
+add wave -noupdate /tb_ampel/SW
+add wave -noupdate -subitemconfig {{/tb_ampel/HAUPTSTR_LINKS[2]} {-color Red -height 15} {/tb_ampel/HAUPTSTR_LINKS[1]} {-color Gold -height 15}} /tb_ampel/HAUPTSTR_LINKS
+add wave -noupdate -subitemconfig {{/tb_ampel/NEBENSTR_LINKS[2]} {-color Red -height 15} {/tb_ampel/NEBENSTR_LINKS[1]} {-color Gold -height 15}} /tb_ampel/NEBENSTR_LINKS
+add wave -noupdate -subitemconfig {{/tb_ampel/FUSSGAENGER_LINKS[1]} {-color Red -height 15}} /tb_ampel/FUSSGAENGER_LINKS
+add wave -noupdate -subitemconfig {{/tb_ampel/HAUPTSTR_RECHTS[2]} {-color Red -height 15} {/tb_ampel/HAUPTSTR_RECHTS[1]} {-color Gold -height 15}} /tb_ampel/HAUPTSTR_RECHTS
+add wave -noupdate -subitemconfig {{/tb_ampel/NEBENSTR_RECHTS[2]} {-color Red -height 15} {/tb_ampel/NEBENSTR_RECHTS[1]} {-color Gold -height 15}} /tb_ampel/NEBENSTR_RECHTS
+add wave -noupdate -subitemconfig {{/tb_ampel/FUSSGAENGER_RECHTS[1]} {-color Red -height 15}} /tb_ampel/FUSSGAENGER_RECHTS
+add wave -noupdate /tb_ampel/ampel/CLOCK_50
+add wave -noupdate /tb_ampel/ampel/KEY
+add wave -noupdate /tb_ampel/ampel/LEDH_L
+add wave -noupdate /tb_ampel/ampel/LEDH_R
+add wave -noupdate /tb_ampel/ampel/LEDN_L
+add wave -noupdate /tb_ampel/ampel/LEDN_R
+add wave -noupdate /tb_ampel/ampel/LEDF_L
+add wave -noupdate /tb_ampel/ampel/LEDF_R
+add wave -noupdate /tb_ampel/ampel/DBG
+add wave -noupdate /tb_ampel/ampel/CLKDIV1
+add wave -noupdate /tb_ampel/ampel/CLKDIV2
+add wave -noupdate /tb_ampel/ampel/CLKDIV3
+add wave -noupdate /tb_ampel/ampel/MELDER
+add wave -noupdate /tb_ampel/ampel/MELDER_Q
+add wave -noupdate /tb_ampel/ampel/MELDER_QQ
+add wave -noupdate /tb_ampel/ampel/MELDER_ACK
+add wave -noupdate /tb_ampel/ampel/CLOCK_ENABLE
+add wave -noupdate /tb_ampel/ampel/START_WARTEN
+add wave -noupdate /tb_ampel/ampel/STATE
+add wave -noupdate /tb_ampel/ampel/HAUPTSTR
+add wave -noupdate /tb_ampel/ampel/NEBENSTR
+add wave -noupdate /tb_ampel/ampel/FUSSGAENGER
+add wave -noupdate /tb_ampel/ampel/WARTEZAEHLER
+add wave -noupdate /tb_ampel/ampel/WARTEWERT
+add wave -noupdate /tb_ampel/ampel/en_div_1
+add wave -noupdate /tb_ampel/ampel/en_div_2
+add wave -noupdate /tb_ampel/ampel/en_div_3
+add wave -noupdate /tb_ampel/ampel/q_div_1
+add wave -noupdate /tb_ampel/ampel/q_div_2
+add wave -noupdate /tb_ampel/ampel/q_div_3
+add wave -noupdate /tb_ampel/ampel/tc_div_1
+add wave -noupdate /tb_ampel/ampel/tc_div_2
+add wave -noupdate /tb_ampel/ampel/tc_div_3
+add wave -noupdate /tb_ampel/ampel/RESET
+add wave -noupdate /tb_ampel/ampel/WARTEN_FERTIG
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {157723025 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 39
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 5000
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {420 us}

labor_3/Übungen/ampel/sim/work/_info

@@ -0,0 +1,63 @@
+m255
+K3
+13
+cModel Technology
+Z0 dC:\Users\Erdem\Desktop\labor_eds\labor_3\Übungen\ampel\sim
+vampel
+Z1 IaQGYY?BdBf@agb6lTWYkz3
+Z2 VRO2_FXGbKEQ9T<W2M?dVH1
+Z3 dC:\Users\Erdem\Desktop\labor_eds\labor_3\Übungen\ampel\sim
+Z4 w1708681481
+Z5 8../src/ampel.v
+Z6 F../src/ampel.v
+L0 20
+Z7 OV;L;10.1d;51
+r1
+31
+o-O0
+!i10b 1
+Z8 !s100 V^If:`L@9b]?^9XGzD5z@3
+!s85 0
+Z9 !s108 1708681485.221000
+Z10 !s107 ../src/ampel.v|
+Z11 !s90 -reportprogress|300|../src/ampel.v|+define+SIMULATION|
+!s101 -O0
+Z12 !s92 +define+SIMULATION -O0
+vmod_n_counter_10bit
+!i10b 1
+!s100 9e`GV_]:ML:l92jkefb>Q0
+IlLNUY`h`GTJ1?TjLj1BUS2
+VOCKRzhG[H7hm^_`n>48^e3
+R3
+Z13 w1708675165
+8../src/mod_n_counter_10bit.v
+F../src/mod_n_counter_10bit.v
+L0 1
+R7
+r1
+!s85 0
+31
+!s108 1708681485.276000
+!s107 ../src/mod_n_counter_10bit.v|
+!s90 -reportprogress|300|../src/mod_n_counter_10bit.v|
+!s101 -O0
+o-O0
+vtb_ampel
+Z14 I:0IMZj9F7dM=NBGQ@:fYS0
+Z15 V6nf?5m:3VQD@E=_a?l5VH1
+R3
+R13
+Z16 8tb_ampel.v
+Z17 Ftb_ampel.v
+L0 17
+R7
+r1
+31
+o-O0
+Z18 !s100 1oY2jolgFK??ee;z]EH8c2
+Z19 !s108 1708681485.163000
+Z20 !s107 tb_ampel.v|
+Z21 !s90 -reportprogress|300|tb_ampel.v|
+!i10b 1
+!s85 0
+!s101 -O0

labor_3/Übungen/ampel/sim/work/ampel/_primary.vhd

@@ -0,0 +1,32 @@
+library verilog;
+use verilog.vl_types.all;
+entity ampel is
+    generic(
+        FUSS_AUS        : vl_logic_vector(0 to 1) := (Hi0, Hi0);
+        FUSS_ROT        : vl_logic_vector(0 to 1) := (Hi1, Hi0);
+        FUSS_GRUEN      : vl_logic_vector(0 to 1) := (Hi0, Hi1);
+        AUTO_AUS        : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi0);
+        AUTO_ROT        : vl_logic_vector(0 to 2) := (Hi1, Hi0, Hi0);
+        AUTO_GELB       : vl_logic_vector(0 to 2) := (Hi0, Hi1, Hi0);
+        AUTO_GRUEN      : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi1)
+    );
+    port(
+        CLOCK_50        : in     vl_logic;
+        KEY             : in     vl_logic_vector(1 downto 0);
+        LEDH_L          : out    vl_logic_vector(2 downto 0);
+        LEDH_R          : out    vl_logic_vector(2 downto 0);
+        LEDN_L          : out    vl_logic_vector(2 downto 0);
+        LEDN_R          : out    vl_logic_vector(2 downto 0);
+        LEDF_L          : out    vl_logic_vector(1 downto 0);
+        LEDF_R          : out    vl_logic_vector(1 downto 0);
+        DBG             : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of FUSS_AUS : constant is 1;
+    attribute mti_svvh_generic_type of FUSS_ROT : constant is 1;
+    attribute mti_svvh_generic_type of FUSS_GRUEN : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_AUS : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_ROT : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_GELB : constant is 1;
+    attribute mti_svvh_generic_type of AUTO_GRUEN : constant is 1;
+end ampel;

labor_3/Übungen/ampel/sim/work/mod_n_counter_10bit/_primary.vhd

@@ -0,0 +1,16 @@
+library verilog;
+use verilog.vl_types.all;
+entity mod_n_counter_10bit is
+    generic(
+        N               : integer := 10
+    );
+    port(
+        CLK             : in     vl_logic;
+        RST             : in     vl_logic;
+        EN              : in     vl_logic;
+        Q               : out    vl_logic_vector(9 downto 0);
+        TC              : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of N : constant is 1;
+end mod_n_counter_10bit;

labor_3/Übungen/ampel/sim/work/tb_ampel/_primary.vhd

@@ -0,0 +1,4 @@
+library verilog;
+use verilog.vl_types.all;
+entity tb_ampel is
+end tb_ampel;

labor_3/Übungen/ampel/src/ampel.v

@@ -0,0 +1,334 @@
+/******************************************************
+*                                                     
+*  Description:  Vorlage Ampelsteurerung                                
+*         Date:  05.01.2018                          
+*    File Name:  ampel_wo_src.v                              
+*      Version:  1.2                                  
+*       Target:  Simulation and Synthesis             
+*   Technology:                                       
+*                                                     
+* Rev   Author   Date          Changes                
+* -----------------------------------------------------
+* 1.0   RHK      10.10.2011    Initial Release        
+* 1.1   JZ       10.03.2016    several bugfixes
+* 1.2   JZ       05.01.2018    angepasst auf neues Ampelboard
+* 1.3   MW       07.03.2019    STATE Konstanten angepasst
+*******************************************************/
+
+`timescale 1ns / 1ps
+
+module ampel (
+  input              CLOCK_50,
+  input        [1:0] KEY,
+  output       [2:0] LEDH_L,
+  output       [2:0] LEDH_R,
+  output       [2:0] LEDN_L,
+  output       [2:0] LEDN_R,
+  output       [1:0] LEDF_L,
+  output       [1:0] LEDF_R, 
+  output reg			DBG  
+);
+
+reg [9:0] CLKDIV1;
+reg [9:0] CLKDIV2;
+reg [9:0] CLKDIV3;
+
+reg MELDER;
+reg MELDER_Q;
+reg MELDER_QQ;
+reg MELDER_ACK;
+reg CLOCK_ENABLE;
+
+reg START_WARTEN;
+reg [3:0] STATE;
+reg [2:0] HAUPTSTR;
+reg [2:0] NEBENSTR;
+reg [1:0] FUSSGAENGER;
+
+reg [3:0] WARTEZAEHLER;
+reg [3:0] WARTEWERT;
+
+wire en_div_1;
+wire en_div_2;
+wire en_div_3;
+
+wire [9:0] q_div_1;
+wire [9:0] q_div_2;
+wire [9:0] q_div_3;
+
+wire tc_div_1;
+wire tc_div_2;
+wire tc_div_3;
+
+//                       R Gr
+parameter FUSS_AUS   = 2'b00;
+parameter FUSS_ROT   = 2'b10;
+parameter FUSS_GRUEN = 2'b01;
+//                      R Ge Gr
+parameter AUTO_AUS   = 3'b000;
+parameter AUTO_ROT   = 3'b100;
+parameter AUTO_GELB  = 3'b010;
+parameter AUTO_GRUEN = 3'b001;
+
+assign RESET                     = ~KEY[1];
+
+assign LEDH_L  = HAUPTSTR;
+assign LEDH_R  = HAUPTSTR;
+assign LEDN_L = NEBENSTR;
+assign LEDN_R = NEBENSTR;
+assign LEDF_L = FUSSGAENGER;
+assign LEDF_R = FUSSGAENGER;
+
+`ifdef SIMULATION
+`define DIVVAL1 10-1
+`define DIVVAL3 5-1
+`else
+`define DIVVAL1 1000-1
+`define DIVVAL3 50-1
+`endif
+
+`define FUSS_WARTEN       4  //Wartezeit
+`define GELB_DAUER        4  //Wartezeit 
+`define FUSS_GRUEN_DAUER  4  //Wartezeit
+`define ALLE_ROT_DAUER    4  //Wartezeit
+
+`define HAUPT_GRUEN_DAUER 4  //Wartezeit
+`define NEBEN_GRUEN_DAUER 4  //Wartezeit
+
+
+`define PHASEVAL 8
+
+//clock divider to generate 1 Hz
+//Clock Enable Generation
+assign en_div_1 = 1'b1;
+assign en_div_2 = tc_div_1;
+assign en_div_3 = tc_div_1 & tc_div_2;
+
+always @(tc_div_3) begin
+      CLOCK_ENABLE <= tc_div_3;
+end
+
+// synchronisze KEY to CLOCK_50
+always @(posedge CLOCK_50 or posedge ~KEY[0]) begin
+      MELDER_Q = ~KEY[0];
+      MELDER_QQ = MELDER_Q;
+end
+
+// Melder sofort setzen 
+// Melder zuruecksetzen wenn die Anforderung von der Statemachine verarbeitet
+// wurde. Die Ampelanlage gibt den FUSSGAENGERn nur dann gruen wenn
+// ein Melder anstehst...			
+always @(posedge CLOCK_50 or posedge RESET) begin
+  if (RESET)
+    MELDER <= 1'b0;
+  else begin
+      case ({MELDER_QQ,MELDER_ACK})
+            2'b00: ;
+            2'b01: MELDER <= 1'b0;
+            2'b10: MELDER <= 1'b1;
+            2'b11: MELDER <= ~MELDER;
+      endcase
+  end 	
+end            
+
+//Wartezaehler
+
+assign WARTEN_FERTIG = (WARTEZAEHLER == 1'b0);
+
+always @(posedge CLOCK_50 or posedge RESET) begin
+      if (RESET) begin
+            WARTEZAEHLER <= WARTEWERT;
+      end
+      else if (CLOCK_ENABLE) begin
+            if (~WARTEN_FERTIG) begin
+                  WARTEZAEHLER <= WARTEZAEHLER - 1'b1;
+            end
+            else if (START_WARTEN) begin
+                  START_WARTEN <= ~START_WARTEN;
+                  WARTEZAEHLER <= WARTEWERT;
+            end
+      end
+end
+
+
+always @(posedge CLOCK_50 or posedge RESET)
+  if (RESET)
+    begin
+    HAUPTSTR     <= AUTO_GRUEN;
+    NEBENSTR     <= AUTO_ROT;
+    FUSSGAENGER  <= FUSS_ROT;
+    START_WARTEN <= 1'b0;
+    STATE        <= 4'd0;
+    MELDER_ACK   <= 1'b0;
+    end
+  else
+  if (CLOCK_ENABLE)
+  case (STATE)
+    4'd0: begin
+            if (~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd0;
+            end
+            else begin
+                  HAUPTSTR <= AUTO_GRUEN;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `HAUPT_GRUEN_DAUER;
+                  STATE <= 4'd1;
+            end
+          end        
+
+    4'd1: begin
+            if(~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd1;
+            end
+            else begin
+                  HAUPTSTR <= AUTO_GELB;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `GELB_DAUER;
+                  STATE <= 4'd2;
+            end
+
+          end
+    4'd2: begin
+            if (~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd2;
+            end
+            else if (WARTEN_FERTIG && MELDER) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `FUSS_WARTEN;
+                  MELDER_ACK <= 1'b1;
+                  STATE <= 4'd3;
+            end
+            else if (WARTEN_FERTIG && ~MELDER) begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `ALLE_ROT_DAUER;
+                  STATE <= 4'd4;
+            end
+
+          end
+    4'd3: begin
+            if (~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd3;
+            end
+            else begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_GRUEN;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `FUSS_GRUEN_DAUER;
+                  MELDER_ACK <= 1'b0;
+                  STATE <= 4'd2;
+            end
+          end 
+    4'd4: begin
+            if (~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd4;
+            end
+            else begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_GELB | AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `GELB_DAUER;
+                  STATE <= 4'd5;
+            end
+          end
+    4'd5: begin
+            if (~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd5;
+            end
+            else begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_GRUEN;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `NEBEN_GRUEN_DAUER;
+                  STATE <= 4'd6;
+            end
+          end
+    4'd6: begin
+            if (~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd6;
+            end
+            else begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_GELB;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `GELB_DAUER;
+                  STATE <= 4'd7;
+            end
+          end     
+    4'd7: begin
+            if (~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd7;
+            end
+            else begin
+                  HAUPTSTR <= AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `ALLE_ROT_DAUER;
+                  STATE <= 4'd8;
+            end
+          end         
+    4'd8: begin
+            if (~WARTEN_FERTIG) begin
+                  START_WARTEN <= 1'b0;
+                  STATE <= 4'd8;
+            end
+            else begin
+                  HAUPTSTR <= AUTO_GELB | AUTO_ROT;
+                  NEBENSTR <= AUTO_ROT;
+                  FUSSGAENGER <= FUSS_ROT;
+                  START_WARTEN <= 1'b1;
+                  WARTEWERT <= `GELB_DAUER;
+                  STATE <= 4'd0;
+            end
+          end     
+    default:                      
+          STATE <= 4'd1;
+  endcase
+
+mod_n_counter_10bit #(.N(`DIVVAL1)) divider_1(
+      .CLK(CLOCK_50),
+      .RST(RESET),
+      .EN(en_div_1),
+      .Q(q_div_1),
+      .TC(tc_div_1)
+);
+
+mod_n_counter_10bit #(.N(`DIVVAL1)) divider_2(
+      .CLK(CLOCK_50),
+      .RST(RESET),
+      .EN(en_div_2),
+      .Q(q_div_2),
+      .TC(tc_div_2)
+);
+
+mod_n_counter_10bit #(.N(`DIVVAL3)) divider_3(
+      .CLK(CLOCK_50),
+      .RST(RESET),
+      .EN(en_div_3),
+      .Q(q_div_3),
+      .TC(tc_div_3)
+);
+                        
+endmodule

labor_3/Übungen/ampel/src/mod_n_counter_10bit.v

@@ -0,0 +1,31 @@
+module mod_n_counter_10bit
+# (parameter N = 10)
+(
+  // module inputs
+  input CLK,
+  input RST,
+  input EN,
+  // module outputs
+  output reg [9:0] Q,
+  output TC
+);
+
+localparam TERMINAL_COUNT = N-1;
+
+always @ (posedge CLK or posedge RST) begin
+  if (RST) begin
+    Q <= 10'd0;
+  end else if (EN) begin
+    if (Q == TERMINAL_COUNT) begin
+      Q <= 10'd0;
+    end else begin
+      Q <= Q + 10'd1;
+    end
+  end else begin
+    Q <= Q;
+  end
+end
+
+assign TC = (Q == TERMINAL_COUNT);
+
+endmodule

labor_4/README.md

@@ -1,37 +0,0 @@
-# Labor EDS: Labor 4
-
-## Übung 6: SPI Master
-
-### Vorbereitung 1
-
-Aufgabenstellung aus der Email:
-
-- Kapitel 6 durchlesen und Aufgaben 6.3 und 6.5 bearbeiten
-    - Auf dem Dozentenlaufwerk und auf Teams liegt der Ordner 'spi_master' mit der Vorlage 'spi_master_template.v'
-    - Vorlage kann mit 'sim_w_lib.do' kompiliert werden
-    - SImulation anschauen und versuchen zu verstehen
-
-- Aufgabe 6.3 ist eine Schaltung-zu-Code Übersetzung 
-    - das Modul 'sclk_gen' und eine Testbench dazu schreiben
-
-- Aufgabe 6.5:
-    - benötigt einen Zähler der statt einer festen Variable, eine von außen dynamisch vorgegebene Anzahl Schritte zählt
-    - Zähler als Modul vorbereiten und dazu eine kleine Testbench
-    - Zähler soll als Abwärtszähler arbeiten
-    - Beim Erreichen des Wertes 0 soll im nächsten Takt der Wert am Eingang CLOCK_DIVIDER ins Zählerregister geladen werden
-    - Wenn das Zählerregister 0 ist soll außerdem der Ausgang SYNC auf 1 gesetzt werden.
-
-
-**Eingänge:**
-
-CLK:            Taktsignal
-
-RESETn:         Asynchroner, 0-aktiver Reset, setzt alle Bits im Zählerregister auf 0
-
-CLOCK_DIVIDER:  Startwert für den Abwärtszähler
-
-**Ausgänge:**
-
-SYNC:             1 wenn alle Zählerregister 0, sonst 0
-
-manuel.walz@advantest.com

labor_4/res/spi_master/quartus/led_chaser.sdc

@@ -1,41 +0,0 @@
-#************************************************************
-# THIS IS A WIZARD-GENERATED FILE.                           
-#
-# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
-#
-#************************************************************
-
-# Copyright (C) 1991-2012 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-
-
-
-# Clock constraints
-
-create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}] -waveform {0.000 10.000}
-
-
-# Automatically constrain PLL and other generated clocks
-derive_pll_clocks -create_base_clocks
-
-# Automatically calculate clock uncertainty to jitter and other effects.
-#derive_clock_uncertainty
-# Not supported for family Cyclone II
-
-# tsu/th constraints
-
-# tco constraints
-
-# tpd constraints
-

labor_4/res/spi_master/quartus/led_chaser_pin_assignments.csv

@@ -1,93 +0,0 @@
-# Quartus II Version 5.1 Internal Build 160 09/19/2005 TO Full Version,
-# File: D:\de2_pins\de2_pins.csv,
-# Generated on: Wed Sep 28 09:40:34 2005,
-
-# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software.,
-
-To,Location
-SW[0],PIN_N25
-SW[1],PIN_N26
-SW[2],PIN_P25
-SW[3],PIN_AE14
-SW[4],PIN_AF14
-SW[5],PIN_AD13
-SW[6],PIN_AC13
-SW[7],PIN_C13
-SW[8],PIN_B13
-SW[9],PIN_A13
-SW[10],PIN_N1
-SW[11],PIN_P1
-SW[12],PIN_P2
-SW[13],PIN_T7
-SW[14],PIN_U3
-SW[15],PIN_U4
-
-LEDR[0],PIN_AE23
-LEDR[1],PIN_AF23
-LEDR[2],PIN_AB21
-LEDR[3],PIN_AC22
-LEDR[4],PIN_AD22
-LEDR[5],PIN_AD23
-LEDR[6],PIN_AD21
-LEDR[7],PIN_AC21
-LEDR[8],PIN_AA14
-LEDR[9],PIN_Y13
-LEDR[10],PIN_AA13
-LEDR[11],PIN_AC14
-LEDR[12],PIN_AD15
-LEDR[13],PIN_AE15
-LEDR[14],PIN_AF13
-LEDR[15],PIN_AE13
-
-LEDG[0],PIN_AE22
-LEDG[1],PIN_AF22
-LEDG[2],PIN_W19
-LEDG[3],PIN_V18
-LEDG[4],PIN_U18
-LEDG[5],PIN_U17
-LEDG[6],PIN_AA20
-LEDG[7],PIN_Y18
-CLOCK_50,PIN_N2
-
-SSn_A[0],PIN_D25
-SSn_A[1],PIN_J22
-SSn_A[2],PIN_E26
-SSn_A[3],PIN_E25
-MOSI_A,PIN_F24
-SCLK_A,PIN_F23
-MISO_A1,PIN_J21
-MISO_A2,PIN_J20
-SSn_D[0],PIN_F25
-SSn_D[1],PIN_F26
-SSn_D[2],PIN_N18
-SSn_D[3],PIN_P18
-MOSI_D,PIN_G23
-SCLK_D,PIN_G24
-MISO_D,PIN_K22
-PWM_OUT_A,PIN_G25
-PWM_OUT_B,PIN_H23
-PWM_IN_A,PIN_H24
-PWM_IN_B,PIN_J23
-
-MOSI_SCOPE,PIN_W23
-SCLK_SCOPE,PIN_V23
-MISO_SCOPE,PIN_W25
-
-LCD_RW,PIN_K4
-LCD_EN,PIN_K3
-LCD_RS,PIN_K1
-LCD_DATA[0],PIN_J1
-LCD_DATA[1],PIN_J2
-LCD_DATA[2],PIN_H1
-LCD_DATA[3],PIN_H2
-LCD_DATA[4],PIN_J4
-LCD_DATA[5],PIN_J3
-LCD_DATA[6],PIN_H4
-LCD_DATA[7],PIN_H3
-LCD_ON,PIN_L4
-LCD_BLON,PIN_K2
-
-KEY[0],PIN_G26
-KEY[1],PIN_N23
-KEY[2],PIN_P23
-KEY[3],PIN_W26

labor_4/res/spi_master/sim/libs/spi_master/_info

@@ -1,21 +0,0 @@
-m255
-K3
-13
-cModel Technology
-dC:\digitale_systeme\spi_master\sim
-vspi_master
-!s100 PDm=HJzS7gNQJSYmeO1UX1
-IN33U<eK;gRE;z6ImB8iaH3
-VVAEF_7[2`JEP650]dTjC60
-d.
-Fnofile
-L0 4
-OV;L;10.1b;51
-r1
-!s85 0
-31
-!s108 1521123190.954000
-!s107 ../src/spi_master.v|
-!s90 -reportprogress|300|-quiet|-nodebug|-work|spi_master|../src/spi_master.v|
-!s101 -O0
-o-quiet -nodebug -nodebug -work spi_master -O0

labor_4/res/spi_master/sim/libs/spi_master/spi_master/_primary.vhd

@@ -1,23 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity spi_master is
-    port(
-        RESETn          : in     vl_logic;
-        CLK             : in     vl_logic;
-        CLK_DIVIDER     : in     vl_logic_vector(7 downto 0);
-        SLAVE_SELECT    : in     vl_logic_vector(7 downto 0);
-        DATA_LENGTH     : in     vl_logic_vector(1 downto 0);
-        MODE            : in     vl_logic_vector(1 downto 0);
-        MISO            : in     vl_logic;
-        TX              : in     vl_logic_vector(31 downto 0);
-        RUN             : in     vl_logic;
-        RX              : out    vl_logic_vector(31 downto 0);
-        SCLK            : out    vl_logic;
-        MOSI            : out    vl_logic;
-        SSn             : out    vl_logic_vector(7 downto 0);
-        BUSY            : out    vl_logic;
-        SYNC_TEST       : out    vl_logic;
-        STATE_TEST      : out    vl_logic_vector(2 downto 0);
-        ENA_TEST        : out    vl_logic
-    );
-end spi_master;

labor_4/res/spi_master/sim/sim.do

@@ -1,19 +0,0 @@
-#remove working directory
-file delete -force work
-
-#Creating the work lib
-vlib work
-vmap work work
-
-
-#Top level testbench
-vlog spi_master_tb.v \
-     ../src/spi_master.v
-
-#Simulate
-vsim -c -t ps spi_master_tb 
-
-#get wave
-do wave.do
-
-run 25 us

labor_4/res/spi_master/sim/sim_w_lib.do

@@ -1,19 +0,0 @@
-#remove working directory
-file delete -force work
-
-#Creating the work lib
-vlib work
-vmap work work
-vlib "libs/spi_master"
-vmap spi_master "libs/spi_master"
-
-#Top level testbench
-vlog spi_master_tb.v 
-
-#Simulate
-vsim -c -t ps -L spi_master spi_master_tb 
-
-#get wave
-do wave.do
-
-run 25 us

labor_4/res/spi_master/sim/spi_master_tb.v

@@ -1,96 +0,0 @@
-`timescale 1ns/1ps
-
-module spi_master_tb;
-// top level testbench, no inputs or outputs
-
-  reg RESETn_TB, RUN_TB, CLOCK_50_TB;
-  reg [7:0] CLK_DIVIDER_TB, SLAVE_SELECT_TB;
-  reg [1:0] DATA_LENGTH_TB, MODE_TB;
-  reg [31:0] TX_TB;
-
-//DUT module outputs
-  wire [31:0] RX_TB;
-  wire [7:0]  SSn_TB;
-  wire SCLK_TB, MOSI_TB, BUSY_TB, MISO_TB;
-  
-//DUT test signals
-  wire [2:0] STATE_TEST_TB;
-  wire SYNC_TEST_TB, ENA_TEST_TB;
-  
-  assign MISO_TB = 1'b0;
-  
-  initial begin
-    // Reset
-    CLOCK_50_TB <= 1'b0;
-    RESETn_TB <= 1'b1;
-    
-    TX_TB <= 32'h0;
-    CLK_DIVIDER_TB <= 8'h0;
-    SLAVE_SELECT_TB <= 8'h0;
-    DATA_LENGTH_TB <= 2'b00;
-    MODE_TB <= 2'b00;
-    RUN_TB <= 1'b0;
-    
-    #20 RESETn_TB <= 1'b0;
-    #80 RESETn_TB <= 1'b1;
-    
-    // spi_master setup: 8 Bit Daten, Mode 0
-        
-    TX_TB <= 32'h000000AA;
-    CLK_DIVIDER_TB <= 8'h1;
-    SLAVE_SELECT_TB <= 8'h1;
-    DATA_LENGTH_TB <= 2'b00;
-    MODE_TB <= 2'b00;
-    
-    #100 RUN_TB <= 1'b1;
-    #100 RUN_TB <= 1'b0;
-
-    #5000
-
-    // spi_master setup: 16 Bit Daten, Mode 3    
-    TX_TB <= 32'h000084A8;
-    CLK_DIVIDER_TB <= 8'h4;
-    SLAVE_SELECT_TB <= 8'h1;
-    DATA_LENGTH_TB <= 2'b01;
-    MODE_TB <= 2'b11;
-    
-    #100 RUN_TB <= 1'b1;
-    #100 RUN_TB <= 1'b0;
-    
-    #7000
-    
-    // spi_master setup: 8 Bit Daten, Mode 2    
-    TX_TB <= 32'h000084A8;
-    CLK_DIVIDER_TB <= 8'h4;
-    SLAVE_SELECT_TB <= 8'h2;
-    DATA_LENGTH_TB <= 2'b00;
-    MODE_TB <= 2'b10;
-    
-    #100 RUN_TB <= 1'b1;
-    #100 RUN_TB <= 1'b0;
-    
-  end
-  
-  always begin
-    #10 CLOCK_50_TB <= ~CLOCK_50_TB;
-  end
-  
-  spi_master spi_master_test(
-  .RESETn(RESETn_TB),
-  .CLK(CLOCK_50_TB),
-  .RUN(RUN_TB),
-  .MODE(MODE_TB),
-  .DATA_LENGTH(DATA_LENGTH_TB),
-  .CLK_DIVIDER(CLK_DIVIDER_TB),
-  .SLAVE_SELECT(SLAVE_SELECT_TB),
-  .TX(TX_TB),
-  .SCLK(SCLK_TB),
-  .MISO(MISO_TB),
-  .MOSI(MOSI_TB),
-  .SSn(SSn_TB),
-  .RX(RX_TB),
-  .BUSY(BUSY_TB),
-  .SYNC_TEST(SYNC_TEST_TB),
-  .STATE_TEST(STATE_TEST_TB),
-  .ENA_TEST(ENA_TEST_TB));  
-endmodule

labor_4/res/spi_master/sim/wave.do

@@ -1,43 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate /spi_master_tb/RESETn_TB
-add wave -noupdate /spi_master_tb/RUN_TB
-add wave -noupdate /spi_master_tb/CLOCK_50_TB
-add wave -noupdate -radix unsigned /spi_master_tb/CLK_DIVIDER_TB
-add wave -noupdate /spi_master_tb/SLAVE_SELECT_TB
-add wave -noupdate /spi_master_tb/DATA_LENGTH_TB
-add wave -noupdate -radix unsigned /spi_master_tb/MODE_TB
-add wave -noupdate -radix hexadecimal /spi_master_tb/TX_TB
-add wave -noupdate -radix hexadecimal /spi_master_tb/RX_TB
-add wave -noupdate -divider {SPI Interface}
-add wave -noupdate /spi_master_tb/SSn_TB
-add wave -noupdate /spi_master_tb/SCLK_TB
-add wave -noupdate /spi_master_tb/MOSI_TB
-add wave -noupdate /spi_master_tb/BUSY_TB
-add wave -noupdate /spi_master_tb/MISO_TB
-add wave -noupdate -divider {SPI Master intern}
-add wave -noupdate /spi_master_tb/SYNC_TEST_TB
-add wave -noupdate -radix unsigned -childformat {{{/spi_master_tb/STATE_TEST_TB[2]} -radix unsigned} {{/spi_master_tb/STATE_TEST_TB[1]} -radix unsigned} {{/spi_master_tb/STATE_TEST_TB[0]} -radix unsigned}} -subitemconfig {{/spi_master_tb/STATE_TEST_TB[2]} {-radix unsigned} {/spi_master_tb/STATE_TEST_TB[1]} {-radix unsigned} {/spi_master_tb/STATE_TEST_TB[0]} {-radix unsigned}} /spi_master_tb/STATE_TEST_TB
-add wave -noupdate /spi_master_tb/ENA_TEST_TB
-add wave -noupdate /spi_master_tb/spi_master_test/BUSY
-add wave -noupdate -radix hexadecimal /spi_master_tb/spi_master_test/TX_SR
-add wave -noupdate -radix hexadecimal /spi_master_tb/spi_master_test/RX_SR
-add wave -noupdate -radix unsigned /spi_master_tb/spi_master_test/CYCLE_CTR
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {0 ps} 0}
-quietly wave cursor active 0
-configure wave -namecolwidth 232
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 0
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ns
-update
-WaveRestoreZoom {0 ps} {1640626 ps}

labor_4/res/spi_master/sim/work/_info

@@ -1,24 +0,0 @@
-m255
-K3
-13
-cModel Technology
-Z0 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_4\res\spi_master\sim
-vspi_master_tb
-!i10b 1
-!s100 WzH7KW]Xga2>VXnFzWQ6=2
-I_fR75FE<PVdhQ0XH_iiNO3
-VGVIa@54JI5PLOVOW3THe=0
-Z1 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_4\res\spi_master\sim
-w1709129563
-8spi_master_tb.v
-Fspi_master_tb.v
-L0 3
-OV;L;10.1d;51
-r1
-!s85 0
-31
-!s108 1709129621.059000
-!s107 spi_master_tb.v|
-!s90 -reportprogress|300|spi_master_tb.v|
-!s101 -O0
-o-O0

labor_4/res/spi_master/src/led_chaser.v

@@ -1,93 +0,0 @@
-module led_chaser(
-// module inputs
-CLOCK_50,
-KEY,
-SW,
-// module outputs
-SSn_D,
-MOSI_D,
-SCLK_D,
-LEDR
-);
-
-input [3:0] KEY;
-input CLOCK_50;
-input [15:0] SW;
-output [3:0] SSn_D;
-output MOSI_D, SCLK_D;
-output [15:0] LEDR;
-
-assign LEDR = LEDS;
-
-// Reset wire
-wire RESETn;
-assign RESETn = KEY[0];
-
-wire [15:0] LEDS;
-reg [9:0] CLKDIV0, CLKDIV1, CLKDIV2;
-
-`define DIVVAL0 1000-1
-`define DIVVAL1 1000-1
-`define DIVVAL2 50-1
-
-// Clock Divider
-always @(posedge CLOCK_50 or negedge RESETn)
-	if (~RESETn) CLKDIV0 <=`DIVVAL0;
-	else if (CLKDIV0 > 10'b0)
-      CLKDIV0[9:0] <= CLKDIV0[9:0] - 1'b1;
-    else
-      CLKDIV0[9:0] <= `DIVVAL0;
-
-always @(posedge CLOCK_50 or negedge RESETn)
-	if (~RESETn) CLKDIV1 <=`DIVVAL1;
-	else if (CLKDIV0[9:0] == 10'b0)
-      begin
-      if (CLKDIV1 > 10'b0)
-        CLKDIV1[9:0] <= CLKDIV1[9:0] - 1'b1;
-      else
-        CLKDIV1[9:0] <= `DIVVAL1;
-      end
-		
-always @(posedge CLOCK_50 or negedge RESETn)
-	if (~RESETn) CLKDIV2<=`DIVVAL2;
-	else if ((CLKDIV1[9:0] == 10'b0) & (CLKDIV0[9:0] == 10'b0))
-      begin
-      if (CLKDIV2 > 10'b0)
-        CLKDIV2[9:0] <= CLKDIV2[9:0] - 1'b1;
-      else
-        CLKDIV2[9:0] <= `DIVVAL2;
-      end
-
-// ring_sr
-
-ring_sr ring_shift_reg(
-	.CLK(CLOCK_50),
-	.RSTn(RESETn),
-	.ENA((CLKDIV0[9:0] == 10'b0) & (CLKDIV1[9:0] == 10'b0) & (CLKDIV2[9:0] == 10'b0)),
-	.PATTERN(SW),
-	.Q(LEDS[15:0]));
-	
-// SPI-Master
-spi_master spimaster(
-  .RESETn(RESETn),
-  .CLK(CLOCK_50),
-  .CLK_DIVIDER(8'd10),
-  .SLAVE_SELECT(8'h1),
-  .DATA_LENGTH(2'd1),
-  .MODE(2'd1),
-  .MISO(1'b1),
-  .TX({16'h0,LEDS}),
-  .RUN((CLKDIV0[9:0] == 10'b0) & (CLKDIV1[9:0] == 10'b0) & (CLKDIV2[9:0] == 10'b0)),
-  //module outputs
-  .RX(),
-  .SCLK(SCLK_D),
-  .MOSI(MOSI_D),
-  .SSn(SSn_D),
-  .BUSY(),
-  // module test outputs
-  .SYNC_TEST(),
-  .STATE_TEST(),
-  .ENA_TEST()  
-);
-	
-endmodule

labor_4/res/spi_master/src/ring_sr.v

@@ -1,23 +0,0 @@
-module ring_sr(
-  //inputs
-  PATTERN,
-  CLK,
-  RSTn,
-  ENA,
-  //outputs
-  Q);
-  
-  input [15:0] PATTERN;
-  input CLK,RSTn,ENA;
-  output reg [15:0] Q;
-  
-  always @(posedge CLK)
-    if(~RSTn) Q <= PATTERN;
-    
-    else if (ENA) 
-      begin
-        Q[15:1] <= Q[14:0];
-        Q[0] <= Q[15];
-      end
-      
-endmodule // ring_sr 

labor_4/res/spi_master/src/spi_master_template.v

@@ -1,86 +0,0 @@
-// module spi_master
-// Author: M. Walz
-
-module spi_master(
-  //module inputs
-  // --- Definition of control inputs ---
-  input wire        RESETn,
-  input wire        CLK,
-  input wire [7:0]  CLK_DIVIDER,
-  input wire [7:0]  SLAVE_SELECT,
-  input wire [1:0]  DATA_LENGTH,
-  input wire [1:0]  MODE,
-  input wire        MISO,
-  input wire [31:0] TX,
-  input wire RUN,
-  //module outputs
-  output reg [31:0] RX,
-  output            SCLK,
-  output reg        MOSI,
-  output reg [7:0]  SSn,
-  output reg        BUSY,
-  // module test outputs
-  output wire       SYNC_TEST,
-  output wire [2:0] STATE_TEST,
-  output wire       ENA_TEST  
-  );
-
-
-  
-  
-// --- Definition of internal varibles ---
-  reg [31:0]TX_SR, RX_SR;
-  reg [7:0] CLK_DIVIDER_REG;
-  reg [5:0] CYCLE_CTR;
-  reg [2:0] STATE;
-  reg ENA;                // Enables operation of SCLK generator
-  reg T1, Q1;             // Used for SLCK generation
-  wire CPOL, CPHA;        // SPI Mode
-  wire SYNC;              // SYNC Signal
-  
-// --- Implementation ---
-
-// assignments of test signals
-  assign STATE_TEST = STATE;
-  assign ENA_TEST = ENA;
-  assign SYNC_TEST = SYNC;
-
-// assignments MODE to control wires  
-  assign CPOL = MODE [1];
-  assign CPHA = MODE [0];
-  
-// Clockdivider for generation of SYNC signal
-
-always @ (posedge CLK or negedge RESETn) begin
-end
-
-// SPI-interface control logic
-
-always @ (posedge CLK or negedge RESETn) begin
-  if (~RESETn) begin
-  end 
-  else case (STATE)
-    // STATE: Wait
-    
-    // STATE: Initialize
-
-    // STATE: Shift
-
-    // STATE: Latch
-
-    // STATE:  
-
-	// When transfering data from RX to RX_SR, ignore previously received bytes
-				case (DATA_LENGTH[1:0])
-					2'h0 : RX[31:0] <= {24'h0, RX_SR[ 7:0]};	// 1 Byte received
-					2'h1 :  // 2 Bytes received	
-					2'h2 : // 3 Bytes received
-					2'h3 :   // 4 Bytes received
-				endcase
-
-  endcase
-end
-
-//  SPI SCLK generation
-
-endmodule