//cola testbench
`timescale 1ns/1ps

module tb_cola();

    reg tb_clk;
    reg tb_rst;
    reg tb_enable;
    reg dut_eineuro;
    reg dut_zweieuro;

    wire [1:0] dut_ausgabe;
    wire [1:0] dut_zustand;

    integer i = 0;

    initial begin
        tb_clk = 1'b0;
        tb_rst = 1'b0;
        tb_enable = 1'b0;
    end

    always begin
        #10;
        tb_clk = ~tb_clk;
    end

    initial begin
        for (i=0; i<4; i=i+1) begin
            @(negedge tb_clk);
        end

        dut_eineuro = 1'b0;
        dut_zweieuro = 1'b0;

        tb_rst = 1'b1;
        @(negedge tb_clk)

        tb_rst = 1'b0;
        @(negedge tb_clk)

        tb_enable = 1'b1;
        
        for (i=0; i<8; i=i+1) begin
            @(negedge tb_clk);
        end

        //Fall 1: 3 mal 1 Euro
        for (i=0; i<3; i=i+1) begin
            dut_eineuro = 1'b1;
            @(negedge tb_clk);
            dut_eineuro = 1'b0;
            @(negedge tb_clk);
        end

        for (i=0; i<=4; i=i+1) begin
            @(negedge tb_clk);
        end

        tb_rst = 1'b1;
        @(negedge tb_clk)

        tb_rst = 1'b0;
        @(negedge tb_clk)

        for (i=0; i<4; i=i+1) begin
            @(negedge tb_clk);
        end

        //Fall 2: 2 Euro + 1 Euro
        dut_zweieuro = 1'b1;
        @(negedge tb_clk);
        dut_zweieuro = 1'b0;
        @(negedge tb_clk);

        dut_eineuro = 1'b1;
        @(negedge tb_clk);
        dut_eineuro = 1'b0;
        @(negedge tb_clk);

        for (i=0; i<4; i=i+1) begin
            @(negedge tb_clk);
        end

    end

cola cola_dut(
    .CLK(tb_clk),
    .RST(tb_rst),
    .ENABLE(tb_enable),
    .EINEURO(dut_eineuro),
    .ZWEIEURO(dut_zweieuro),
    .AUSGABE(dut_ausgabe),
    .ZUSTAND(dut_zustand)
);

endmodule