Grundstruktur des Moore Automaten angelegt.

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2024-02-29 12:31:34 +01:00
parent 1a74cc5b56
commit 673abf9c48

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@@ -0,0 +1,87 @@
module sr_fsm (
input CLK,
input reset,
input run,
input Sync,
input CYCLE_CTR,
input MISO,
output MOSI,
output [7:0] SSn,
output ENA
);
//Definition der States
parameter STATE_WAIT = 3'h0;
parameter STATE_INIT = 3'h1;
parameter STATE_SHIFT = 3'h2;
parameter STATE_LATCH = 3'h3;
parameter STATE_CLEAR = 3'h4;
reg [2:0] STATE;
reg [2:0] NEXT_STATE;
//Bei jedem Takt wird der State auf den nächsten State gesetzt, wenn ein Reset anliegt wird der State 'Wait' vorgegeben.
always @(posedge CLK) begin
if(reset) begin
STATE = STATE_WAIT;
end
else begin
STATE = NEXT_STATE;
end
end
//Moore Automat
always @(STATE) begin
case (STATE)
STATE_WAIT:
if (run == 1'b1) begin
NEXT_STATE = STATE_INIT;
end
else begin
NEXT_STATE = STATE_WAIT;
end
STATE_INIT:
if (Sync == 1'b1) begin
NEXT_STATE = STATE_SHIFT;
end
else begin
NEXT_STATE = STATE_INIT;
end
STATE_SHIFT:
CYCLE_CTR = CYCLE_CTR - 1; //CYCLE_CTR dekrementieren
//Schieberegister schieben??
if (Sync == 1'b1) begin
NEXT_STATE = STATE_LATCH;
end
else begin
NEXT_STATE = STATE_SHIFT;
end
STATE_LATCH:
if (Sync == 1'b1 && CYCLE_CTR != 6'h0) begin
NEXT_STATE = STATE_SHIFT;
end
else if (Sync == 1'b1 && CYCLE_CTR == 6'h0) begin
NEXT_STATE = STATE_CLEAR;
end
else begin
NEXT_STATE = STATE_LATCH;
end
STATE_CLEAR:
if (Sync == 1'b1) begin
NEXT_STATE = STATE_WAIT;
end
else begin
NEXT_STATE = STATE_CLEAR;
end
default: NEXT_STATE = STATE;
endcase
end
endmodule