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Hochladen der vorherigen Laborübungen.

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Musab Erdem
2024-02-22 10:42:38 +01:00
parent e114dd98d9
commit 7d9ff524f9
293 changed files with 12180 additions and 0 deletions
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<sld_project_info>
<project>
<hash md5_digest_80b="00000000000000000000"/>
</project>
<file_info/>
</sld_project_info>

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 22:27:25 February 08, 2024
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "22:27:25 February 08, 2024"
# Revisions
PROJECT_REVISION = "d_ff"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 22:27:25 February 08, 2024
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# d_ff_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F672C6
set_global_assignment -name TOP_LEVEL_ENTITY d_ff
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:27:25 FEBRUARY 08, 2024"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name VERILOG_FILE ../src/d_ff.v
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1707427976416 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1707427976417 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 08 22:32:56 2024 " "Processing started: Thu Feb 08 22:32:56 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1707427976417 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1707427976417 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off d_ff -c d_ff " "Command: quartus_asm --read_settings_files=off --write_settings_files=off d_ff -c d_ff" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1707427976417 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1707427977424 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1707427977465 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4560 " "Peak virtual memory: 4560 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1707427977872 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 08 22:32:57 2024 " "Processing ended: Thu Feb 08 22:32:57 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1707427977872 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1707427977872 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1707427977872 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1707427977872 ""}

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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="d_ff">
</PROJECT>
</LOG_ROOT>

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v1

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Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
Creation_Time = Thu Feb 08 22:27:26 2024

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{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1707427972137 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "d_ff EP2C35F672C6 " "Selected device EP2C35F672C6 for design \"d_ff\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1707427972145 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1707427972169 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1707427972169 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1707427972221 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1707427972229 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Device EP2C50F672C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1707427972630 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Device EP2C70F672C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1707427972630 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1707427972630 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ E3 " "Pin ~ASDO~ is reserved at location E3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/" { { 0 { 0 ""} 0 13 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1707427972631 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ D3 " "Pin ~nCSO~ is reserved at location D3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/" { { 0 { 0 ""} 0 14 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1707427972631 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS150p/nCEO~ AE24 " "Pin ~LVDS150p/nCEO~ is reserved at location AE24" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~LVDS150p/nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~LVDS150p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/" { { 0 { 0 ""} 0 15 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1707427972631 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1707427972631 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "4 4 " "No exact pin location assignment(s) for 4 pins of 4 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q " "Pin Q not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { Q } } } { "../src/d_ff.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/src/d_ff.v" 11 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/" { { 0 { 0 ""} 0 3 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1707427972711 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Qn " "Pin Qn not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { Qn } } } { "../src/d_ff.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/src/d_ff.v" 12 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Qn } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/" { { 0 { 0 ""} 0 6 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1707427972711 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D " "Pin D not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { D } } } { "../src/d_ff.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/src/d_ff.v" 10 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { D } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/" { { 0 { 0 ""} 0 4 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1707427972711 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLK " "Pin CLK not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLK } } } { "../src/d_ff.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/src/d_ff.v" 10 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/" { { 0 { 0 ""} 0 5 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1707427972711 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1707427972711 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "d_ff.sdc " "Synopsys Design Constraints File file not found: 'd_ff.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1707427972783 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1707427972783 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1707427972784 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1707427972797 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1707427972797 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1707427972797 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1707427972798 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1707427972798 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1707427972798 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1707427972798 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1707427972798 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1707427972804 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1707427972804 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1707427972804 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "4 unused 3.3V 2 2 0 " "Number of I/O pins in group: 4 (unused VREF, 3.3V VCCIO, 2 input, 2 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1707427972805 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1707427972805 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1707427972805 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 0 64 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 64 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1707427972806 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 2 57 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 57 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1707427972806 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 56 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 56 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1707427972806 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 58 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 58 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1707427972806 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 65 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 65 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1707427972806 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 58 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 58 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1707427972806 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 58 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 58 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1707427972806 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 56 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 56 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1707427972806 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1707427972806 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1707427972806 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1707427972810 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1707427974000 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1707427974059 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1707427974065 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1707427974208 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1707427974208 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1707427974248 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X22_Y24 X32_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y24 to location X32_Y36" { } { { "loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y24 to location X32_Y36"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y24 to location X32_Y36"} 22 24 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1707427974817 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1707427974817 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1707427974984 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1707427974986 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1707427974986 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1707427974986 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.13 " "Total time spent on timing analysis during the Fitter is 0.13 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1707427974993 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1707427974995 ""}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "2 " "Found 2 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q 0 " "Pin \"Q\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1707427974996 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Qn 0 " "Pin \"Qn\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1707427974996 ""} } { } 0 306006 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "Fitter" 0 -1 1707427974996 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1707427975055 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1707427975060 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1707427975121 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1707427975366 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1707427975435 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/output_files/d_ff.fit.smsg " "Generated suppressed messages file C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/output_files/d_ff.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1707427975493 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4875 " "Peak virtual memory: 4875 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1707427975600 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 08 22:32:55 2024 " "Processing ended: Thu Feb 08 22:32:55 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1707427975600 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1707427975600 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1707427975600 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1707427975600 ""}

7
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|d_ff
D => Q~reg0.DATAIN
CLK => Q~reg0.CLK
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
Qn <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE

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<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
</TABLE>

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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1707427970183 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1707427970184 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 08 22:32:50 2024 " "Processing started: Thu Feb 08 22:32:50 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1707427970184 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1707427970184 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off d_ff -c d_ff " "Command: quartus_map --read_settings_files=on --write_settings_files=off d_ff -c d_ff" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1707427970184 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1707427970502 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/d_ff/src/d_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/d_ff/src/d_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 d_ff " "Found entity 1: d_ff" { } { { "../src/d_ff.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/src/d_ff.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1707427970553 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1707427970553 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "d_ff " "Elaborating entity \"d_ff\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1707427970578 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1707427970981 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1707427970981 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "5 " "Implemented 5 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1707427971015 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1707427971015 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1707427971015 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1707427971015 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4599 " "Peak virtual memory: 4599 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1707427971033 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 08 22:32:51 2024 " "Processing ended: Thu Feb 08 22:32:51 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1707427971033 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1707427971033 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1707427971033 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1707427971033 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1707428007067 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 64-Bit " "Running Quartus II 64-Bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1707428007068 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 08 22:33:26 2024 " "Processing started: Thu Feb 08 22:33:26 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1707428007068 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1707428007068 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp d_ff -c d_ff --netlist_type=sgate " "Command: quartus_rpp d_ff -c d_ff --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1707428007068 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4428 " "Peak virtual memory: 4428 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1707428007101 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 08 22:33:27 2024 " "Processing ended: Thu Feb 08 22:33:27 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1707428007101 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1707428007101 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1707428007101 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1707428007101 ""}

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DONE

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1707427978827 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1707427978827 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 08 22:32:58 2024 " "Processing started: Thu Feb 08 22:32:58 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1707427978827 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1707427978827 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta d_ff -c d_ff " "Command: quartus_sta d_ff -c d_ff" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1707427978827 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1707427978907 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1707427979013 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1707427979039 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1707427979039 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "d_ff.sdc " "Synopsys Design Constraints File file not found: 'd_ff.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1707427979098 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1707427979098 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK CLK " "create_clock -period 1.000 -name CLK CLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1707427979098 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1707427979098 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1707427979109 ""}
{ "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1707427979302 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427979302 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427979312 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427979318 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427979318 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427979323 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1707427979323 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1707427979328 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1707427979328 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -2.380 CLK " " -1.380 -2.380 CLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1707427979328 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1707427979328 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1707427979333 ""}
{ "Info" "0" "" "Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1707427979333 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427979344 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427979349 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427979349 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427979355 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1707427979355 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1707427979355 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1707427979355 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -2.380 CLK " " -1.380 -2.380 CLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1707427979355 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1707427979355 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1707427979366 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1707427979381 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1707427979381 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4540 " "Peak virtual memory: 4540 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1707427979423 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 08 22:32:59 2024 " "Processing ended: Thu Feb 08 22:32:59 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1707427979423 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1707427979423 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1707427979423 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1707427979423 ""}

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start_full_compilation:s:00:00:11
start_analysis_synthesis:s:00:00:02-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:05-start_full_compilation
start_assembler:s:00:00:02-start_full_compilation
start_timing_analyzer:s:00:00:02-start_full_compilation

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1707427707237 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1707427707237 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 08 22:28:27 2024 " "Processing started: Thu Feb 08 22:28:27 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1707427707237 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1707427707237 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off d_ff -c d_ff " "Command: quartus_map --read_settings_files=on --write_settings_files=off d_ff -c d_ff" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1707427707237 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1707427707531 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/d_ff/src/d_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/d_ff/src/d_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 d_ff " "Found entity 1: d_ff" { } { { "../src/d_ff.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/src/d_ff.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1707427707574 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1707427707574 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "d_ff " "Elaborating entity \"d_ff\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1707427707600 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1707427707924 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1707427707924 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "6 " "Implemented 6 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1707427707957 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1707427707957 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2 " "Implemented 2 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1707427707957 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1707427707957 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4599 " "Peak virtual memory: 4599 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1707427707979 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 08 22:28:27 2024 " "Processing ended: Thu Feb 08 22:28:27 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1707427707979 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1707427707979 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1707427707979 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1707427707979 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1707427708982 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1707427708983 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 08 22:28:28 2024 " "Processing started: Thu Feb 08 22:28:28 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1707427708983 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1707427708983 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off d_ff -c d_ff " "Command: quartus_fit --read_settings_files=off --write_settings_files=off d_ff -c d_ff" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1707427708983 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1707427709057 ""}
{ "Info" "0" "" "Project = d_ff" { } { } 0 0 "Project = d_ff" 0 0 "Fitter" 0 0 1707427709058 ""}
{ "Info" "0" "" "Revision = d_ff" { } { } 0 0 "Revision = d_ff" 0 0 "Fitter" 0 0 1707427709058 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1707427709107 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "d_ff EP2C35F672C6 " "Selected device EP2C35F672C6 for design \"d_ff\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1707427709114 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1707427709139 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1707427709139 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1707427709186 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1707427709195 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Device EP2C50F672C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1707427709593 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Device EP2C70F672C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1707427709593 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1707427709593 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ E3 " "Pin ~ASDO~ is reserved at location E3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/" { { 0 { 0 ""} 0 14 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1707427709594 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ D3 " "Pin ~nCSO~ is reserved at location D3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/" { { 0 { 0 ""} 0 15 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1707427709594 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS150p/nCEO~ AE24 " "Pin ~LVDS150p/nCEO~ is reserved at location AE24" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~LVDS150p/nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~LVDS150p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/" { { 0 { 0 ""} 0 16 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1707427709594 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1707427709594 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "4 4 " "No exact pin location assignment(s) for 4 pins of 4 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q " "Pin Q not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { Q } } } { "../src/d_ff.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/src/d_ff.v" 11 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/" { { 0 { 0 ""} 0 4 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1707427709671 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Qn " "Pin Qn not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { Qn } } } { "../src/d_ff.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/src/d_ff.v" 11 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Qn } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/" { { 0 { 0 ""} 0 3 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1707427709671 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D " "Pin D not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { D } } } { "../src/d_ff.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/src/d_ff.v" 10 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { D } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/" { { 0 { 0 ""} 0 5 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1707427709671 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLK " "Pin CLK not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLK } } } { "../src/d_ff.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/src/d_ff.v" 10 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/" { { 0 { 0 ""} 0 6 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1707427709671 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1707427709671 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "d_ff.sdc " "Synopsys Design Constraints File file not found: 'd_ff.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1707427709741 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1707427709742 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1707427709743 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK (placed in PIN P2 (CLK2, LVDSCLK1p, Input)) " "Automatically promoted node CLK (placed in PIN P2 (CLK2, LVDSCLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1707427709748 ""} } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLK } } } { "../src/d_ff.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/src/d_ff.v" 10 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/" { { 0 { 0 ""} 0 6 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1707427709748 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1707427709790 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1707427709790 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1707427709790 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1707427709792 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1707427709792 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1707427709792 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1707427709792 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1707427709793 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1707427709798 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1707427709798 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1707427709798 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "3 unused 3.3V 1 2 0 " "Number of I/O pins in group: 3 (unused VREF, 3.3V VCCIO, 1 input, 2 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1707427709799 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1707427709799 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1707427709799 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 63 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 63 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1707427709800 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 2 57 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 57 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1707427709800 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 56 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 56 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1707427709800 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 58 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 58 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1707427709800 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 65 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 65 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1707427709800 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 58 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 58 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1707427709800 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 58 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 58 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1707427709800 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 56 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 56 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1707427709800 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1707427709800 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1707427709800 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1707427709804 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1707427711003 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1707427711060 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1707427711066 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1707427711217 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1707427711217 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1707427711253 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X22_Y24 X32_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y24 to location X32_Y36" { } { { "loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y24 to location X32_Y36"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y24 to location X32_Y36"} 22 24 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1707427711791 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1707427711791 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1707427711921 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1707427711922 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1707427711922 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1707427711922 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1707427711929 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1707427711931 ""}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "2 " "Found 2 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q 0 " "Pin \"Q\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1707427711932 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Qn 0 " "Pin \"Qn\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1707427711932 ""} } { } 0 306006 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "Fitter" 0 -1 1707427711932 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1707427711993 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1707427711998 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1707427712060 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1707427712333 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1707427712403 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/output_files/d_ff.fit.smsg " "Generated suppressed messages file C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/output_files/d_ff.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1707427712467 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4875 " "Peak virtual memory: 4875 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1707427712600 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 08 22:28:32 2024 " "Processing ended: Thu Feb 08 22:28:32 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1707427712600 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1707427712600 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1707427712600 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1707427712600 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1707427713461 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1707427713462 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 08 22:28:33 2024 " "Processing started: Thu Feb 08 22:28:33 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1707427713462 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1707427713462 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off d_ff -c d_ff " "Command: quartus_asm --read_settings_files=off --write_settings_files=off d_ff -c d_ff" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1707427713462 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1707427714468 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1707427714515 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4560 " "Peak virtual memory: 4560 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1707427714931 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 08 22:28:34 2024 " "Processing ended: Thu Feb 08 22:28:34 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1707427714931 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1707427714931 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1707427714931 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1707427714931 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1707427715505 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1707427715925 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1707427715926 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 08 22:28:35 2024 " "Processing started: Thu Feb 08 22:28:35 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1707427715926 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1707427715926 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta d_ff -c d_ff " "Command: quartus_sta d_ff -c d_ff" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1707427715926 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1707427716013 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1707427716135 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1707427716163 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1707427716163 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "d_ff.sdc " "Synopsys Design Constraints File file not found: 'd_ff.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1707427716233 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1707427716233 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK CLK " "create_clock -period 1.000 -name CLK CLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1707427716234 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1707427716234 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1707427716235 ""}
{ "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1707427716245 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427716246 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427716252 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427716255 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427716258 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427716261 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1707427716262 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1707427716265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1707427716265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -3.380 CLK " " -1.380 -3.380 CLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1707427716265 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1707427716265 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1707427716273 ""}
{ "Info" "0" "" "Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1707427716274 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427716283 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427716286 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427716290 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1707427716293 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1707427716293 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1707427716297 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1707427716297 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -3.380 CLK " " -1.380 -3.380 CLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1707427716297 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1707427716297 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1707427716305 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1707427716321 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1707427716321 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4540 " "Peak virtual memory: 4540 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1707427716371 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 08 22:28:36 2024 " "Processing ended: Thu Feb 08 22:28:36 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1707427716371 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1707427716371 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1707427716371 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1707427716371 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 11 s " "Quartus II Full Compilation was successful. 0 errors, 11 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1707427716977 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1707427792938 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 64-Bit " "Running Quartus II 64-Bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1707427792938 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 08 22:29:52 2024 " "Processing started: Thu Feb 08 22:29:52 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1707427792938 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1707427792938 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp d_ff -c d_ff --netlist_type=sgate " "Command: quartus_rpp d_ff -c d_ff --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1707427792938 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4429 " "Peak virtual memory: 4429 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1707427792980 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 08 22:29:52 2024 " "Processing ended: Thu Feb 08 22:29:52 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1707427792980 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1707427792980 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1707427792980 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1707427792980 ""}

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This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

3
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Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
Creation_Time = Thu Feb 08 22:27:26 2024

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v1

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9a9b3e9d06db00b9dc03feca87af856c

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Assembler report for d_ff
Thu Feb 08 22:32:57 2024
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/output_files/d_ff.sof
6. Assembler Device Options: C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/output_files/d_ff.pof
7. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Thu Feb 08 22:32:57 2024 ;
; Revision Name ; d_ff ;
; Top-level Entity Name ; d_ff ;
; Family ; Cyclone II ;
; Device ; EP2C35F672C6 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Generate compressed bitstreams ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Auto user code ; On ; On ;
; Use configuration device ; On ; On ;
; Configuration device ; Auto ; Auto ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+----------+---------------+
+------------------------------------------------------------------------------------------------------------------------+
; Assembler Generated Files ;
+------------------------------------------------------------------------------------------------------------------------+
; File Name ;
+------------------------------------------------------------------------------------------------------------------------+
; C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/output_files/d_ff.sof ;
; C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/output_files/d_ff.pof ;
+------------------------------------------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/output_files/d_ff.sof ;
+----------------+---------------------------------------------------------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+---------------------------------------------------------------------------------------------------------------------------------+
; Device ; EP2C35F672C6 ;
; JTAG usercode ; 0x002F82EE ;
; Checksum ; 0x002F82EE ;
+----------------+---------------------------------------------------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/quartus/output_files/d_ff.pof ;
+--------------------+-----------------------------------------------------------------------------------------------------------------------------+
; Option ; Setting ;
+--------------------+-----------------------------------------------------------------------------------------------------------------------------+
; Device ; EPCS16 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x1C790232 ;
; Compression Ratio ; 3 ;
+--------------------+-----------------------------------------------------------------------------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Thu Feb 08 22:32:56 2024
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off d_ff -c d_ff
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4560 megabytes
Info: Processing ended: Thu Feb 08 22:32:57 2024
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

1
labor_1/d_ff/quartus/output_files/d_ff.done Normal file
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@@ -0,0 +1 @@
Thu Feb 08 22:33:27 2024

1294
labor_1/d_ff/quartus/output_files/d_ff.fit.rpt Normal file
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File diff suppressed because it is too large Load Diff

8
labor_1/d_ff/quartus/output_files/d_ff.fit.smsg Normal file
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@@ -0,0 +1,8 @@
Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
Extra Info (176236): Started Fast Input/Output/OE register processing
Extra Info (176237): Finished Fast Input/Output/OE register processing
Extra Info (176238): Start inferring scan chains for DSP blocks
Extra Info (176239): Inferring scan chains for DSP blocks is complete
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

16
labor_1/d_ff/quartus/output_files/d_ff.fit.summary Normal file
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@@ -0,0 +1,16 @@
Fitter Status : Successful - Thu Feb 08 22:32:55 2024
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : d_ff
Top-level Entity Name : d_ff
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 1 / 33,216 ( < 1 % )
Total combinational functions : 0 / 33,216 ( 0 % )
Dedicated logic registers : 1 / 33,216 ( < 1 % )
Total registers : 1
Total pins : 4 / 475 ( < 1 % )
Total virtual pins : 0
Total memory bits : 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )

122
labor_1/d_ff/quartus/output_files/d_ff.flow.rpt Normal file
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Flow report for d_ff
Thu Feb 08 22:32:59 2024
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Thu Feb 08 22:32:57 2024 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; d_ff ;
; Top-level Entity Name ; d_ff ;
; Family ; Cyclone II ;
; Device ; EP2C35F672C6 ;
; Timing Models ; Final ;
; Total logic elements ; 1 / 33,216 ( < 1 % ) ;
; Total combinational functions ; 0 / 33,216 ( 0 % ) ;
; Dedicated logic registers ; 1 / 33,216 ( < 1 % ) ;
; Total registers ; 1 ;
; Total pins ; 4 / 475 ( < 1 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 483,840 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+-------------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 02/08/2024 22:32:50 ;
; Main task ; Compilation ;
; Revision Name ; d_ff ;
+-------------------+---------------------+
+------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+---------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+---------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 246775572656857.170742797020780 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+-------------------------------------+---------------------------------+---------------+-------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 4589 MB ; 00:00:00 ;
; Fitter ; 00:00:04 ; 1.0 ; 4875 MB ; 00:00:03 ;
; Assembler ; 00:00:01 ; 1.0 ; 4560 MB ; 00:00:01 ;
; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4540 MB ; 00:00:01 ;
; Total ; 00:00:06 ; -- ; -- ; 00:00:05 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; DESKTOP-MSP383K ; Windows 7 ; 6.2 ; x86_64 ;
; Fitter ; DESKTOP-MSP383K ; Windows 7 ; 6.2 ; x86_64 ;
; Assembler ; DESKTOP-MSP383K ; Windows 7 ; 6.2 ; x86_64 ;
; TimeQuest Timing Analyzer ; DESKTOP-MSP383K ; Windows 7 ; 6.2 ; x86_64 ;
+---------------------------+------------------+-----------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off d_ff -c d_ff
quartus_fit --read_settings_files=off --write_settings_files=off d_ff -c d_ff
quartus_asm --read_settings_files=off --write_settings_files=off d_ff -c d_ff
quartus_sta d_ff -c d_ff

8
labor_1/d_ff/quartus/output_files/d_ff.jdi Normal file
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@@ -0,0 +1,8 @@
<sld_project_info>
<project>
<hash md5_digest_80b="4525fb60407042eeee70"/>
</project>
<file_info>
<file device="EP2C35F672C6" path="d_ff.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>

254
labor_1/d_ff/quartus/output_files/d_ff.map.rpt Normal file
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@@ -0,0 +1,254 @@
Analysis & Synthesis report for d_ff
Thu Feb 08 22:32:51 2024
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. General Register Statistics
9. Elapsed Time Per Partition
10. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Feb 08 22:32:51 2024 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; d_ff ;
; Top-level Entity Name ; d_ff ;
; Family ; Cyclone II ;
; Total logic elements ; 1 ;
; Total combinational functions ; 0 ;
; Dedicated logic registers ; 1 ;
; Total registers ; 1 ;
; Total pins ; 4 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+-------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C35F672C6 ; ;
; Top-level entity name ; d_ff ; d_ff ;
; Family name ; Cyclone II ; Cyclone IV GX ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; Off ; Off ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+--------------------+--------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 12 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------------+---------+
; ../src/d_ff.v ; yes ; User Verilog HDL File ; C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/d_ff/src/d_ff.v ; ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------------+---------+
+------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+--------+
; Resource ; Usage ;
+---------------------------------------------+--------+
; Estimated Total logic elements ; 1 ;
; ; ;
; Total combinational functions ; 0 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 3 input functions ; 0 ;
; -- <=2 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 0 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers ; 1 ;
; -- Dedicated logic registers ; 1 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 4 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Maximum fan-out node ; Q~reg0 ;
; Maximum fan-out ; 2 ;
; Total fan-out ; 4 ;
; Average fan-out ; 0.80 ;
+---------------------------------------------+--------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |d_ff ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; |d_ff ; work ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 1 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:00 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Thu Feb 08 22:32:50 2024
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off d_ff -c d_ff
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/d_ff/src/d_ff.v
Info (12023): Found entity 1: d_ff
Info (12127): Elaborating entity "d_ff" for the top level hierarchy
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 5 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 2 input pins
Info (21059): Implemented 2 output pins
Info (21061): Implemented 1 logic cells
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4599 megabytes
Info: Processing ended: Thu Feb 08 22:32:51 2024
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00

14
labor_1/d_ff/quartus/output_files/d_ff.map.summary Normal file
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@@ -0,0 +1,14 @@
Analysis & Synthesis Status : Successful - Thu Feb 08 22:32:51 2024
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : d_ff
Top-level Entity Name : d_ff
Family : Cyclone II
Total logic elements : 1
Total combinational functions : 0
Dedicated logic registers : 1
Total registers : 1
Total pins : 4
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0

742
labor_1/d_ff/quartus/output_files/d_ff.pin Normal file
View File

@@ -0,0 +1,742 @@
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- Bank 5: 3.3V
-- Bank 6: 3.3V
-- Bank 7: 3.3V
-- Bank 8: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
CHIP "d_ff" ASSIGNED TO AN: EP2C35F672C6
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND : A2 : gnd : : : :
VCCIO3 : A3 : power : : 3.3V : 3 :
GND* : A4 : : : : 3 :
GND* : A5 : : : : 3 :
GND* : A6 : : : : 3 :
GND* : A7 : : : : 3 :
GND* : A8 : : : : 3 :
GND* : A9 : : : : 3 :
GND* : A10 : : : : 3 :
VCCIO3 : A11 : power : : 3.3V : 3 :
GND : A12 : gnd : : : :
GND+ : A13 : : : : 4 :
GND* : A14 : : : : 4 :
GND : A15 : gnd : : : :
VCCIO4 : A16 : power : : 3.3V : 4 :
GND* : A17 : : : : 4 :
GND* : A18 : : : : 4 :
GND* : A19 : : : : 4 :
GND* : A20 : : : : 4 :
GND* : A21 : : : : 4 :
GND* : A22 : : : : 4 :
GND* : A23 : : : : 4 :
VCCIO4 : A24 : power : : 3.3V : 4 :
GND : A25 : gnd : : : :
GND* : AA1 : : : : 1 :
GND* : AA2 : : : : 1 :
GND* : AA3 : : : : 1 :
GND* : AA4 : : : : 1 :
GND* : AA5 : : : : 1 :
GND* : AA6 : : : : 1 :
GND* : AA7 : : : : 1 :
VCCA_PLL1 : AA8 : power : : 1.2V : :
GND* : AA9 : : : : 8 :
GND* : AA10 : : : : 8 :
GND* : AA11 : : : : 8 :
GND* : AA12 : : : : 8 :
GND* : AA13 : : : : 7 :
GND* : AA14 : : : : 7 :
GND* : AA15 : : : : 7 :
GND* : AA16 : : : : 7 :
GND* : AA17 : : : : 7 :
GND* : AA18 : : : : 7 :
VCCA_PLL4 : AA19 : power : : 1.2V : :
GND* : AA20 : : : : 7 :
GND_PLL4 : AA21 : gnd : : : :
VCCIO6 : AA22 : power : : 3.3V : 6 :
GND* : AA23 : : : : 6 :
GND* : AA24 : : : : 6 :
GND* : AA25 : : : : 6 :
GND* : AA26 : : : : 6 :
GND* : AB1 : : : : 1 :
GND* : AB2 : : : : 1 :
GND* : AB3 : : : : 1 :
GND* : AB4 : : : : 1 :
VCCIO1 : AB5 : power : : 3.3V : 1 :
VCCIO8 : AB6 : power : : 3.3V : 8 :
GND : AB7 : gnd : : : :
GND* : AB8 : : : : 8 :
VCCIO8 : AB9 : power : : 3.3V : 8 :
GND* : AB10 : : : : 8 :
GND : AB11 : gnd : : : :
GND* : AB12 : : : : 8 :
VCCIO8 : AB13 : power : : 3.3V : 8 :
VCCIO7 : AB14 : power : : 3.3V : 7 :
GND* : AB15 : : : : 7 :
GND : AB16 : gnd : : : :
VCCIO7 : AB17 : power : : 3.3V : 7 :
GND* : AB18 : : : : 7 :
GND : AB19 : gnd : : : :
GND* : AB20 : : : : 7 :
GND* : AB21 : : : : 7 :
VCCIO7 : AB22 : power : : 3.3V : 7 :
GND* : AB23 : : : : 6 :
GND* : AB24 : : : : 6 :
GND* : AB25 : : : : 6 :
GND* : AB26 : : : : 6 :
GND* : AC1 : : : : 1 :
GND* : AC2 : : : : 1 :
GND* : AC3 : : : : 1 :
GND : AC4 : gnd : : : :
GND* : AC5 : : : : 8 :
GND* : AC6 : : : : 8 :
GND* : AC7 : : : : 8 :
GND* : AC8 : : : : 8 :
GND* : AC9 : : : : 8 :
GND* : AC10 : : : : 8 :
GND* : AC11 : : : : 8 :
GND* : AC12 : : : : 8 :
GND+ : AC13 : : : : 8 :
GND* : AC14 : : : : 7 :
GND* : AC15 : : : : 7 :
GND* : AC16 : : : : 7 :
GND* : AC17 : : : : 7 :
GND* : AC18 : : : : 7 :
GND* : AC19 : : : : 7 :
GND* : AC20 : : : : 7 :
GND* : AC21 : : : : 7 :
GND* : AC22 : : : : 7 :
GND* : AC23 : : : : 6 :
NC : AC24 : : : : :
GND* : AC25 : : : : 6 :
GND* : AC26 : : : : 6 :
VCCIO1 : AD1 : power : : 3.3V : 1 :
GND* : AD2 : : : : 1 :
GND* : AD3 : : : : 1 :
GND* : AD4 : : : : 8 :
GND* : AD5 : : : : 8 :
GND* : AD6 : : : : 8 :
GND* : AD7 : : : : 8 :
GND* : AD8 : : : : 8 :
GND : AD9 : gnd : : : :
GND* : AD10 : : : : 8 :
GND* : AD11 : : : : 8 :
GND* : AD12 : : : : 8 :
GND+ : AD13 : : : : 8 :
GND : AD14 : gnd : : : :
GND* : AD15 : : : : 7 :
GND* : AD16 : : : : 7 :
GND* : AD17 : : : : 7 :
GND : AD18 : gnd : : : :
GND* : AD19 : : : : 7 :
VCCIO7 : AD20 : power : : 3.3V : 7 :
GND* : AD21 : : : : 7 :
GND* : AD22 : : : : 7 :
GND* : AD23 : : : : 7 :
GND* : AD24 : : : : 6 :
GND* : AD25 : : : : 6 :
VCCIO6 : AD26 : power : : 3.3V : 6 :
GND : AE1 : gnd : : : :
GND* : AE2 : : : : 1 :
GND* : AE3 : : : : 1 :
GND* : AE4 : : : : 8 :
GND* : AE5 : : : : 8 :
GND* : AE6 : : : : 8 :
GND* : AE7 : : : : 8 :
GND* : AE8 : : : : 8 :
GND* : AE9 : : : : 8 :
GND* : AE10 : : : : 8 :
GND* : AE11 : : : : 8 :
GND* : AE12 : : : : 8 :
GND* : AE13 : : : : 8 :
GND+ : AE14 : : : : 7 :
GND* : AE15 : : : : 7 :
GND* : AE16 : : : : 7 :
GND* : AE17 : : : : 7 :
GND* : AE18 : : : : 7 :
GND* : AE19 : : : : 7 :
GND* : AE20 : : : : 7 :
GND* : AE21 : : : : 7 :
GND* : AE22 : : : : 7 :
GND* : AE23 : : : : 7 :
~LVDS150p/nCEO~ : AE24 : output : 3.3-V LVTTL : : 6 : N
GND* : AE25 : : : : 6 :
GND : AE26 : gnd : : : :
GND : AF2 : gnd : : : :
VCCIO8 : AF3 : power : : 3.3V : 8 :
GND* : AF4 : : : : 8 :
GND* : AF5 : : : : 8 :
GND* : AF6 : : : : 8 :
GND* : AF7 : : : : 8 :
GND* : AF8 : : : : 8 :
GND* : AF9 : : : : 8 :
GND* : AF10 : : : : 8 :
VCCIO8 : AF11 : power : : 3.3V : 8 :
GND : AF12 : gnd : : : :
GND* : AF13 : : : : 8 :
GND+ : AF14 : : : : 7 :
GND : AF15 : gnd : : : :
VCCIO7 : AF16 : power : : 3.3V : 7 :
GND* : AF17 : : : : 7 :
GND* : AF18 : : : : 7 :
GND* : AF19 : : : : 7 :
GND* : AF20 : : : : 7 :
GND* : AF21 : : : : 7 :
GND* : AF22 : : : : 7 :
GND* : AF23 : : : : 7 :
VCCIO7 : AF24 : power : : 3.3V : 7 :
GND : AF25 : gnd : : : :
GND : B1 : gnd : : : :
GND* : B2 : : : : 2 :
GND* : B3 : : : : 2 :
GND* : B4 : : : : 3 :
GND* : B5 : : : : 3 :
GND* : B6 : : : : 3 :
GND* : B7 : : : : 3 :
GND* : B8 : : : : 3 :
GND* : B9 : : : : 3 :
GND* : B10 : : : : 3 :
GND* : B11 : : : : 3 :
Qn : B12 : output : 3.3-V LVTTL : : 3 : N
GND+ : B13 : : : : 4 :
GND* : B14 : : : : 4 :
GND* : B15 : : : : 4 :
GND* : B16 : : : : 4 :
GND* : B17 : : : : 4 :
GND* : B18 : : : : 4 :
GND* : B19 : : : : 4 :
GND* : B20 : : : : 4 :
GND* : B21 : : : : 4 :
GND* : B22 : : : : 4 :
GND* : B23 : : : : 4 :
GND* : B24 : : : : 5 :
GND* : B25 : : : : 5 :
GND : B26 : gnd : : : :
VCCIO2 : C1 : power : : 3.3V : 2 :
GND* : C2 : : : : 2 :
GND* : C3 : : : : 2 :
GND* : C4 : : : : 3 :
GND* : C5 : : : : 3 :
GND* : C6 : : : : 3 :
GND* : C7 : : : : 3 :
GND* : C8 : : : : 3 :
GND* : C9 : : : : 3 :
GND* : C10 : : : : 3 :
GND* : C11 : : : : 3 :
Q : C12 : output : 3.3-V LVTTL : : 3 : N
D : C13 : input : 3.3-V LVTTL : : 3 : N
GND : C14 : gnd : : : :
GND* : C15 : : : : 4 :
GND* : C16 : : : : 4 :
GND* : C17 : : : : 4 :
GND : C18 : gnd : : : :
GND* : C19 : : : : 4 :
VCCIO4 : C20 : power : : 3.3V : 4 :
GND* : C21 : : : : 4 :
GND* : C22 : : : : 4 :
GND* : C23 : : : : 4 :
GND* : C24 : : : : 5 :
GND* : C25 : : : : 5 :
VCCIO5 : C26 : power : : 3.3V : 5 :
GND* : D1 : : : : 2 :
GND* : D2 : : : : 2 :
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : input : 3.3-V LVTTL : : 2 : N
GND : D4 : gnd : : : :
GND* : D5 : : : : 3 :
GND* : D6 : : : : 3 :
GND* : D7 : : : : 3 :
GND* : D8 : : : : 3 :
GND* : D9 : : : : 3 :
GND* : D10 : : : : 3 :
GND* : D11 : : : : 3 :
GND* : D12 : : : : 3 :
CLK : D13 : input : 3.3-V LVTTL : : 3 : N
GND* : D14 : : : : 4 :
GND* : D15 : : : : 4 :
GND* : D16 : : : : 4 :
GND* : D17 : : : : 4 :
GND* : D18 : : : : 4 :
GND* : D19 : : : : 4 :
GND* : D20 : : : : 4 :
GND* : D21 : : : : 4 :
VCCIO4 : D22 : power : : 3.3V : 4 :
GND* : D23 : : : : 5 :
GND : D24 : gnd : : : :
GND* : D25 : : : : 5 :
GND* : D26 : : : : 5 :
GND* : E1 : : : : 2 :
GND* : E2 : : : : 2 :
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : input : 3.3-V LVTTL : : 2 : N
GND_PLL3 : E4 : gnd : : : :
GND* : E5 : : : : 2 :
VCCIO3 : E6 : power : : 3.3V : 3 :
GND : E7 : gnd : : : :
GND* : E8 : : : : 3 :
VCCIO3 : E9 : power : : 3.3V : 3 :
GND* : E10 : : : : 3 :
GND : E11 : gnd : : : :
GND* : E12 : : : : 3 :
VCCIO3 : E13 : power : : 3.3V : 3 :
VCCIO4 : E14 : power : : 3.3V : 4 :
GND* : E15 : : : : 4 :
GND : E16 : gnd : : : :
VCCIO4 : E17 : power : : 3.3V : 4 :
GND* : E18 : : : : 4 :
GND : E19 : gnd : : : :
GND* : E20 : : : : 4 :
GND_PLL2 : E21 : gnd : : : :
GND* : E22 : : : : 5 :
GND* : E23 : : : : 5 :
GND* : E24 : : : : 5 :
GND* : E25 : : : : 5 :
GND* : E26 : : : : 5 :
GND* : F1 : : : : 2 :
GND* : F2 : : : : 2 :
GND* : F3 : : : : 2 :
GND* : F4 : : : : 2 :
VCCIO2 : F5 : power : : 3.3V : 2 :
GND* : F6 : : : : 2 :
GND* : F7 : : : : 2 :
GNDA_PLL3 : F8 : gnd : : : :
GND* : F9 : : : : 3 :
GND* : F10 : : : : 3 :
GND* : F11 : : : : 3 :
GND* : F12 : : : : 3 :
GND* : F13 : : : : 4 :
GND* : F14 : : : : 4 :
GND* : F15 : : : : 4 :
GND* : F16 : : : : 4 :
GND* : F17 : : : : 4 :
GND* : F18 : : : : 4 :
GNDA_PLL2 : F19 : gnd : : : :
GND* : F20 : : : : 5 :
GND* : F21 : : : : 5 :
VCCIO5 : F22 : power : : 3.3V : 5 :
GND* : F23 : : : : 5 :
GND* : F24 : : : : 5 :
GND* : F25 : : : : 5 :
GND* : F26 : : : : 5 :
GND* : G1 : : : : 2 :
GND* : G2 : : : : 2 :
GND* : G3 : : : : 2 :
GND* : G4 : : : : 2 :
GND* : G5 : : : : 2 :
GND* : G6 : : : : 2 :
GND_PLL3 : G7 : gnd : : : :
VCCA_PLL3 : G8 : power : : 1.2V : :
GND* : G9 : : : : 3 :
GND* : G10 : : : : 3 :
GND* : G11 : : : : 3 :
GND* : G12 : : : : 3 :
GND* : G13 : : : : 4 :
GND* : G14 : : : : 4 :
GND* : G15 : : : : 4 :
GND* : G16 : : : : 4 :
GND* : G17 : : : : 4 :
GND* : G18 : : : : 4 :
VCCA_PLL2 : G19 : power : : 1.2V : :
GND_PLL2 : G20 : gnd : : : :
GND* : G21 : : : : 5 :
GND* : G22 : : : : 5 :
GND* : G23 : : : : 5 :
GND* : G24 : : : : 5 :
GND* : G25 : : : : 5 :
GND* : G26 : : : : 5 :
GND* : H1 : : : : 2 :
GND* : H2 : : : : 2 :
GND* : H3 : : : : 2 :
GND* : H4 : : : : 2 :
GND : H5 : gnd : : : :
GND* : H6 : : : : 2 :
VCCD_PLL3 : H7 : power : : 1.2V : :
GND* : H8 : : : : 3 :
VCCIO3 : H9 : power : : 3.3V : 3 :
GND* : H10 : : : : 3 :
GND* : H11 : : : : 3 :
GND* : H12 : : : : 3 :
GND : H13 : gnd : : : :
GND : H14 : gnd : : : :
GND* : H15 : : : : 4 :
GND* : H16 : : : : 4 :
GND* : H17 : : : : 4 :
VCCIO4 : H18 : power : : 3.3V : 4 :
GND* : H19 : : : : 5 :
VCCD_PLL2 : H20 : power : : 1.2V : :
GND* : H21 : : : : 5 :
GND : H22 : gnd : : : :
GND* : H23 : : : : 5 :
GND* : H24 : : : : 5 :
GND* : H25 : : : : 5 :
GND* : H26 : : : : 5 :
GND* : J1 : : : : 2 :
GND* : J2 : : : : 2 :
GND* : J3 : : : : 2 :
GND* : J4 : : : : 2 :
GND* : J5 : : : : 2 :
GND* : J6 : : : : 2 :
GND* : J7 : : : : 2 :
GND* : J8 : : : : 2 :
GND* : J9 : : : : 3 :
GND* : J10 : : : : 3 :
GND* : J11 : : : : 3 :
VCCIO3 : J12 : power : : 3.3V : 3 :
GND* : J13 : : : : 3 :
GND* : J14 : : : : 3 :
VCCIO4 : J15 : power : : 3.3V : 4 :
GND* : J16 : : : : 4 :
GND* : J17 : : : : 4 :
GND* : J18 : : : : 4 :
VCCIO5 : J19 : power : : 3.3V : 5 :
GND* : J20 : : : : 5 :
GND* : J21 : : : : 5 :
GND* : J22 : : : : 5 :
GND* : J23 : : : : 5 :
GND* : J24 : : : : 5 :
GND* : J25 : : : : 5 :
GND* : J26 : : : : 5 :
GND* : K1 : : : : 2 :
GND* : K2 : : : : 2 :
GND* : K3 : : : : 2 :
GND* : K4 : : : : 2 :
GND* : K5 : : : : 2 :
GND* : K6 : : : : 2 :
GND* : K7 : : : : 2 :
GND* : K8 : : : : 2 :
GND* : K9 : : : : 3 :
VCCINT : K10 : power : : 1.2V : :
VCCINT : K11 : power : : 1.2V : :
VCCINT : K12 : power : : 1.2V : :
VCCINT : K13 : power : : 1.2V : :
VCCINT : K14 : power : : 1.2V : :
VCCINT : K15 : power : : 1.2V : :
GND* : K16 : : : : 4 :
GND* : K17 : : : : 4 :
GND* : K18 : : : : 5 :
GND* : K19 : : : : 5 :
GND : K20 : gnd : : : :
GND* : K21 : : : : 5 :
GND* : K22 : : : : 5 :
GND* : K23 : : : : 5 :
GND* : K24 : : : : 5 :
GND* : K25 : : : : 5 :
GND* : K26 : : : : 5 :
VCCIO2 : L1 : power : : 3.3V : 2 :
GND* : L2 : : : : 2 :
GND* : L3 : : : : 2 :
GND* : L4 : : : : 2 :
GND : L5 : gnd : : : :
GND* : L6 : : : : 2 :
GND* : L7 : : : : 2 :
TMS : L8 : input : : : 2 :
GND* : L9 : : : : 2 :
GND* : L10 : : : : 2 :
VCCINT : L11 : power : : 1.2V : :
GND : L12 : gnd : : : :
GND : L13 : gnd : : : :
GND : L14 : gnd : : : :
GND : L15 : gnd : : : :
VCCINT : L16 : power : : 1.2V : :
VCCINT : L17 : power : : 1.2V : :
VCCINT : L18 : power : : 1.2V : :
GND* : L19 : : : : 5 :
GND* : L20 : : : : 5 :
GND* : L21 : : : : 5 :
GND : L22 : gnd : : : :
GND* : L23 : : : : 5 :
GND* : L24 : : : : 5 :
GND* : L25 : : : : 5 :
VCCIO5 : L26 : power : : 3.3V : 5 :
GND : M1 : gnd : : : :
GND* : M2 : : : : 2 :
GND* : M3 : : : : 2 :
GND* : M4 : : : : 2 :
GND* : M5 : : : : 2 :
TCK : M6 : input : : : 2 :
TDO : M7 : output : : : 2 :
TDI : M8 : input : : : 2 :
VCCIO2 : M9 : power : : 3.3V : 2 :
VCCINT : M10 : power : : 1.2V : :
VCCINT : M11 : power : : 1.2V : :
GND : M12 : gnd : : : :
GND : M13 : gnd : : : :
GND : M14 : gnd : : : :
GND : M15 : gnd : : : :
VCCINT : M16 : power : : 1.2V : :
VCCINT : M17 : power : : 1.2V : :
VCCIO5 : M18 : power : : 3.3V : 5 :
GND* : M19 : : : : 5 :
GND* : M20 : : : : 5 :
GND* : M21 : : : : 5 :
GND* : M22 : : : : 5 :
GND* : M23 : : : : 5 :
GND* : M24 : : : : 5 :
GND* : M25 : : : : 5 :
GND : M26 : gnd : : : :
GND+ : N1 : : : : 2 :
GND+ : N2 : : : : 2 :
DATA0 : N3 : input : : : 2 :
nCE : N4 : : : : 2 :
VCCIO2 : N5 : power : : 3.3V : 2 :
DCLK : N6 : : : : 2 :
nCONFIG : N7 : : : : 2 :
GND : N8 : gnd : : : :
GND* : N9 : : : : 2 :
VCCINT : N10 : power : : 1.2V : :
GND : N11 : gnd : : : :
GND : N12 : gnd : : : :
GND : N13 : gnd : : : :
GND : N14 : gnd : : : :
GND : N15 : gnd : : : :
GND : N16 : gnd : : : :
VCCINT : N17 : power : : 1.2V : :
GND* : N18 : : : : 5 :
GND : N19 : gnd : : : :
GND* : N20 : : : : 5 :
NC : N21 : : : : :
VCCIO5 : N22 : power : : 3.3V : 5 :
GND* : N23 : : : : 5 :
GND* : N24 : : : : 5 :
GND+ : N25 : : : : 5 :
GND+ : N26 : : : : 5 :
GND+ : P1 : : : : 1 :
GND+ : P2 : : : : 1 :
GND* : P3 : : : : 1 :
GND* : P4 : : : : 1 :
VCCIO1 : P5 : power : : 3.3V : 1 :
GND* : P6 : : : : 1 :
GND* : P7 : : : : 1 :
GND : P8 : gnd : : : :
GND* : P9 : : : : 2 :
VCCINT : P10 : power : : 1.2V : :
GND : P11 : gnd : : : :
GND : P12 : gnd : : : :
GND : P13 : gnd : : : :
GND : P14 : gnd : : : :
GND : P15 : gnd : : : :
GND : P16 : gnd : : : :
GND* : P17 : : : : 6 :
GND* : P18 : : : : 5 :
GND : P19 : gnd : : : :
MSEL0 : P20 : : : : 6 :
MSEL1 : P21 : : : : 6 :
VCCIO6 : P22 : power : : 3.3V : 6 :
GND* : P23 : : : : 6 :
GND* : P24 : : : : 6 :
GND+ : P25 : : : : 6 :
GND+ : P26 : : : : 6 :
GND : R1 : gnd : : : :
GND* : R2 : : : : 1 :
GND* : R3 : : : : 1 :
GND* : R4 : : : : 1 :
GND* : R5 : : : : 1 :
GND* : R6 : : : : 1 :
GND* : R7 : : : : 1 :
GND* : R8 : : : : 1 :
VCCIO1 : R9 : power : : 3.3V : 1 :
VCCINT : R10 : power : : 1.2V : :
VCCINT : R11 : power : : 1.2V : :
GND : R12 : gnd : : : :
GND : R13 : gnd : : : :
GND : R14 : gnd : : : :
GND : R15 : gnd : : : :
VCCINT : R16 : power : : 1.2V : :
GND* : R17 : : : : 6 :
VCCIO6 : R18 : power : : 3.3V : 6 :
GND* : R19 : : : : 6 :
GND* : R20 : : : : 6 :
GND : R21 : gnd : : : :
nSTATUS : R22 : : : : 6 :
CONF_DONE : R23 : : : : 6 :
GND* : R24 : : : : 6 :
GND* : R25 : : : : 6 :
GND : R26 : gnd : : : :
VCCIO1 : T1 : power : : 3.3V : 1 :
GND* : T2 : : : : 1 :
GND* : T3 : : : : 1 :
GND* : T4 : : : : 1 :
GND : T5 : gnd : : : :
GND* : T6 : : : : 1 :
GND* : T7 : : : : 1 :
GND* : T8 : : : : 1 :
GND* : T9 : : : : 1 :
GND* : T10 : : : : 1 :
VCCINT : T11 : power : : 1.2V : :
GND : T12 : gnd : : : :
GND : T13 : gnd : : : :
GND : T14 : gnd : : : :
GND : T15 : gnd : : : :
VCCINT : T16 : power : : 1.2V : :
GND* : T17 : : : : 6 :
GND* : T18 : : : : 6 :
GND* : T19 : : : : 6 :
GND* : T20 : : : : 6 :
GND* : T21 : : : : 6 :
GND* : T22 : : : : 6 :
GND* : T23 : : : : 6 :
GND* : T24 : : : : 6 :
GND* : T25 : : : : 6 :
VCCIO6 : T26 : power : : 3.3V : 6 :
GND* : U1 : : : : 1 :
GND* : U2 : : : : 1 :
GND* : U3 : : : : 1 :
GND* : U4 : : : : 1 :
GND* : U5 : : : : 1 :
GND* : U6 : : : : 1 :
GND* : U7 : : : : 1 :
GND : U8 : gnd : : : :
GND* : U9 : : : : 1 :
GND* : U10 : : : : 1 :
VCCINT : U11 : power : : 1.2V : :
GND* : U12 : : : : 8 :
VCCINT : U13 : power : : 1.2V : :
VCCINT : U14 : power : : 1.2V : :
VCCINT : U15 : power : : 1.2V : :
VCCINT : U16 : power : : 1.2V : :
GND* : U17 : : : : 7 :
GND* : U18 : : : : 7 :
GND : U19 : gnd : : : :
GND* : U20 : : : : 6 :
GND* : U21 : : : : 6 :
GND* : U22 : : : : 6 :
GND* : U23 : : : : 6 :
GND* : U24 : : : : 6 :
GND* : U25 : : : : 6 :
GND* : U26 : : : : 6 :
GND* : V1 : : : : 1 :
GND* : V2 : : : : 1 :
GND* : V3 : : : : 1 :
GND* : V4 : : : : 1 :
GND* : V5 : : : : 1 :
GND* : V6 : : : : 1 :
GND* : V7 : : : : 1 :
VCCIO1 : V8 : power : : 3.3V : 1 :
GND* : V9 : : : : 8 :
GND* : V10 : : : : 8 :
GND* : V11 : : : : 8 :
VCCIO8 : V12 : power : : 3.3V : 8 :
GND* : V13 : : : : 8 :
GND* : V14 : : : : 8 :
VCCIO7 : V15 : power : : 3.3V : 7 :
VCCINT : V16 : power : : 1.2V : :
GND* : V17 : : : : 7 :
GND* : V18 : : : : 7 :
VCCIO6 : V19 : power : : 3.3V : 6 :
GND* : V20 : : : : 6 :
GND* : V21 : : : : 6 :
GND* : V22 : : : : 6 :
GND* : V23 : : : : 6 :
GND* : V24 : : : : 6 :
GND* : V25 : : : : 6 :
GND* : V26 : : : : 6 :
GND* : W1 : : : : 1 :
GND* : W2 : : : : 1 :
GND* : W3 : : : : 1 :
GND* : W4 : : : : 1 :
GND : W5 : gnd : : : :
GND* : W6 : : : : 1 :
GND_PLL1 : W7 : gnd : : : :
GND* : W8 : : : : 8 :
VCCIO8 : W9 : power : : 3.3V : 8 :
GND* : W10 : : : : 8 :
GND* : W11 : : : : 8 :
GND* : W12 : : : : 8 :
GND : W13 : gnd : : : :
GND : W14 : gnd : : : :
GND* : W15 : : : : 7 :
GND* : W16 : : : : 7 :
GND* : W17 : : : : 7 :
VCCIO7 : W18 : power : : 3.3V : 7 :
GND* : W19 : : : : 7 :
GND_PLL4 : W20 : gnd : : : :
GND* : W21 : : : : 6 :
GND : W22 : gnd : : : :
GND* : W23 : : : : 6 :
GND* : W24 : : : : 6 :
GND* : W25 : : : : 6 :
GND* : W26 : : : : 6 :
GND* : Y1 : : : : 1 :
NC : Y2 : : : : :
GND* : Y3 : : : : 1 :
GND* : Y4 : : : : 1 :
GND* : Y5 : : : : 1 :
GND_PLL1 : Y6 : gnd : : : :
VCCD_PLL1 : Y7 : power : : 1.2V : :
GNDA_PLL1 : Y8 : gnd : : : :
GND : Y9 : gnd : : : :
GND* : Y10 : : : : 8 :
GND* : Y11 : : : : 8 :
GND* : Y12 : : : : 8 :
GND* : Y13 : : : : 7 :
GND* : Y14 : : : : 7 :
GND* : Y15 : : : : 7 :
GND* : Y16 : : : : 7 :
GND : Y17 : gnd : : : :
GND* : Y18 : : : : 7 :
GNDA_PLL4 : Y19 : gnd : : : :
VCCD_PLL4 : Y20 : power : : 1.2V : :
GND* : Y21 : : : : 6 :
GND* : Y22 : : : : 6 :
GND* : Y23 : : : : 6 :
GND* : Y24 : : : : 6 :
GND* : Y25 : : : : 6 :
GND* : Y26 : : : : 6 :

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TimeQuest Timing Analyzer report for d_ff
Thu Feb 08 22:32:59 2024
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Slow Model Fmax Summary
6. Slow Model Setup Summary
7. Slow Model Hold Summary
8. Slow Model Recovery Summary
9. Slow Model Removal Summary
10. Slow Model Minimum Pulse Width Summary
11. Slow Model Minimum Pulse Width: 'CLK'
12. Setup Times
13. Hold Times
14. Clock to Output Times
15. Minimum Clock to Output Times
16. Fast Model Setup Summary
17. Fast Model Hold Summary
18. Fast Model Recovery Summary
19. Fast Model Removal Summary
20. Fast Model Minimum Pulse Width Summary
21. Fast Model Minimum Pulse Width: 'CLK'
22. Setup Times
23. Hold Times
24. Clock to Output Times
25. Minimum Clock to Output Times
26. Multicorner Timing Analysis Summary
27. Setup Times
28. Hold Times
29. Clock to Output Times
30. Minimum Clock to Output Times
31. Clock Transfers
32. Report TCCS
33. Report RSKM
34. Unconstrained Paths
35. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name ; d_ff ;
; Device Family ; Cyclone II ;
; Device Name ; EP2C35F672C6 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Unavailable ;
+--------------------+-------------------------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 12 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; CLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { CLK } ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
---------------------------
; Slow Model Fmax Summary ;
---------------------------
No paths to report.
----------------------------
; Slow Model Setup Summary ;
----------------------------
No paths to report.
---------------------------
; Slow Model Hold Summary ;
---------------------------
No paths to report.
-------------------------------
; Slow Model Recovery Summary ;
-------------------------------
No paths to report.
------------------------------
; Slow Model Removal Summary ;
------------------------------
No paths to report.
+----------------------------------------+
; Slow Model Minimum Pulse Width Summary ;
+-------+--------+-----------------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+-----------------------+
; CLK ; -1.380 ; -2.380 ;
+-------+--------+-----------------------+
+----------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CLK' ;
+--------+--------------+----------------+------------------+-------+------------+-------------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+------------------+-------+------------+-------------+
; -1.380 ; 1.000 ; 2.380 ; Port Rate ; CLK ; Rise ; CLK ;
; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; CLK ; Rise ; Q~reg0 ;
; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; CLK ; Rise ; Q~reg0 ;
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; CLK ; Rise ; CLK|combout ;
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; CLK|combout ;
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; CLK ; Rise ; Q~reg0|clk ;
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; Q~reg0|clk ;
+--------+--------------+----------------+------------------+-------+------------+-------------+
+-------------------------------------------------------------------------+
; Setup Times ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; D ; CLK ; -0.324 ; -0.324 ; Rise ; CLK ;
+-----------+------------+--------+--------+------------+-----------------+
+-----------------------------------------------------------------------+
; Hold Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; D ; CLK ; 0.554 ; 0.554 ; Rise ; CLK ;
+-----------+------------+-------+-------+------------+-----------------+
+-----------------------------------------------------------------------+
; Clock to Output Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; Q ; CLK ; 5.792 ; 5.792 ; Rise ; CLK ;
; Qn ; CLK ; 5.792 ; 5.792 ; Rise ; CLK ;
+-----------+------------+-------+-------+------------+-----------------+
+-----------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; Q ; CLK ; 5.792 ; 5.792 ; Rise ; CLK ;
; Qn ; CLK ; 5.792 ; 5.792 ; Rise ; CLK ;
+-----------+------------+-------+-------+------------+-----------------+
----------------------------
; Fast Model Setup Summary ;
----------------------------
No paths to report.
---------------------------
; Fast Model Hold Summary ;
---------------------------
No paths to report.
-------------------------------
; Fast Model Recovery Summary ;
-------------------------------
No paths to report.
------------------------------
; Fast Model Removal Summary ;
------------------------------
No paths to report.
+----------------------------------------+
; Fast Model Minimum Pulse Width Summary ;
+-------+--------+-----------------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+-----------------------+
; CLK ; -1.380 ; -2.380 ;
+-------+--------+-----------------------+
+----------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CLK' ;
+--------+--------------+----------------+------------------+-------+------------+-------------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+------------------+-------+------------+-------------+
; -1.380 ; 1.000 ; 2.380 ; Port Rate ; CLK ; Rise ; CLK ;
; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; CLK ; Rise ; Q~reg0 ;
; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; CLK ; Rise ; Q~reg0 ;
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; CLK ; Rise ; CLK|combout ;
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; CLK|combout ;
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; CLK ; Rise ; Q~reg0|clk ;
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; CLK ; Rise ; Q~reg0|clk ;
+--------+--------------+----------------+------------------+-------+------------+-------------+
+-------------------------------------------------------------------------+
; Setup Times ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; D ; CLK ; -0.249 ; -0.249 ; Rise ; CLK ;
+-----------+------------+--------+--------+------------+-----------------+
+-----------------------------------------------------------------------+
; Hold Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; D ; CLK ; 0.369 ; 0.369 ; Rise ; CLK ;
+-----------+------------+-------+-------+------------+-----------------+
+-----------------------------------------------------------------------+
; Clock to Output Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; Q ; CLK ; 3.126 ; 3.126 ; Rise ; CLK ;
; Qn ; CLK ; 3.126 ; 3.126 ; Rise ; CLK ;
+-----------+------------+-------+-------+------------+-----------------+
+-----------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; Q ; CLK ; 3.126 ; 3.126 ; Rise ; CLK ;
; Qn ; CLK ; 3.126 ; 3.126 ; Rise ; CLK ;
+-----------+------------+-------+-------+------------+-----------------+
+----------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+------------------+-------+------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+-------+------+----------+---------+---------------------+
; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; -1.380 ;
; CLK ; N/A ; N/A ; N/A ; N/A ; -1.380 ;
; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; -2.38 ;
; CLK ; N/A ; N/A ; N/A ; N/A ; -2.380 ;
+------------------+-------+------+----------+---------+---------------------+
+-------------------------------------------------------------------------+
; Setup Times ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; D ; CLK ; -0.249 ; -0.249 ; Rise ; CLK ;
+-----------+------------+--------+--------+------------+-----------------+
+-----------------------------------------------------------------------+
; Hold Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; D ; CLK ; 0.554 ; 0.554 ; Rise ; CLK ;
+-----------+------------+-------+-------+------------+-----------------+
+-----------------------------------------------------------------------+
; Clock to Output Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; Q ; CLK ; 5.792 ; 5.792 ; Rise ; CLK ;
; Qn ; CLK ; 5.792 ; 5.792 ; Rise ; CLK ;
+-----------+------------+-------+-------+------------+-----------------+
+-----------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; Q ; CLK ; 3.126 ; 3.126 ; Rise ; CLK ;
; Qn ; CLK ; 3.126 ; 3.126 ; Rise ; CLK ;
+-----------+------------+-------+-------+------------+-----------------+
-------------------
; Clock Transfers ;
-------------------
Nothing to report.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 1 ; 1 ;
; Unconstrained Input Port Paths ; 1 ; 1 ;
; Unconstrained Output Ports ; 2 ; 2 ;
; Unconstrained Output Port Paths ; 2 ; 2 ;
+---------------------------------+-------+------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Thu Feb 08 22:32:58 2024
Info: Command: quartus_sta d_ff -c d_ff
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'd_ff.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
Info (332105): create_clock -period 1.000 -name CLK CLK
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow Model
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case minimum pulse width slack is -1.380
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): -1.380 -2.380 CLK
Info (332001): The selected device family is not supported by the report_metastability command.
Info: Analyzing Fast Model
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case minimum pulse width slack is -1.380
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): -1.380 -2.380 CLK
Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 4540 megabytes
Info: Processing ended: Thu Feb 08 22:32:59 2024
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

13
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------------------------------------------------------------
TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Slow Model Minimum Pulse Width 'CLK'
Slack : -1.380
TNS : -2.380
Type : Fast Model Minimum Pulse Width 'CLK'
Slack : -1.380
TNS : -2.380
------------------------------------------------------------

324
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; Copyright 1991-2009 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
[Library]
others = $MODEL_TECH/../modelsim.ini
; Altera Primitive libraries
;
; VHDL Section
;
;
; Verilog Section
;
work = work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
; Default or value of 3 or 2008 for VHDL-2008.
VHDL93 = 2002
; Show source line containing error. Default is off.
; Show_source = 1
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
; Turn on incremental compilation of modules. Default is off.
; Incremental = 1
; Turns on lint-style checking.
; Show_Lint = 1
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ps
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
; Default run length
RunLength = 100
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
; Directive to license manager:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license isn't available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license
; License = plus
; Stop the simulator after a VHDL/Verilog assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
; Assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
; AssertFile = assert.log
; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
; VSIM Startup command
; Startup = do startup.do
; File for saving command transcript
TranscriptFile = transcript
; File for saving command history
; CommandHistory = cmdhist.log
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type). Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave
; DefaultRestartOptions = -force
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
; Automatic SDF compilation
; Disables automatic compilation of SDF files in flows that support it.
; Default is on, uncomment to turn off.
; NoAutoSDFCompile = 1
[lmc]
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.
; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer). The other settings
; are to send messages only to the transcript or only to the
; wlf file. The valid values are
; both {default}
; tran {transcript only}
; wlf {wlf file only}
; msgmode = both

20
labor_1/d_ff/sim/sim.tcl Normal file
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#remove working directory
file delete -force work
#Creating the work lib
vlib work
vmap work work
#Top level testbench
vlog tb_d_ff.v
#Compile DUT
vlog ../src/d_ff.v
#Simulate
vsim -c -t ps tb_d_ff
#get wave
do wave.tcl
run 100 ns

48
labor_1/d_ff/sim/tb_d_ff.v Normal file
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// Testbench fuer D-FlipFlop. Dieses module erzeugt Signale, mit denen das D-FF geprüft wird.
`timescale 1ns/1ps //Anweisung für den Simulator: Ein Zeitschritt ist 1ns lang. es soll mit einer
//Genauigkeit von 1ps simuliert werden.
module tb_d_ff; //Dies ist das sogenannte top-level module, das direkt vom Simulator ausgeführt wird.
//Daher hat es keine Ein- oder Ausgänge.
reg CLK_50_TB; //50 MHz Taktsignal
reg DATA_TB; //Datensignal
wire Q_TB; //Nichtinvertierender Ausgang
assign Qn_TB = ~Q_TB;
//wire Qn_TB; //Invertierender Ausgang
//Initialisierung der regs
initial //Der Initialblock startet einmal beim Beginn der Simulation
begin
CLK_50_TB = 1'b0; //Die Signale, die die Testbech erzeugt, werden initialisiert
DATA_TB = 1'b0;
//Erzeugung der Signalfolge für DATA_TB
#15 DATA_TB = 1'b1; //15 Zeiteinheiten nach Simulationsbeginn wird DATA_TB 1
#20 DATA_TB = 1'b0; //20 Simulationseinheiten später wird DATA_TB wieder 0
#17 DATA_TB = ~DATA_TB; //Weitere 17 Zeiteinheiten später wird DATA_TB invertiert.
#3 DATA_TB = 1'b0;
#3 DATA_TB = 1'b1;
#3 DATA_TB = 1'b0;
#3 DATA_TB = 1'b1;
#3 DATA_TB = 1'b0;
#3 DATA_TB = 1'b1;
#10 DATA_TB = 1'b0;
end
//Alwaysblock zum erzeugen des Taktsignals
always
begin
CLK_50_TB = ~CLK_50_TB;
#10; // Zeiteinheiten Verzögerung -> 20ns Periode -> 50 MHz Taktfrequenz
end
//Instanzierung des modules d_ff unter dem Namen d_ff_test
d_ff d_ff_test(
.D(DATA_TB),
.CLK(CLK_50_TB),
.Q(Q_TB),
.Qn(Qn_TB));
endmodule //testbench

BIN
labor_1/d_ff/sim/vsim.wlf Normal file
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24
labor_1/d_ff/sim/wave.tcl Normal file
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /tb_d_ff/CLK_50_TB
add wave -noupdate /tb_d_ff/DATA_TB
add wave -noupdate /tb_d_ff/Q_TB
add wave -noupdate /tb_d_ff/Qn_TB
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {49842 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {128 ns}

43
labor_1/d_ff/sim/work/_info Normal file
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m255
K3
13
cModel Technology
Z0 dC:\Users\Musab Erdem\Nextcloud\Dokumente\Studium\DHBW\Semester 4\Labor_EDS\Uebungen\d_ff\sim
vd_ff
!i10b 1
!s100 oZ]l01X^hFGzKPH;aK`@D0
I8B?SNQ^=G9?5;5FQ6Mh:[2
VABY;<Ad0?iWMIRAfZmZ3O2
Z1 dC:\Users\Musab Erdem\Nextcloud\Dokumente\Studium\DHBW\Semester 4\Labor_EDS\Uebungen\d_ff\sim
w1707427951
8../src/d_ff.v
F../src/d_ff.v
L0 1
Z2 OV;L;10.1d;51
r1
!s85 0
31
!s108 1707427957.947000
!s107 ../src/d_ff.v|
!s90 -reportprogress|300|../src/d_ff.v|
!s101 -O0
o-O0
vtb_d_ff
Z3 I8IJoKf=QSj]g6^bXGZD:72
Z4 V5YY7Djb3980=@9?5^H^bR2
R1
Z5 w1707395424
Z6 8tb_d_ff.v
Z7 Ftb_d_ff.v
L0 5
R2
r1
31
o-O0
!i10b 1
Z8 !s100 TBE=QSe;Im^<=L?C2OVY11
!s85 0
Z9 !s108 1707427957.891000
Z10 !s107 tb_d_ff.v|
Z11 !s90 -reportprogress|300|tb_d_ff.v|
!s101 -O0

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