Hochladen der vorherigen Laborübungen.

Die Dateien selbst wurden nicht verändert.

labor_2/aufwaertszaehler/sim/work/_info

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+m255
+K3
+13
+cModel Technology
+Z0 dC:\Users\Musab Erdem\Nextcloud\Dokumente\Studium\DHBW\Semester 4\Labor_EDS\Vorbereitung\4_Getraenkeautomat\aufwaertszaehler\sim
+vn_bit_counter
+!i10b 1
+!s100 7QPmi8gB:5XM`@G_^Y^UN2
+Iibfh1[JFT1R`eQZM`El:P1
+VoHO280_3HC[07hjL6?djI0
+Z1 dC:\Users\Musab Erdem\Nextcloud\Dokumente\Studium\DHBW\Semester 4\Labor_EDS\Vorbereitung\4_Getraenkeautomat\aufwaertszaehler\sim
+w1707967466
+8../src/n_bit_counter.v
+F../src/n_bit_counter.v
+L0 2
+Z2 OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1707967480.131000
+!s107 ../src/n_bit_counter.v|
+!s90 -reportprogress|300|../src/n_bit_counter.v|
+!s101 -O0
+o-O0
+vtb_n_bit_counter
+Z3 IPR4DYFS6VoIFF:Vk[BO813
+Z4 V?Z`X[2[ZbBLQ9:^Xg2d6O1
+R1
+Z5 w1707967478
+Z6 8tb_n_bit_counter.v
+Z7 Ftb_n_bit_counter.v
+L0 5
+R2
+r1
+31
+o-O0
+!i10b 1
+Z8 !s100 B6nQ1S6371jU9``Z@kBhX3
+!s85 0
+Z9 !s108 1707967480.065000
+Z10 !s107 tb_n_bit_counter.v|
+Z11 !s90 -reportprogress|300|tb_n_bit_counter.v|
+!s101 -O0

labor_2/aufwaertszaehler/sim/work/_vmake

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+m255
+K3
+cModel Technology

labor_2/aufwaertszaehler/sim/work/n_bit_counter/_primary.vhd

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+library verilog;
+use verilog.vl_types.all;
+entity n_bit_counter is
+    generic(
+        terminalCount   : integer := 5
+    );
+    port(
+        CLK             : in     vl_logic;
+        CLK_EN          : in     vl_logic;
+        RST             : in     vl_logic;
+        Q               : out    vl_logic_vector;
+        TC              : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of terminalCount : constant is 1;
+end n_bit_counter;

labor_2/aufwaertszaehler/sim/work/tb_n_bit_counter/_primary.vhd

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+library verilog;
+use verilog.vl_types.all;
+entity tb_n_bit_counter is
+end tb_n_bit_counter;