Hochladen der vorherigen Laborübungen.
Die Dateien selbst wurden nicht verändert.
This commit is contained in:
@@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 13:26:59 February 15, 2024
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.0"
|
||||
DATE = "13:26:59 February 15, 2024"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "counters_leds"
|
||||
@@ -0,0 +1,486 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 13:26:59 February 15, 2024
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# counters_leds_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone II"
|
||||
set_global_assignment -name DEVICE EP2C35F672C6
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY counters_leds
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:26:59 FEBRUARY 15, 2024"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name VERILOG_FILE ../src/mod_n_counter_10bit.v
|
||||
set_global_assignment -name VERILOG_FILE ../src/d_ff.v
|
||||
set_global_assignment -name VERILOG_FILE ../src/counters_leds.v
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_location_assignment PIN_N25 -to SW[0]
|
||||
set_location_assignment PIN_N26 -to SW[1]
|
||||
set_location_assignment PIN_P25 -to SW[2]
|
||||
set_location_assignment PIN_AE14 -to SW[3]
|
||||
set_location_assignment PIN_AF14 -to SW[4]
|
||||
set_location_assignment PIN_AD13 -to SW[5]
|
||||
set_location_assignment PIN_AC13 -to SW[6]
|
||||
set_location_assignment PIN_C13 -to SW[7]
|
||||
set_location_assignment PIN_B13 -to SW[8]
|
||||
set_location_assignment PIN_A13 -to SW[9]
|
||||
set_location_assignment PIN_N1 -to SW[10]
|
||||
set_location_assignment PIN_P1 -to SW[11]
|
||||
set_location_assignment PIN_P2 -to SW[12]
|
||||
set_location_assignment PIN_T7 -to SW[13]
|
||||
set_location_assignment PIN_U3 -to SW[14]
|
||||
set_location_assignment PIN_U4 -to SW[15]
|
||||
set_location_assignment PIN_V1 -to SW[16]
|
||||
set_location_assignment PIN_V2 -to SW[17]
|
||||
set_location_assignment PIN_T6 -to DRAM_ADDR[0]
|
||||
set_location_assignment PIN_V4 -to DRAM_ADDR[1]
|
||||
set_location_assignment PIN_V3 -to DRAM_ADDR[2]
|
||||
set_location_assignment PIN_W2 -to DRAM_ADDR[3]
|
||||
set_location_assignment PIN_W1 -to DRAM_ADDR[4]
|
||||
set_location_assignment PIN_U6 -to DRAM_ADDR[5]
|
||||
set_location_assignment PIN_U7 -to DRAM_ADDR[6]
|
||||
set_location_assignment PIN_U5 -to DRAM_ADDR[7]
|
||||
set_location_assignment PIN_W4 -to DRAM_ADDR[8]
|
||||
set_location_assignment PIN_W3 -to DRAM_ADDR[9]
|
||||
set_location_assignment PIN_Y1 -to DRAM_ADDR[10]
|
||||
set_location_assignment PIN_V5 -to DRAM_ADDR[11]
|
||||
set_location_assignment PIN_AE2 -to DRAM_BA_0
|
||||
set_location_assignment PIN_AE3 -to DRAM_BA_1
|
||||
set_location_assignment PIN_AB3 -to DRAM_CAS_N
|
||||
set_location_assignment PIN_AA6 -to DRAM_CKE
|
||||
set_location_assignment PIN_AA7 -to DRAM_CLK
|
||||
set_location_assignment PIN_AC3 -to DRAM_CS_N
|
||||
set_location_assignment PIN_V6 -to DRAM_DQ[0]
|
||||
set_location_assignment PIN_AA2 -to DRAM_DQ[1]
|
||||
set_location_assignment PIN_AA1 -to DRAM_DQ[2]
|
||||
set_location_assignment PIN_Y3 -to DRAM_DQ[3]
|
||||
set_location_assignment PIN_Y4 -to DRAM_DQ[4]
|
||||
set_location_assignment PIN_R8 -to DRAM_DQ[5]
|
||||
set_location_assignment PIN_T8 -to DRAM_DQ[6]
|
||||
set_location_assignment PIN_V7 -to DRAM_DQ[7]
|
||||
set_location_assignment PIN_W6 -to DRAM_DQ[8]
|
||||
set_location_assignment PIN_AB2 -to DRAM_DQ[9]
|
||||
set_location_assignment PIN_AB1 -to DRAM_DQ[10]
|
||||
set_location_assignment PIN_AA4 -to DRAM_DQ[11]
|
||||
set_location_assignment PIN_AA3 -to DRAM_DQ[12]
|
||||
set_location_assignment PIN_AC2 -to DRAM_DQ[13]
|
||||
set_location_assignment PIN_AC1 -to DRAM_DQ[14]
|
||||
set_location_assignment PIN_AA5 -to DRAM_DQ[15]
|
||||
set_location_assignment PIN_AD2 -to DRAM_LDQM
|
||||
set_location_assignment PIN_Y5 -to DRAM_UDQM
|
||||
set_location_assignment PIN_AB4 -to DRAM_RAS_N
|
||||
set_location_assignment PIN_AD3 -to DRAM_WE_N
|
||||
set_location_assignment PIN_AC18 -to FL_ADDR[0]
|
||||
set_location_assignment PIN_AB18 -to FL_ADDR[1]
|
||||
set_location_assignment PIN_AE19 -to FL_ADDR[2]
|
||||
set_location_assignment PIN_AF19 -to FL_ADDR[3]
|
||||
set_location_assignment PIN_AE18 -to FL_ADDR[4]
|
||||
set_location_assignment PIN_AF18 -to FL_ADDR[5]
|
||||
set_location_assignment PIN_Y16 -to FL_ADDR[6]
|
||||
set_location_assignment PIN_AA16 -to FL_ADDR[7]
|
||||
set_location_assignment PIN_AD17 -to FL_ADDR[8]
|
||||
set_location_assignment PIN_AC17 -to FL_ADDR[9]
|
||||
set_location_assignment PIN_AE17 -to FL_ADDR[10]
|
||||
set_location_assignment PIN_AF17 -to FL_ADDR[11]
|
||||
set_location_assignment PIN_W16 -to FL_ADDR[12]
|
||||
set_location_assignment PIN_W15 -to FL_ADDR[13]
|
||||
set_location_assignment PIN_AC16 -to FL_ADDR[14]
|
||||
set_location_assignment PIN_AD16 -to FL_ADDR[15]
|
||||
set_location_assignment PIN_AE16 -to FL_ADDR[16]
|
||||
set_location_assignment PIN_AC15 -to FL_ADDR[17]
|
||||
set_location_assignment PIN_AB15 -to FL_ADDR[18]
|
||||
set_location_assignment PIN_AA15 -to FL_ADDR[19]
|
||||
set_location_assignment PIN_Y15 -to FL_ADDR[20]
|
||||
set_location_assignment PIN_Y14 -to FL_ADDR[21]
|
||||
set_location_assignment PIN_V17 -to FL_CE_N
|
||||
set_location_assignment PIN_W17 -to FL_OE_N
|
||||
set_location_assignment PIN_AD19 -to FL_DQ[0]
|
||||
set_location_assignment PIN_AC19 -to FL_DQ[1]
|
||||
set_location_assignment PIN_AF20 -to FL_DQ[2]
|
||||
set_location_assignment PIN_AE20 -to FL_DQ[3]
|
||||
set_location_assignment PIN_AB20 -to FL_DQ[4]
|
||||
set_location_assignment PIN_AC20 -to FL_DQ[5]
|
||||
set_location_assignment PIN_AF21 -to FL_DQ[6]
|
||||
set_location_assignment PIN_AE21 -to FL_DQ[7]
|
||||
set_location_assignment PIN_AA18 -to FL_RST_N
|
||||
set_location_assignment PIN_AA17 -to FL_WE_N
|
||||
set_location_assignment PIN_AF10 -to HEX0[0]
|
||||
set_location_assignment PIN_AB12 -to HEX0[1]
|
||||
set_location_assignment PIN_AC12 -to HEX0[2]
|
||||
set_location_assignment PIN_AD11 -to HEX0[3]
|
||||
set_location_assignment PIN_AE11 -to HEX0[4]
|
||||
set_location_assignment PIN_V14 -to HEX0[5]
|
||||
set_location_assignment PIN_V13 -to HEX0[6]
|
||||
set_location_assignment PIN_V20 -to HEX1[0]
|
||||
set_location_assignment PIN_V21 -to HEX1[1]
|
||||
set_location_assignment PIN_W21 -to HEX1[2]
|
||||
set_location_assignment PIN_Y22 -to HEX1[3]
|
||||
set_location_assignment PIN_AA24 -to HEX1[4]
|
||||
set_location_assignment PIN_AA23 -to HEX1[5]
|
||||
set_location_assignment PIN_AB24 -to HEX1[6]
|
||||
set_location_assignment PIN_AB23 -to HEX2[0]
|
||||
set_location_assignment PIN_V22 -to HEX2[1]
|
||||
set_location_assignment PIN_AC25 -to HEX2[2]
|
||||
set_location_assignment PIN_AC26 -to HEX2[3]
|
||||
set_location_assignment PIN_AB26 -to HEX2[4]
|
||||
set_location_assignment PIN_AB25 -to HEX2[5]
|
||||
set_location_assignment PIN_Y24 -to HEX2[6]
|
||||
set_location_assignment PIN_Y23 -to HEX3[0]
|
||||
set_location_assignment PIN_AA25 -to HEX3[1]
|
||||
set_location_assignment PIN_AA26 -to HEX3[2]
|
||||
set_location_assignment PIN_Y26 -to HEX3[3]
|
||||
set_location_assignment PIN_Y25 -to HEX3[4]
|
||||
set_location_assignment PIN_U22 -to HEX3[5]
|
||||
set_location_assignment PIN_W24 -to HEX3[6]
|
||||
set_location_assignment PIN_U9 -to HEX4[0]
|
||||
set_location_assignment PIN_U1 -to HEX4[1]
|
||||
set_location_assignment PIN_U2 -to HEX4[2]
|
||||
set_location_assignment PIN_T4 -to HEX4[3]
|
||||
set_location_assignment PIN_R7 -to HEX4[4]
|
||||
set_location_assignment PIN_R6 -to HEX4[5]
|
||||
set_location_assignment PIN_T3 -to HEX4[6]
|
||||
set_location_assignment PIN_T2 -to HEX5[0]
|
||||
set_location_assignment PIN_P6 -to HEX5[1]
|
||||
set_location_assignment PIN_P7 -to HEX5[2]
|
||||
set_location_assignment PIN_T9 -to HEX5[3]
|
||||
set_location_assignment PIN_R5 -to HEX5[4]
|
||||
set_location_assignment PIN_R4 -to HEX5[5]
|
||||
set_location_assignment PIN_R3 -to HEX5[6]
|
||||
set_location_assignment PIN_R2 -to HEX6[0]
|
||||
set_location_assignment PIN_P4 -to HEX6[1]
|
||||
set_location_assignment PIN_P3 -to HEX6[2]
|
||||
set_location_assignment PIN_M2 -to HEX6[3]
|
||||
set_location_assignment PIN_M3 -to HEX6[4]
|
||||
set_location_assignment PIN_M5 -to HEX6[5]
|
||||
set_location_assignment PIN_M4 -to HEX6[6]
|
||||
set_location_assignment PIN_L3 -to HEX7[0]
|
||||
set_location_assignment PIN_L2 -to HEX7[1]
|
||||
set_location_assignment PIN_L9 -to HEX7[2]
|
||||
set_location_assignment PIN_L6 -to HEX7[3]
|
||||
set_location_assignment PIN_L7 -to HEX7[4]
|
||||
set_location_assignment PIN_P9 -to HEX7[5]
|
||||
set_location_assignment PIN_N9 -to HEX7[6]
|
||||
set_location_assignment PIN_G26 -to KEY[0]
|
||||
set_location_assignment PIN_N23 -to KEY[1]
|
||||
set_location_assignment PIN_P23 -to KEY[2]
|
||||
set_location_assignment PIN_W26 -to KEY[3]
|
||||
set_location_assignment PIN_AE23 -to LEDR[0]
|
||||
set_location_assignment PIN_AF23 -to LEDR[1]
|
||||
set_location_assignment PIN_AB21 -to LEDR[2]
|
||||
set_location_assignment PIN_AC22 -to LEDR[3]
|
||||
set_location_assignment PIN_AD22 -to LEDR[4]
|
||||
set_location_assignment PIN_AD23 -to LEDR[5]
|
||||
set_location_assignment PIN_AD21 -to LEDR[6]
|
||||
set_location_assignment PIN_AC21 -to LEDR[7]
|
||||
set_location_assignment PIN_AA14 -to LEDR[8]
|
||||
set_location_assignment PIN_Y13 -to LEDR[9]
|
||||
set_location_assignment PIN_AA13 -to LEDR[10]
|
||||
set_location_assignment PIN_AC14 -to LEDR[11]
|
||||
set_location_assignment PIN_AD15 -to LEDR[12]
|
||||
set_location_assignment PIN_AE15 -to LEDR[13]
|
||||
set_location_assignment PIN_AF13 -to LEDR[14]
|
||||
set_location_assignment PIN_AE13 -to LEDR[15]
|
||||
set_location_assignment PIN_AE12 -to LEDR[16]
|
||||
set_location_assignment PIN_AD12 -to LEDR[17]
|
||||
set_location_assignment PIN_AE22 -to LEDG[0]
|
||||
set_location_assignment PIN_AF22 -to LEDG[1]
|
||||
set_location_assignment PIN_W19 -to LEDG[2]
|
||||
set_location_assignment PIN_V18 -to LEDG[3]
|
||||
set_location_assignment PIN_U18 -to LEDG[4]
|
||||
set_location_assignment PIN_U17 -to LEDG[5]
|
||||
set_location_assignment PIN_AA20 -to LEDG[6]
|
||||
set_location_assignment PIN_Y18 -to LEDG[7]
|
||||
set_location_assignment PIN_Y12 -to LEDG[8]
|
||||
set_location_assignment PIN_D13 -to CLOCK_27
|
||||
set_location_assignment PIN_N2 -to CLOCK_50
|
||||
set_location_assignment PIN_P26 -to EXT_CLOCK
|
||||
set_location_assignment PIN_D26 -to PS2_CLK
|
||||
set_location_assignment PIN_C24 -to PS2_DAT
|
||||
set_location_assignment PIN_C25 -to UART_RXD
|
||||
set_location_assignment PIN_B25 -to UART_TXD
|
||||
set_location_assignment PIN_K4 -to LCD_RW
|
||||
set_location_assignment PIN_K3 -to LCD_EN
|
||||
set_location_assignment PIN_K1 -to LCD_RS
|
||||
set_location_assignment PIN_J1 -to LCD_DATA[0]
|
||||
set_location_assignment PIN_J2 -to LCD_DATA[1]
|
||||
set_location_assignment PIN_H1 -to LCD_DATA[2]
|
||||
set_location_assignment PIN_H2 -to LCD_DATA[3]
|
||||
set_location_assignment PIN_J4 -to LCD_DATA[4]
|
||||
set_location_assignment PIN_J3 -to LCD_DATA[5]
|
||||
set_location_assignment PIN_H4 -to LCD_DATA[6]
|
||||
set_location_assignment PIN_H3 -to LCD_DATA[7]
|
||||
set_location_assignment PIN_L4 -to LCD_ON
|
||||
set_location_assignment PIN_K2 -to LCD_BLON
|
||||
set_location_assignment PIN_AE4 -to SRAM_ADDR[0]
|
||||
set_location_assignment PIN_AF4 -to SRAM_ADDR[1]
|
||||
set_location_assignment PIN_AC5 -to SRAM_ADDR[2]
|
||||
set_location_assignment PIN_AC6 -to SRAM_ADDR[3]
|
||||
set_location_assignment PIN_AD4 -to SRAM_ADDR[4]
|
||||
set_location_assignment PIN_AD5 -to SRAM_ADDR[5]
|
||||
set_location_assignment PIN_AE5 -to SRAM_ADDR[6]
|
||||
set_location_assignment PIN_AF5 -to SRAM_ADDR[7]
|
||||
set_location_assignment PIN_AD6 -to SRAM_ADDR[8]
|
||||
set_location_assignment PIN_AD7 -to SRAM_ADDR[9]
|
||||
set_location_assignment PIN_V10 -to SRAM_ADDR[10]
|
||||
set_location_assignment PIN_V9 -to SRAM_ADDR[11]
|
||||
set_location_assignment PIN_AC7 -to SRAM_ADDR[12]
|
||||
set_location_assignment PIN_W8 -to SRAM_ADDR[13]
|
||||
set_location_assignment PIN_W10 -to SRAM_ADDR[14]
|
||||
set_location_assignment PIN_Y10 -to SRAM_ADDR[15]
|
||||
set_location_assignment PIN_AB8 -to SRAM_ADDR[16]
|
||||
set_location_assignment PIN_AC8 -to SRAM_ADDR[17]
|
||||
set_location_assignment PIN_AD8 -to SRAM_DQ[0]
|
||||
set_location_assignment PIN_AE6 -to SRAM_DQ[1]
|
||||
set_location_assignment PIN_AF6 -to SRAM_DQ[2]
|
||||
set_location_assignment PIN_AA9 -to SRAM_DQ[3]
|
||||
set_location_assignment PIN_AA10 -to SRAM_DQ[4]
|
||||
set_location_assignment PIN_AB10 -to SRAM_DQ[5]
|
||||
set_location_assignment PIN_AA11 -to SRAM_DQ[6]
|
||||
set_location_assignment PIN_Y11 -to SRAM_DQ[7]
|
||||
set_location_assignment PIN_AE7 -to SRAM_DQ[8]
|
||||
set_location_assignment PIN_AF7 -to SRAM_DQ[9]
|
||||
set_location_assignment PIN_AE8 -to SRAM_DQ[10]
|
||||
set_location_assignment PIN_AF8 -to SRAM_DQ[11]
|
||||
set_location_assignment PIN_W11 -to SRAM_DQ[12]
|
||||
set_location_assignment PIN_W12 -to SRAM_DQ[13]
|
||||
set_location_assignment PIN_AC9 -to SRAM_DQ[14]
|
||||
set_location_assignment PIN_AC10 -to SRAM_DQ[15]
|
||||
set_location_assignment PIN_AE10 -to SRAM_WE_N
|
||||
set_location_assignment PIN_AD10 -to SRAM_OE_N
|
||||
set_location_assignment PIN_AF9 -to SRAM_UB_N
|
||||
set_location_assignment PIN_AE9 -to SRAM_LB_N
|
||||
set_location_assignment PIN_AC11 -to SRAM_CE_N
|
||||
set_location_assignment PIN_K7 -to OTG_ADDR[0]
|
||||
set_location_assignment PIN_F2 -to OTG_ADDR[1]
|
||||
set_location_assignment PIN_F1 -to OTG_CS_N
|
||||
set_location_assignment PIN_G2 -to OTG_RD_N
|
||||
set_location_assignment PIN_G1 -to OTG_WR_N
|
||||
set_location_assignment PIN_G5 -to OTG_RST_N
|
||||
set_location_assignment PIN_F4 -to OTG_DATA[0]
|
||||
set_location_assignment PIN_D2 -to OTG_DATA[1]
|
||||
set_location_assignment PIN_D1 -to OTG_DATA[2]
|
||||
set_location_assignment PIN_F7 -to OTG_DATA[3]
|
||||
set_location_assignment PIN_J5 -to OTG_DATA[4]
|
||||
set_location_assignment PIN_J8 -to OTG_DATA[5]
|
||||
set_location_assignment PIN_J7 -to OTG_DATA[6]
|
||||
set_location_assignment PIN_H6 -to OTG_DATA[7]
|
||||
set_location_assignment PIN_E2 -to OTG_DATA[8]
|
||||
set_location_assignment PIN_E1 -to OTG_DATA[9]
|
||||
set_location_assignment PIN_K6 -to OTG_DATA[10]
|
||||
set_location_assignment PIN_K5 -to OTG_DATA[11]
|
||||
set_location_assignment PIN_G4 -to OTG_DATA[12]
|
||||
set_location_assignment PIN_G3 -to OTG_DATA[13]
|
||||
set_location_assignment PIN_J6 -to OTG_DATA[14]
|
||||
set_location_assignment PIN_K8 -to OTG_DATA[15]
|
||||
set_location_assignment PIN_B3 -to OTG_INT0
|
||||
set_location_assignment PIN_C3 -to OTG_INT1
|
||||
set_location_assignment PIN_C2 -to OTG_DACK0_N
|
||||
set_location_assignment PIN_B2 -to OTG_DACK1_N
|
||||
set_location_assignment PIN_F6 -to OTG_DREQ0
|
||||
set_location_assignment PIN_E5 -to OTG_DREQ1
|
||||
set_location_assignment PIN_F3 -to OTG_FSPEED
|
||||
set_location_assignment PIN_G6 -to OTG_LSPEED
|
||||
set_location_assignment PIN_B14 -to TDI
|
||||
set_location_assignment PIN_A14 -to TCS
|
||||
set_location_assignment PIN_D14 -to TCK
|
||||
set_location_assignment PIN_F14 -to TDO
|
||||
set_location_assignment PIN_C4 -to TD_RESET
|
||||
set_location_assignment PIN_C8 -to VGA_R[0]
|
||||
set_location_assignment PIN_F10 -to VGA_R[1]
|
||||
set_location_assignment PIN_G10 -to VGA_R[2]
|
||||
set_location_assignment PIN_D9 -to VGA_R[3]
|
||||
set_location_assignment PIN_C9 -to VGA_R[4]
|
||||
set_location_assignment PIN_A8 -to VGA_R[5]
|
||||
set_location_assignment PIN_H11 -to VGA_R[6]
|
||||
set_location_assignment PIN_H12 -to VGA_R[7]
|
||||
set_location_assignment PIN_F11 -to VGA_R[8]
|
||||
set_location_assignment PIN_E10 -to VGA_R[9]
|
||||
set_location_assignment PIN_B9 -to VGA_G[0]
|
||||
set_location_assignment PIN_A9 -to VGA_G[1]
|
||||
set_location_assignment PIN_C10 -to VGA_G[2]
|
||||
set_location_assignment PIN_D10 -to VGA_G[3]
|
||||
set_location_assignment PIN_B10 -to VGA_G[4]
|
||||
set_location_assignment PIN_A10 -to VGA_G[5]
|
||||
set_location_assignment PIN_G11 -to VGA_G[6]
|
||||
set_location_assignment PIN_D11 -to VGA_G[7]
|
||||
set_location_assignment PIN_E12 -to VGA_G[8]
|
||||
set_location_assignment PIN_D12 -to VGA_G[9]
|
||||
set_location_assignment PIN_J13 -to VGA_B[0]
|
||||
set_location_assignment PIN_J14 -to VGA_B[1]
|
||||
set_location_assignment PIN_F12 -to VGA_B[2]
|
||||
set_location_assignment PIN_G12 -to VGA_B[3]
|
||||
set_location_assignment PIN_J10 -to VGA_B[4]
|
||||
set_location_assignment PIN_J11 -to VGA_B[5]
|
||||
set_location_assignment PIN_C11 -to VGA_B[6]
|
||||
set_location_assignment PIN_B11 -to VGA_B[7]
|
||||
set_location_assignment PIN_C12 -to VGA_B[8]
|
||||
set_location_assignment PIN_B12 -to VGA_B[9]
|
||||
set_location_assignment PIN_B8 -to VGA_CLK
|
||||
set_location_assignment PIN_D6 -to VGA_BLANK
|
||||
set_location_assignment PIN_A7 -to VGA_HS
|
||||
set_location_assignment PIN_D8 -to VGA_VS
|
||||
set_location_assignment PIN_B7 -to VGA_SYNC
|
||||
set_location_assignment PIN_A6 -to I2C_SCLK
|
||||
set_location_assignment PIN_B6 -to I2C_SDAT
|
||||
set_location_assignment PIN_J9 -to TD_DATA[0]
|
||||
set_location_assignment PIN_E8 -to TD_DATA[1]
|
||||
set_location_assignment PIN_H8 -to TD_DATA[2]
|
||||
set_location_assignment PIN_H10 -to TD_DATA[3]
|
||||
set_location_assignment PIN_G9 -to TD_DATA[4]
|
||||
set_location_assignment PIN_F9 -to TD_DATA[5]
|
||||
set_location_assignment PIN_D7 -to TD_DATA[6]
|
||||
set_location_assignment PIN_C7 -to TD_DATA[7]
|
||||
set_location_assignment PIN_D5 -to TD_HS
|
||||
set_location_assignment PIN_K9 -to TD_VS
|
||||
set_location_assignment PIN_C5 -to AUD_ADCLRCK
|
||||
set_location_assignment PIN_B5 -to AUD_ADCDAT
|
||||
set_location_assignment PIN_C6 -to AUD_DACLRCK
|
||||
set_location_assignment PIN_A4 -to AUD_DACDAT
|
||||
set_location_assignment PIN_A5 -to AUD_XCK
|
||||
set_location_assignment PIN_B4 -to AUD_BCLK
|
||||
set_location_assignment PIN_D17 -to ENET_DATA[0]
|
||||
set_location_assignment PIN_C17 -to ENET_DATA[1]
|
||||
set_location_assignment PIN_B18 -to ENET_DATA[2]
|
||||
set_location_assignment PIN_A18 -to ENET_DATA[3]
|
||||
set_location_assignment PIN_B17 -to ENET_DATA[4]
|
||||
set_location_assignment PIN_A17 -to ENET_DATA[5]
|
||||
set_location_assignment PIN_B16 -to ENET_DATA[6]
|
||||
set_location_assignment PIN_B15 -to ENET_DATA[7]
|
||||
set_location_assignment PIN_B20 -to ENET_DATA[8]
|
||||
set_location_assignment PIN_A20 -to ENET_DATA[9]
|
||||
set_location_assignment PIN_C19 -to ENET_DATA[10]
|
||||
set_location_assignment PIN_D19 -to ENET_DATA[11]
|
||||
set_location_assignment PIN_B19 -to ENET_DATA[12]
|
||||
set_location_assignment PIN_A19 -to ENET_DATA[13]
|
||||
set_location_assignment PIN_E18 -to ENET_DATA[14]
|
||||
set_location_assignment PIN_D18 -to ENET_DATA[15]
|
||||
set_location_assignment PIN_B24 -to ENET_CLK
|
||||
set_location_assignment PIN_A21 -to ENET_CMD
|
||||
set_location_assignment PIN_A23 -to ENET_CS_N
|
||||
set_location_assignment PIN_B21 -to ENET_INT
|
||||
set_location_assignment PIN_A22 -to ENET_RD_N
|
||||
set_location_assignment PIN_B22 -to ENET_WR_N
|
||||
set_location_assignment PIN_B23 -to ENET_RST_N
|
||||
set_location_assignment PIN_AE24 -to IRDA_TXD
|
||||
set_location_assignment PIN_AE25 -to IRDA_RXD
|
||||
set_location_assignment PIN_AD24 -to SD_DAT
|
||||
set_location_assignment PIN_AC23 -to SD_DAT3
|
||||
set_location_assignment PIN_Y21 -to SD_CMD
|
||||
set_location_assignment PIN_AD25 -to SD_CLK
|
||||
set_location_assignment PIN_D25 -to GPIO_0[0]
|
||||
set_location_assignment PIN_J22 -to GPIO_0[1]
|
||||
set_location_assignment PIN_E26 -to GPIO_0[2]
|
||||
set_location_assignment PIN_E25 -to GPIO_0[3]
|
||||
set_location_assignment PIN_F24 -to GPIO_0[4]
|
||||
set_location_assignment PIN_F23 -to GPIO_0[5]
|
||||
set_location_assignment PIN_J21 -to GPIO_0[6]
|
||||
set_location_assignment PIN_J20 -to GPIO_0[7]
|
||||
set_location_assignment PIN_F25 -to GPIO_0[8]
|
||||
set_location_assignment PIN_F26 -to GPIO_0[9]
|
||||
set_location_assignment PIN_N18 -to GPIO_0[10]
|
||||
set_location_assignment PIN_P18 -to GPIO_0[11]
|
||||
set_location_assignment PIN_G23 -to GPIO_0[12]
|
||||
set_location_assignment PIN_G24 -to GPIO_0[13]
|
||||
set_location_assignment PIN_K22 -to GPIO_0[14]
|
||||
set_location_assignment PIN_G25 -to GPIO_0[15]
|
||||
set_location_assignment PIN_H23 -to GPIO_0[16]
|
||||
set_location_assignment PIN_H24 -to GPIO_0[17]
|
||||
set_location_assignment PIN_J23 -to GPIO_0[18]
|
||||
set_location_assignment PIN_J24 -to GPIO_0[19]
|
||||
set_location_assignment PIN_H25 -to GPIO_0[20]
|
||||
set_location_assignment PIN_H26 -to GPIO_0[21]
|
||||
set_location_assignment PIN_H19 -to GPIO_0[22]
|
||||
set_location_assignment PIN_K18 -to GPIO_0[23]
|
||||
set_location_assignment PIN_K19 -to GPIO_0[24]
|
||||
set_location_assignment PIN_K21 -to GPIO_0[25]
|
||||
set_location_assignment PIN_K23 -to GPIO_0[26]
|
||||
set_location_assignment PIN_K24 -to GPIO_0[27]
|
||||
set_location_assignment PIN_L21 -to GPIO_0[28]
|
||||
set_location_assignment PIN_L20 -to GPIO_0[29]
|
||||
set_location_assignment PIN_J25 -to GPIO_0[30]
|
||||
set_location_assignment PIN_J26 -to GPIO_0[31]
|
||||
set_location_assignment PIN_L23 -to GPIO_0[32]
|
||||
set_location_assignment PIN_L24 -to GPIO_0[33]
|
||||
set_location_assignment PIN_L25 -to GPIO_0[34]
|
||||
set_location_assignment PIN_L19 -to GPIO_0[35]
|
||||
set_location_assignment PIN_K25 -to GPIO_1[0]
|
||||
set_location_assignment PIN_K26 -to GPIO_1[1]
|
||||
set_location_assignment PIN_M22 -to GPIO_1[2]
|
||||
set_location_assignment PIN_M23 -to GPIO_1[3]
|
||||
set_location_assignment PIN_M19 -to GPIO_1[4]
|
||||
set_location_assignment PIN_M20 -to GPIO_1[5]
|
||||
set_location_assignment PIN_N20 -to GPIO_1[6]
|
||||
set_location_assignment PIN_M21 -to GPIO_1[7]
|
||||
set_location_assignment PIN_M24 -to GPIO_1[8]
|
||||
set_location_assignment PIN_M25 -to GPIO_1[9]
|
||||
set_location_assignment PIN_N24 -to GPIO_1[10]
|
||||
set_location_assignment PIN_P24 -to GPIO_1[11]
|
||||
set_location_assignment PIN_R25 -to GPIO_1[12]
|
||||
set_location_assignment PIN_R24 -to GPIO_1[13]
|
||||
set_location_assignment PIN_R20 -to GPIO_1[14]
|
||||
set_location_assignment PIN_T22 -to GPIO_1[15]
|
||||
set_location_assignment PIN_T23 -to GPIO_1[16]
|
||||
set_location_assignment PIN_T24 -to GPIO_1[17]
|
||||
set_location_assignment PIN_T25 -to GPIO_1[18]
|
||||
set_location_assignment PIN_T18 -to GPIO_1[19]
|
||||
set_location_assignment PIN_T21 -to GPIO_1[20]
|
||||
set_location_assignment PIN_T20 -to GPIO_1[21]
|
||||
set_location_assignment PIN_U26 -to GPIO_1[22]
|
||||
set_location_assignment PIN_U25 -to GPIO_1[23]
|
||||
set_location_assignment PIN_U23 -to GPIO_1[24]
|
||||
set_location_assignment PIN_U24 -to GPIO_1[25]
|
||||
set_location_assignment PIN_R19 -to GPIO_1[26]
|
||||
set_location_assignment PIN_T19 -to GPIO_1[27]
|
||||
set_location_assignment PIN_U20 -to GPIO_1[28]
|
||||
set_location_assignment PIN_U21 -to GPIO_1[29]
|
||||
set_location_assignment PIN_V26 -to GPIO_1[30]
|
||||
set_location_assignment PIN_V25 -to GPIO_1[31]
|
||||
set_location_assignment PIN_V24 -to GPIO_1[32]
|
||||
set_location_assignment PIN_V23 -to GPIO_1[33]
|
||||
set_location_assignment PIN_W25 -to GPIO_1[34]
|
||||
set_location_assignment PIN_W23 -to GPIO_1[35]
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name CDF_FILE output_files/Chain4.cdf
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -0,0 +1,51 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 13:26:59 February 15, 2024
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# counters_leds_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone II"
|
||||
set_global_assignment -name DEVICE EP2C35F672C6
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY counters_leds
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:26:59 FEBRUARY 15, 2024"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name VERILOG_FILE ../src/mod_n_counter_10bit.v
|
||||
set_global_assignment -name VERILOG_FILE ../src/d_ff.v
|
||||
set_global_assignment -name VERILOG_FILE ../src/counters_leds.v
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
Binary file not shown.
Binary file not shown.
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Binary file not shown.
Binary file not shown.
Binary file not shown.
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Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,6 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1708005769472 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1708005769473 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 15 15:02:49 2024 " "Processing started: Thu Feb 15 15:02:49 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1708005769473 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1708005769473 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off counters_leds -c counters_leds " "Command: quartus_asm --read_settings_files=off --write_settings_files=off counters_leds -c counters_leds" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1708005769473 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1708005770518 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1708005770565 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4560 " "Peak virtual memory: 4560 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1708005771005 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 15 15:02:51 2024 " "Processing ended: Thu Feb 15 15:02:51 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1708005771005 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1708005771005 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1708005771005 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1708005771005 ""}
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0" ?>
|
||||
<LOG_ROOT>
|
||||
<PROJECT NAME="counters_leds">
|
||||
</PROJECT>
|
||||
</LOG_ROOT>
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1 @@
|
||||
v1
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,3 @@
|
||||
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Version_Index = 302049280
|
||||
Creation_Time = Thu Feb 15 15:02:22 2024
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1,211 @@
|
||||
|counters_leds
|
||||
CLOCK_50 => clk.IN7
|
||||
KEY[0] => rst.IN7
|
||||
LEDG[0] <= d_ff:d_ff_1.Q
|
||||
LEDG[1] <= d_ff:d_ff_2.Q
|
||||
LEDG[2] <= d_ff:d_ff_3.Q
|
||||
|
||||
|
||||
|counters_leds|mod_n_counter_10bit:div_1
|
||||
CLK => Q[0]~reg0.CLK
|
||||
CLK => Q[1]~reg0.CLK
|
||||
CLK => Q[2]~reg0.CLK
|
||||
CLK => Q[3]~reg0.CLK
|
||||
CLK => Q[4]~reg0.CLK
|
||||
CLK => Q[5]~reg0.CLK
|
||||
CLK => Q[6]~reg0.CLK
|
||||
CLK => Q[7]~reg0.CLK
|
||||
CLK => Q[8]~reg0.CLK
|
||||
CLK => Q[9]~reg0.CLK
|
||||
RST => Q[0]~reg0.ACLR
|
||||
RST => Q[1]~reg0.ACLR
|
||||
RST => Q[2]~reg0.ACLR
|
||||
RST => Q[3]~reg0.ACLR
|
||||
RST => Q[4]~reg0.ACLR
|
||||
RST => Q[5]~reg0.ACLR
|
||||
RST => Q[6]~reg0.ACLR
|
||||
RST => Q[7]~reg0.ACLR
|
||||
RST => Q[8]~reg0.ACLR
|
||||
RST => Q[9]~reg0.ACLR
|
||||
EN => Q[9]~reg0.ENA
|
||||
EN => Q[8]~reg0.ENA
|
||||
EN => Q[7]~reg0.ENA
|
||||
EN => Q[6]~reg0.ENA
|
||||
EN => Q[5]~reg0.ENA
|
||||
EN => Q[4]~reg0.ENA
|
||||
EN => Q[3]~reg0.ENA
|
||||
EN => Q[2]~reg0.ENA
|
||||
EN => Q[1]~reg0.ENA
|
||||
EN => Q[0]~reg0.ENA
|
||||
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
TC <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|mod_n_counter_10bit:div_2
|
||||
CLK => Q[0]~reg0.CLK
|
||||
CLK => Q[1]~reg0.CLK
|
||||
CLK => Q[2]~reg0.CLK
|
||||
CLK => Q[3]~reg0.CLK
|
||||
CLK => Q[4]~reg0.CLK
|
||||
CLK => Q[5]~reg0.CLK
|
||||
CLK => Q[6]~reg0.CLK
|
||||
CLK => Q[7]~reg0.CLK
|
||||
CLK => Q[8]~reg0.CLK
|
||||
CLK => Q[9]~reg0.CLK
|
||||
RST => Q[0]~reg0.ACLR
|
||||
RST => Q[1]~reg0.ACLR
|
||||
RST => Q[2]~reg0.ACLR
|
||||
RST => Q[3]~reg0.ACLR
|
||||
RST => Q[4]~reg0.ACLR
|
||||
RST => Q[5]~reg0.ACLR
|
||||
RST => Q[6]~reg0.ACLR
|
||||
RST => Q[7]~reg0.ACLR
|
||||
RST => Q[8]~reg0.ACLR
|
||||
RST => Q[9]~reg0.ACLR
|
||||
EN => Q[9]~reg0.ENA
|
||||
EN => Q[8]~reg0.ENA
|
||||
EN => Q[7]~reg0.ENA
|
||||
EN => Q[6]~reg0.ENA
|
||||
EN => Q[5]~reg0.ENA
|
||||
EN => Q[4]~reg0.ENA
|
||||
EN => Q[3]~reg0.ENA
|
||||
EN => Q[2]~reg0.ENA
|
||||
EN => Q[1]~reg0.ENA
|
||||
EN => Q[0]~reg0.ENA
|
||||
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
TC <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|mod_n_counter_10bit:div_3
|
||||
CLK => Q[0]~reg0.CLK
|
||||
CLK => Q[1]~reg0.CLK
|
||||
CLK => Q[2]~reg0.CLK
|
||||
CLK => Q[3]~reg0.CLK
|
||||
CLK => Q[4]~reg0.CLK
|
||||
CLK => Q[5]~reg0.CLK
|
||||
CLK => Q[6]~reg0.CLK
|
||||
CLK => Q[7]~reg0.CLK
|
||||
CLK => Q[8]~reg0.CLK
|
||||
CLK => Q[9]~reg0.CLK
|
||||
RST => Q[0]~reg0.ACLR
|
||||
RST => Q[1]~reg0.ACLR
|
||||
RST => Q[2]~reg0.ACLR
|
||||
RST => Q[3]~reg0.ACLR
|
||||
RST => Q[4]~reg0.ACLR
|
||||
RST => Q[5]~reg0.ACLR
|
||||
RST => Q[6]~reg0.ACLR
|
||||
RST => Q[7]~reg0.ACLR
|
||||
RST => Q[8]~reg0.ACLR
|
||||
RST => Q[9]~reg0.ACLR
|
||||
EN => Q[0]~reg0.ENA
|
||||
EN => Q[9]~reg0.ENA
|
||||
EN => Q[8]~reg0.ENA
|
||||
EN => Q[7]~reg0.ENA
|
||||
EN => Q[6]~reg0.ENA
|
||||
EN => Q[5]~reg0.ENA
|
||||
EN => Q[4]~reg0.ENA
|
||||
EN => Q[3]~reg0.ENA
|
||||
EN => Q[2]~reg0.ENA
|
||||
EN => Q[1]~reg0.ENA
|
||||
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
TC <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|mod_n_counter_10bit:div_4
|
||||
CLK => Q[0]~reg0.CLK
|
||||
CLK => Q[1]~reg0.CLK
|
||||
CLK => Q[2]~reg0.CLK
|
||||
CLK => Q[3]~reg0.CLK
|
||||
CLK => Q[4]~reg0.CLK
|
||||
CLK => Q[5]~reg0.CLK
|
||||
CLK => Q[6]~reg0.CLK
|
||||
CLK => Q[7]~reg0.CLK
|
||||
CLK => Q[8]~reg0.CLK
|
||||
CLK => Q[9]~reg0.CLK
|
||||
RST => Q[0]~reg0.ACLR
|
||||
RST => Q[1]~reg0.ACLR
|
||||
RST => Q[2]~reg0.ACLR
|
||||
RST => Q[3]~reg0.ACLR
|
||||
RST => Q[4]~reg0.ACLR
|
||||
RST => Q[5]~reg0.ACLR
|
||||
RST => Q[6]~reg0.ACLR
|
||||
RST => Q[7]~reg0.ACLR
|
||||
RST => Q[8]~reg0.ACLR
|
||||
RST => Q[9]~reg0.ACLR
|
||||
EN => Q[0]~reg0.ENA
|
||||
EN => Q[9]~reg0.ENA
|
||||
EN => Q[8]~reg0.ENA
|
||||
EN => Q[7]~reg0.ENA
|
||||
EN => Q[6]~reg0.ENA
|
||||
EN => Q[5]~reg0.ENA
|
||||
EN => Q[4]~reg0.ENA
|
||||
EN => Q[3]~reg0.ENA
|
||||
EN => Q[2]~reg0.ENA
|
||||
EN => Q[1]~reg0.ENA
|
||||
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
TC <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|d_ff:d_ff_1
|
||||
D => Q~reg0.DATAIN
|
||||
CLK => Q~reg0.CLK
|
||||
RST => Q~reg0.ACLR
|
||||
ENA => Q~reg0.ENA
|
||||
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Qn <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|d_ff:d_ff_2
|
||||
D => Q~reg0.DATAIN
|
||||
CLK => Q~reg0.CLK
|
||||
RST => Q~reg0.ACLR
|
||||
ENA => Q~reg0.ENA
|
||||
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Qn <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|d_ff:d_ff_3
|
||||
D => Q~reg0.DATAIN
|
||||
CLK => Q~reg0.CLK
|
||||
RST => Q~reg0.ACLR
|
||||
ENA => Q~reg0.ENA
|
||||
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Qn <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,130 @@
|
||||
<TABLE>
|
||||
<TR bgcolor="#C0C0C0">
|
||||
<TH>Hierarchy</TH>
|
||||
<TH>Input</TH>
|
||||
<TH>Constant Input</TH>
|
||||
<TH>Unused Input</TH>
|
||||
<TH>Floating Input</TH>
|
||||
<TH>Output</TH>
|
||||
<TH>Constant Output</TH>
|
||||
<TH>Unused Output</TH>
|
||||
<TH>Floating Output</TH>
|
||||
<TH>Bidir</TH>
|
||||
<TH>Constant Bidir</TH>
|
||||
<TH>Unused Bidir</TH>
|
||||
<TH>Input only Bidir</TH>
|
||||
<TH>Output only Bidir</TH>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >d_ff_3</TD>
|
||||
<TD >4</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >d_ff_2</TD>
|
||||
<TD >4</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >d_ff_1</TD>
|
||||
<TD >4</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >div_4</TD>
|
||||
<TD >3</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >11</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >div_3</TD>
|
||||
<TD >3</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >11</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >div_2</TD>
|
||||
<TD >3</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >11</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >div_1</TD>
|
||||
<TD >3</TD>
|
||||
<TD >1</TD>
|
||||
<TD >0</TD>
|
||||
<TD >1</TD>
|
||||
<TD >11</TD>
|
||||
<TD >1</TD>
|
||||
<TD >1</TD>
|
||||
<TD >1</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
Binary file not shown.
@@ -0,0 +1,13 @@
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Legal Partition Candidates ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; d_ff_3 ; 4 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; d_ff_2 ; 4 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; d_ff_1 ; 4 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; div_4 ; 3 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; div_3 ; 3 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; div_2 ; 3 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; div_1 ; 3 ; 1 ; 0 ; 1 ; 11 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1 @@
|
||||
v1
|
||||
@@ -0,0 +1,18 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1708005761629 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1708005761630 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 15 15:02:41 2024 " "Processing started: Thu Feb 15 15:02:41 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1708005761630 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1708005761630 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off counters_leds -c counters_leds " "Command: quartus_map --read_settings_files=on --write_settings_files=off counters_leds -c counters_leds" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1708005761630 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1708005762025 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/mod_n_counter_10bit.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/mod_n_counter_10bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 mod_n_counter_10bit " "Found entity 1: mod_n_counter_10bit" { } { { "../src/mod_n_counter_10bit.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/mod_n_counter_10bit.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1708005762108 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1708005762108 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/d_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/d_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 d_ff " "Found entity 1: d_ff" { } { { "../src/d_ff.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/d_ff.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1708005762112 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1708005762112 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/counters_leds.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/counters_leds.v" { { "Info" "ISGN_ENTITY_NAME" "1 counters_leds " "Found entity 1: counters_leds" { } { { "../src/counters_leds.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1708005762115 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1708005762115 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "en_ff_1 counters_leds.v(60) " "Verilog HDL Implicit Net warning at counters_leds.v(60): created implicit net for \"en_ff_1\"" { } { { "../src/counters_leds.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 60 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1708005762116 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "en_ff_2 counters_leds.v(61) " "Verilog HDL Implicit Net warning at counters_leds.v(61): created implicit net for \"en_ff_2\"" { } { { "../src/counters_leds.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 61 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1708005762116 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "en_ff_3 counters_leds.v(62) " "Verilog HDL Implicit Net warning at counters_leds.v(62): created implicit net for \"en_ff_3\"" { } { { "../src/counters_leds.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 62 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1708005762116 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "counters_leds " "Elaborating entity \"counters_leds\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1708005762154 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mod_n_counter_10bit mod_n_counter_10bit:div_1 " "Elaborating entity \"mod_n_counter_10bit\" for hierarchy \"mod_n_counter_10bit:div_1\"" { } { { "../src/counters_leds.v" "div_1" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 71 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1708005762188 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mod_n_counter_10bit mod_n_counter_10bit:div_3 " "Elaborating entity \"mod_n_counter_10bit\" for hierarchy \"mod_n_counter_10bit:div_3\"" { } { { "../src/counters_leds.v" "div_3" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 89 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1708005762194 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mod_n_counter_10bit mod_n_counter_10bit:div_4 " "Elaborating entity \"mod_n_counter_10bit\" for hierarchy \"mod_n_counter_10bit:div_4\"" { } { { "../src/counters_leds.v" "div_4" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 98 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1708005762198 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d_ff d_ff:d_ff_1 " "Elaborating entity \"d_ff\" for hierarchy \"d_ff:d_ff_1\"" { } { { "../src/counters_leds.v" "d_ff_1" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 108 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1708005762201 ""}
|
||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1708005762907 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1708005762907 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "79 " "Implemented 79 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1708005762979 ""} { "Info" "ICUT_CUT_TM_OPINS" "3 " "Implemented 3 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1708005762979 ""} { "Info" "ICUT_CUT_TM_LCELLS" "74 " "Implemented 74 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1708005762979 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1708005762979 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4602 " "Peak virtual memory: 4602 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1708005763008 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 15 15:02:43 2024 " "Processing ended: Thu Feb 15 15:02:43 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1708005763008 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1708005763008 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1708005763008 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1708005763008 ""}
|
||||
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|
||||
v1
|
||||
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|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1708005776992 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 64-Bit " "Running Quartus II 64-Bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1708005776993 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 15 15:02:56 2024 " "Processing started: Thu Feb 15 15:02:56 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1708005776993 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1708005776993 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp counters_leds -c counters_leds --netlist_type=sgate " "Command: quartus_rpp counters_leds -c counters_leds --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1708005776993 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4428 " "Peak virtual memory: 4428 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1708005777034 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 15 15:02:57 2024 " "Processing ended: Thu Feb 15 15:02:57 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1708005777034 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1708005777034 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1708005777034 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1708005777034 ""}
|
||||
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|
||||
DONE
|
||||
@@ -0,0 +1,30 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1708005772017 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772017 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 15 15:02:51 2024 " "Processing started: Thu Feb 15 15:02:51 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1708005772017 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1708005772017 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta counters_leds -c counters_leds " "Command: quartus_sta counters_leds -c counters_leds" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1708005772018 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1708005772106 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1708005772259 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1708005772289 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1708005772289 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "counters_leds.sdc " "Synopsys Design Constraints File file not found: 'counters_leds.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1708005772362 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1708005772363 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772363 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772363 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1708005772365 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1708005772378 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1708005772383 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.423 " "Worst-case setup slack is -2.423" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772385 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772385 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.423 -80.978 CLOCK_50 " " -2.423 -80.978 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772385 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772385 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.391 " "Worst-case hold slack is 0.391" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772388 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772388 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.391 0.000 CLOCK_50 " " 0.391 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772388 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772388 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1708005772392 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1708005772394 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772397 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772397 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -44.380 CLOCK_50 " " -1.380 -44.380 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772397 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772397 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1708005772419 ""}
|
||||
{ "Info" "0" "" "Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1708005772421 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1708005772429 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.652 " "Worst-case setup slack is -0.652" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772432 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772432 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.652 -17.377 CLOCK_50 " " -0.652 -17.377 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772432 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772432 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.215 " "Worst-case hold slack is 0.215" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.215 0.000 CLOCK_50 " " 0.215 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772436 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772436 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1708005772439 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1708005772443 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772446 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772446 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -44.380 CLOCK_50 " " -1.380 -44.380 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772446 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772446 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1708005772471 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1708005772493 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1708005772493 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4544 " "Peak virtual memory: 4544 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1708005772554 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 15 15:02:52 2024 " "Processing ended: Thu Feb 15 15:02:52 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1708005772554 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1708005772554 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1708005772554 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1708005772554 ""}
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,6 @@
|
||||
start_full_compilation:s:00:00:12
|
||||
start_analysis_synthesis:s:00:00:02-start_full_compilation
|
||||
start_analysis_elaboration:s-start_full_compilation
|
||||
start_fitter:s:00:00:06-start_full_compilation
|
||||
start_assembler:s:00:00:02-start_full_compilation
|
||||
start_timing_analyzer:s:00:00:02-start_full_compilation
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,11 @@
|
||||
This folder contains data for incremental compilation.
|
||||
|
||||
The compiled_partitions sub-folder contains previous compilation results for each partition.
|
||||
As long as this folder is preserved, incremental compilation results from earlier compiles
|
||||
can be re-used. To perform a clean compilation from source files for all partitions, both
|
||||
the db and incremental_db folder should be removed.
|
||||
|
||||
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
|
||||
As long as this folder is preserved, imported partitions will be automatically re-imported
|
||||
when the db or incremental_db/compiled_partitions folders are removed.
|
||||
|
||||
@@ -0,0 +1,3 @@
|
||||
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Version_Index = 302049280
|
||||
Creation_Time = Thu Feb 15 13:40:16 2024
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
BIN
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BIN
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BIN
Binary file not shown.
+1
@@ -0,0 +1 @@
|
||||
v1
|
||||
BIN
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BIN
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BIN
Binary file not shown.
BIN
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BIN
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BIN
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+1
@@ -0,0 +1 @@
|
||||
9a9b3e9d06db00b9dc03feca87af856c
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,13 @@
|
||||
/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */
|
||||
JedecChain;
|
||||
FileRevision(JESD32A);
|
||||
DefaultMfr(6E);
|
||||
|
||||
P ActionCode(Cfg)
|
||||
Device PartName(EP2C35F672) Path("C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/quartus/output_files/") File("counters_leds.sof") MfrSpec(OpMask(1));
|
||||
|
||||
ChainEnd;
|
||||
|
||||
AlteraBegin;
|
||||
ChainType(JTAG);
|
||||
AlteraEnd;
|
||||
@@ -0,0 +1,130 @@
|
||||
Assembler report for counters_leds
|
||||
Thu Feb 15 15:02:50 2024
|
||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Assembler Summary
|
||||
3. Assembler Settings
|
||||
4. Assembler Generated Files
|
||||
5. Assembler Device Options: C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/quartus/output_files/counters_leds.sof
|
||||
6. Assembler Device Options: C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/quartus/output_files/counters_leds.pof
|
||||
7. Assembler Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Thu Feb 15 15:02:50 2024 ;
|
||||
; Revision Name ; counters_leds ;
|
||||
; Top-level Entity Name ; counters_leds ;
|
||||
; Family ; Cyclone II ;
|
||||
; Device ; EP2C35F672C6 ;
|
||||
+-----------------------+---------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------+
|
||||
; Assembler Settings ;
|
||||
+-----------------------------------------------------------------------------+----------+---------------+
|
||||
; Option ; Setting ; Default Value ;
|
||||
+-----------------------------------------------------------------------------+----------+---------------+
|
||||
; Use smart compilation ; Off ; Off ;
|
||||
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
|
||||
; Enable compact report table ; Off ; Off ;
|
||||
; Generate compressed bitstreams ; On ; On ;
|
||||
; Compression mode ; Off ; Off ;
|
||||
; Clock source for configuration device ; Internal ; Internal ;
|
||||
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
|
||||
; Divide clock frequency by ; 1 ; 1 ;
|
||||
; Auto user code ; On ; On ;
|
||||
; Use configuration device ; On ; On ;
|
||||
; Configuration device ; Auto ; Auto ;
|
||||
; Configuration device auto user code ; Off ; Off ;
|
||||
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
|
||||
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
|
||||
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
|
||||
; Hexadecimal Output File start address ; 0 ; 0 ;
|
||||
; Hexadecimal Output File count direction ; Up ; Up ;
|
||||
; Release clears before tri-states ; Off ; Off ;
|
||||
; Auto-restart configuration after error ; On ; On ;
|
||||
; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ;
|
||||
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
|
||||
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
|
||||
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
|
||||
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
|
||||
+-----------------------------------------------------------------------------+----------+---------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Assembler Generated Files ;
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; File Name ;
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/quartus/output_files/counters_leds.sof ;
|
||||
; C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/quartus/output_files/counters_leds.pof ;
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Assembler Device Options: C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/quartus/output_files/counters_leds.sof ;
|
||||
+----------------+---------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+---------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Device ; EP2C35F672C6 ;
|
||||
; JTAG usercode ; 0x002F21B4 ;
|
||||
; Checksum ; 0x002F21B4 ;
|
||||
+----------------+---------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Assembler Device Options: C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/quartus/output_files/counters_leds.pof ;
|
||||
+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Device ; EPCS16 ;
|
||||
; JTAG usercode ; 0x00000000 ;
|
||||
; Checksum ; 0x1C761E27 ;
|
||||
; Compression Ratio ; 3 ;
|
||||
+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------+
|
||||
; Assembler Messages ;
|
||||
+--------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 64-Bit Assembler
|
||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Info: Processing started: Thu Feb 15 15:02:49 2024
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off counters_leds -c counters_leds
|
||||
Info (115031): Writing out detailed assembly data for power analysis
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 4560 megabytes
|
||||
Info: Processing ended: Thu Feb 15 15:02:51 2024
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
@@ -0,0 +1 @@
|
||||
Thu Feb 15 15:02:57 2024
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,8 @@
|
||||
Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
|
||||
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
|
||||
Extra Info (176236): Started Fast Input/Output/OE register processing
|
||||
Extra Info (176237): Finished Fast Input/Output/OE register processing
|
||||
Extra Info (176238): Start inferring scan chains for DSP blocks
|
||||
Extra Info (176239): Inferring scan chains for DSP blocks is complete
|
||||
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
|
||||
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
|
||||
@@ -0,0 +1,16 @@
|
||||
Fitter Status : Successful - Thu Feb 15 15:02:48 2024
|
||||
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Revision Name : counters_leds
|
||||
Top-level Entity Name : counters_leds
|
||||
Family : Cyclone II
|
||||
Device : EP2C35F672C6
|
||||
Timing Models : Final
|
||||
Total logic elements : 74 / 33,216 ( < 1 % )
|
||||
Total combinational functions : 74 / 33,216 ( < 1 % )
|
||||
Dedicated logic registers : 43 / 33,216 ( < 1 % )
|
||||
Total registers : 43
|
||||
Total pins : 5 / 475 ( 1 % )
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 0 / 483,840 ( 0 % )
|
||||
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
|
||||
Total PLLs : 0 / 4 ( 0 % )
|
||||
@@ -0,0 +1,124 @@
|
||||
Flow report for counters_leds
|
||||
Thu Feb 15 15:02:52 2024
|
||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Flow Summary
|
||||
3. Flow Settings
|
||||
4. Flow Non-Default Global Settings
|
||||
5. Flow Elapsed Time
|
||||
6. Flow OS Summary
|
||||
7. Flow Log
|
||||
8. Flow Messages
|
||||
9. Flow Suppressed Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+------------------------------------+-------------------------------------------------+
|
||||
; Flow Status ; Successful - Thu Feb 15 15:02:50 2024 ;
|
||||
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Revision Name ; counters_leds ;
|
||||
; Top-level Entity Name ; counters_leds ;
|
||||
; Family ; Cyclone II ;
|
||||
; Device ; EP2C35F672C6 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 74 / 33,216 ( < 1 % ) ;
|
||||
; Total combinational functions ; 74 / 33,216 ( < 1 % ) ;
|
||||
; Dedicated logic registers ; 43 / 33,216 ( < 1 % ) ;
|
||||
; Total registers ; 43 ;
|
||||
; Total pins ; 5 / 475 ( 1 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 0 / 483,840 ( 0 % ) ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ;
|
||||
; Total PLLs ; 0 / 4 ( 0 % ) ;
|
||||
+------------------------------------+-------------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------+
|
||||
; Flow Settings ;
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 02/15/2024 15:02:41 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; counters_leds ;
|
||||
+-------------------+---------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------------+
|
||||
; Flow Non-Default Global Settings ;
|
||||
+-------------------------------------+---------------------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+-------------------------------------+---------------------------------------+---------------+-------------+------------+
|
||||
; COMPILER_SIGNATURE_ID ; 246775572656857.170800576114884 ; -- ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
|
||||
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
|
||||
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
|
||||
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
|
||||
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
|
||||
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
||||
+-------------------------------------+---------------------------------------+---------------+-------------+------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Flow Elapsed Time ;
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4592 MB ; 00:00:01 ;
|
||||
; Fitter ; 00:00:05 ; 1.0 ; 4876 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 4560 MB ; 00:00:01 ;
|
||||
; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4544 MB ; 00:00:00 ;
|
||||
; Total ; 00:00:08 ; -- ; -- ; 00:00:06 ;
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------+
|
||||
; Flow OS Summary ;
|
||||
+---------------------------+------------------+-----------+------------+----------------+
|
||||
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
||||
+---------------------------+------------------+-----------+------------+----------------+
|
||||
; Analysis & Synthesis ; DESKTOP-MSP383K ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
; Fitter ; DESKTOP-MSP383K ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
; Assembler ; DESKTOP-MSP383K ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
; TimeQuest Timing Analyzer ; DESKTOP-MSP383K ; Windows 7 ; 6.2 ; x86_64 ;
|
||||
+---------------------------+------------------+-----------+------------+----------------+
|
||||
|
||||
|
||||
------------
|
||||
; Flow Log ;
|
||||
------------
|
||||
quartus_map --read_settings_files=on --write_settings_files=off counters_leds -c counters_leds
|
||||
quartus_fit --read_settings_files=off --write_settings_files=off counters_leds -c counters_leds
|
||||
quartus_asm --read_settings_files=off --write_settings_files=off counters_leds -c counters_leds
|
||||
quartus_sta counters_leds -c counters_leds
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,8 @@
|
||||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="9978a815b38d7bbb0bc9"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="EP2C35F672C6" path="counters_leds.sof" usercode="0xFFFFFFFF"/>
|
||||
</file_info>
|
||||
</sld_project_info>
|
||||
@@ -0,0 +1,359 @@
|
||||
Analysis & Synthesis report for counters_leds
|
||||
Thu Feb 15 15:02:42 2024
|
||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Analysis & Synthesis Summary
|
||||
3. Analysis & Synthesis Settings
|
||||
4. Parallel Compilation
|
||||
5. Analysis & Synthesis Source Files Read
|
||||
6. Analysis & Synthesis Resource Usage Summary
|
||||
7. Analysis & Synthesis Resource Utilization by Entity
|
||||
8. General Register Statistics
|
||||
9. Parameter Settings for User Entity Instance: mod_n_counter_10bit:div_1
|
||||
10. Parameter Settings for User Entity Instance: mod_n_counter_10bit:div_2
|
||||
11. Parameter Settings for User Entity Instance: mod_n_counter_10bit:div_3
|
||||
12. Parameter Settings for User Entity Instance: mod_n_counter_10bit:div_4
|
||||
13. Port Connectivity Checks: "mod_n_counter_10bit:div_4"
|
||||
14. Port Connectivity Checks: "mod_n_counter_10bit:div_3"
|
||||
15. Port Connectivity Checks: "mod_n_counter_10bit:div_2"
|
||||
16. Port Connectivity Checks: "mod_n_counter_10bit:div_1"
|
||||
17. Elapsed Time Per Partition
|
||||
18. Analysis & Synthesis Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+------------------------------------+-------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Thu Feb 15 15:02:42 2024 ;
|
||||
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Revision Name ; counters_leds ;
|
||||
; Top-level Entity Name ; counters_leds ;
|
||||
; Family ; Cyclone II ;
|
||||
; Total logic elements ; 74 ;
|
||||
; Total combinational functions ; 74 ;
|
||||
; Dedicated logic registers ; 43 ;
|
||||
; Total registers ; 43 ;
|
||||
; Total pins ; 5 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 0 ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 ;
|
||||
; Total PLLs ; 0 ;
|
||||
+------------------------------------+-------------------------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Settings ;
|
||||
+----------------------------------------------------------------------------+--------------------+--------------------+
|
||||
; Option ; Setting ; Default Value ;
|
||||
+----------------------------------------------------------------------------+--------------------+--------------------+
|
||||
; Device ; EP2C35F672C6 ; ;
|
||||
; Top-level entity name ; counters_leds ; counters_leds ;
|
||||
; Family name ; Cyclone II ; Cyclone IV GX ;
|
||||
; Use smart compilation ; Off ; Off ;
|
||||
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
|
||||
; Enable compact report table ; Off ; Off ;
|
||||
; Restructure Multiplexers ; Auto ; Auto ;
|
||||
; Create Debugging Nodes for IP Cores ; Off ; Off ;
|
||||
; Preserve fewer node names ; On ; On ;
|
||||
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
|
||||
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
|
||||
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
|
||||
; State Machine Processing ; Auto ; Auto ;
|
||||
; Safe State Machine ; Off ; Off ;
|
||||
; Extract Verilog State Machines ; On ; On ;
|
||||
; Extract VHDL State Machines ; On ; On ;
|
||||
; Ignore Verilog initial constructs ; Off ; Off ;
|
||||
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
|
||||
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
|
||||
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
|
||||
; Infer RAMs from Raw Logic ; On ; On ;
|
||||
; Parallel Synthesis ; On ; On ;
|
||||
; DSP Block Balancing ; Auto ; Auto ;
|
||||
; NOT Gate Push-Back ; On ; On ;
|
||||
; Power-Up Don't Care ; On ; On ;
|
||||
; Remove Redundant Logic Cells ; Off ; Off ;
|
||||
; Remove Duplicate Registers ; On ; On ;
|
||||
; Ignore CARRY Buffers ; Off ; Off ;
|
||||
; Ignore CASCADE Buffers ; Off ; Off ;
|
||||
; Ignore GLOBAL Buffers ; Off ; Off ;
|
||||
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
|
||||
; Ignore LCELL Buffers ; Off ; Off ;
|
||||
; Ignore SOFT Buffers ; On ; On ;
|
||||
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
|
||||
; Optimization Technique ; Balanced ; Balanced ;
|
||||
; Carry Chain Length ; 70 ; 70 ;
|
||||
; Auto Carry Chains ; On ; On ;
|
||||
; Auto Open-Drain Pins ; On ; On ;
|
||||
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
|
||||
; Auto ROM Replacement ; On ; On ;
|
||||
; Auto RAM Replacement ; On ; On ;
|
||||
; Auto Shift Register Replacement ; Auto ; Auto ;
|
||||
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
|
||||
; Auto Clock Enable Replacement ; On ; On ;
|
||||
; Strict RAM Replacement ; Off ; Off ;
|
||||
; Allow Synchronous Control Signals ; On ; On ;
|
||||
; Force Use of Synchronous Clear Signals ; Off ; Off ;
|
||||
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
|
||||
; Auto Resource Sharing ; Off ; Off ;
|
||||
; Allow Any RAM Size For Recognition ; Off ; Off ;
|
||||
; Allow Any ROM Size For Recognition ; Off ; Off ;
|
||||
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
|
||||
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
|
||||
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
|
||||
; Timing-Driven Synthesis ; Off ; Off ;
|
||||
; Report Parameter Settings ; On ; On ;
|
||||
; Report Source Assignments ; On ; On ;
|
||||
; Report Connectivity Checks ; On ; On ;
|
||||
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
|
||||
; Synchronization Register Chain Length ; 2 ; 2 ;
|
||||
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
|
||||
; HDL message level ; Level2 ; Level2 ;
|
||||
; Suppress Register Optimization Related Messages ; Off ; Off ;
|
||||
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
|
||||
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
|
||||
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
|
||||
; Clock MUX Protection ; On ; On ;
|
||||
; Auto Gated Clock Conversion ; Off ; Off ;
|
||||
; Block Design Naming ; Auto ; Auto ;
|
||||
; SDC constraint protection ; Off ; Off ;
|
||||
; Synthesis Effort ; Auto ; Auto ;
|
||||
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
|
||||
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
|
||||
; Analysis & Synthesis Message Level ; Medium ; Medium ;
|
||||
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
|
||||
; Resource Aware Inference For Block RAM ; On ; On ;
|
||||
; Synthesis Seed ; 1 ; 1 ;
|
||||
+----------------------------------------------------------------------------+--------------------+--------------------+
|
||||
|
||||
|
||||
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
|
||||
+-------------------------------------+
|
||||
; Parallel Compilation ;
|
||||
+----------------------------+--------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+--------+
|
||||
; Number detected on machine ; 12 ;
|
||||
; Maximum allowed ; 1 ;
|
||||
+----------------------------+--------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------+---------+
|
||||
; ../src/mod_n_counter_10bit.v ; yes ; User Verilog HDL File ; C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/mod_n_counter_10bit.v ; ;
|
||||
; ../src/d_ff.v ; yes ; User Verilog HDL File ; C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/d_ff.v ; ;
|
||||
; ../src/counters_leds.v ; yes ; User Verilog HDL File ; C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v ; ;
|
||||
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------+---------+
|
||||
|
||||
|
||||
+--------------------------------------------------------+
|
||||
; Analysis & Synthesis Resource Usage Summary ;
|
||||
+---------------------------------------------+----------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+----------+
|
||||
; Estimated Total logic elements ; 74 ;
|
||||
; ; ;
|
||||
; Total combinational functions ; 74 ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 13 ;
|
||||
; -- 3 input functions ; 1 ;
|
||||
; -- <=2 input functions ; 60 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 38 ;
|
||||
; -- arithmetic mode ; 36 ;
|
||||
; ; ;
|
||||
; Total registers ; 43 ;
|
||||
; -- Dedicated logic registers ; 43 ;
|
||||
; -- I/O registers ; 0 ;
|
||||
; ; ;
|
||||
; I/O pins ; 5 ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 ;
|
||||
; Maximum fan-out node ; CLOCK_50 ;
|
||||
; Maximum fan-out ; 43 ;
|
||||
; Total fan-out ; 333 ;
|
||||
; Average fan-out ; 2.73 ;
|
||||
+---------------------------------------------+----------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Resource Utilization by Entity ;
|
||||
+--------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------+--------------+
|
||||
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
|
||||
+--------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------+--------------+
|
||||
; |counters_leds ; 74 (2) ; 43 (0) ; 0 ; 0 ; 0 ; 0 ; 5 ; 0 ; |counters_leds ; work ;
|
||||
; |d_ff:d_ff_1| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |counters_leds|d_ff:d_ff_1 ; work ;
|
||||
; |d_ff:d_ff_2| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |counters_leds|d_ff:d_ff_2 ; work ;
|
||||
; |d_ff:d_ff_3| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |counters_leds|d_ff:d_ff_3 ; work ;
|
||||
; |mod_n_counter_10bit:div_1| ; 19 (19) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |counters_leds|mod_n_counter_10bit:div_1 ; work ;
|
||||
; |mod_n_counter_10bit:div_2| ; 19 (19) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |counters_leds|mod_n_counter_10bit:div_2 ; work ;
|
||||
; |mod_n_counter_10bit:div_3| ; 16 (16) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |counters_leds|mod_n_counter_10bit:div_3 ; work ;
|
||||
; |mod_n_counter_10bit:div_4| ; 15 (15) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |counters_leds|mod_n_counter_10bit:div_4 ; work ;
|
||||
+--------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
|
||||
+------------------------------------------------------+
|
||||
; General Register Statistics ;
|
||||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 43 ;
|
||||
; Number of registers using Synchronous Clear ; 0 ;
|
||||
; Number of registers using Synchronous Load ; 0 ;
|
||||
; Number of registers using Asynchronous Clear ; 43 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
; Number of registers using Clock Enable ; 32 ;
|
||||
; Number of registers using Preset ; 0 ;
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------+
|
||||
; Parameter Settings for User Entity Instance: mod_n_counter_10bit:div_1 ;
|
||||
+----------------+-------+-----------------------------------------------+
|
||||
; Parameter Name ; Value ; Type ;
|
||||
+----------------+-------+-----------------------------------------------+
|
||||
; N ; 1000 ; Signed Integer ;
|
||||
+----------------+-------+-----------------------------------------------+
|
||||
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||||
|
||||
|
||||
+------------------------------------------------------------------------+
|
||||
; Parameter Settings for User Entity Instance: mod_n_counter_10bit:div_2 ;
|
||||
+----------------+-------+-----------------------------------------------+
|
||||
; Parameter Name ; Value ; Type ;
|
||||
+----------------+-------+-----------------------------------------------+
|
||||
; N ; 1000 ; Signed Integer ;
|
||||
+----------------+-------+-----------------------------------------------+
|
||||
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||||
|
||||
|
||||
+------------------------------------------------------------------------+
|
||||
; Parameter Settings for User Entity Instance: mod_n_counter_10bit:div_3 ;
|
||||
+----------------+-------+-----------------------------------------------+
|
||||
; Parameter Name ; Value ; Type ;
|
||||
+----------------+-------+-----------------------------------------------+
|
||||
; N ; 25 ; Signed Integer ;
|
||||
+----------------+-------+-----------------------------------------------+
|
||||
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||||
|
||||
|
||||
+------------------------------------------------------------------------+
|
||||
; Parameter Settings for User Entity Instance: mod_n_counter_10bit:div_4 ;
|
||||
+----------------+-------+-----------------------------------------------+
|
||||
; Parameter Name ; Value ; Type ;
|
||||
+----------------+-------+-----------------------------------------------+
|
||||
; N ; 5 ; Signed Integer ;
|
||||
+----------------+-------+-----------------------------------------------+
|
||||
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "mod_n_counter_10bit:div_4" ;
|
||||
+------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; Q ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
+------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "mod_n_counter_10bit:div_3" ;
|
||||
+------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; Q ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
+------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "mod_n_counter_10bit:div_2" ;
|
||||
+------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; Q ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
+------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "mod_n_counter_10bit:div_1" ;
|
||||
+------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; EN ; Input ; Info ; Stuck at VCC ;
|
||||
; Q ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
+------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+-------------------------------+
|
||||
; Elapsed Time Per Partition ;
|
||||
+----------------+--------------+
|
||||
; Partition Name ; Elapsed Time ;
|
||||
+----------------+--------------+
|
||||
; Top ; 00:00:00 ;
|
||||
+----------------+--------------+
|
||||
|
||||
|
||||
+-------------------------------+
|
||||
; Analysis & Synthesis Messages ;
|
||||
+-------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 64-Bit Analysis & Synthesis
|
||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Info: Processing started: Thu Feb 15 15:02:41 2024
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off counters_leds -c counters_leds
|
||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/mod_n_counter_10bit.v
|
||||
Info (12023): Found entity 1: mod_n_counter_10bit
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/d_ff.v
|
||||
Info (12023): Found entity 1: d_ff
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/counters_leds.v
|
||||
Info (12023): Found entity 1: counters_leds
|
||||
Warning (10236): Verilog HDL Implicit Net warning at counters_leds.v(60): created implicit net for "en_ff_1"
|
||||
Warning (10236): Verilog HDL Implicit Net warning at counters_leds.v(61): created implicit net for "en_ff_2"
|
||||
Warning (10236): Verilog HDL Implicit Net warning at counters_leds.v(62): created implicit net for "en_ff_3"
|
||||
Info (12127): Elaborating entity "counters_leds" for the top level hierarchy
|
||||
Info (12128): Elaborating entity "mod_n_counter_10bit" for hierarchy "mod_n_counter_10bit:div_1"
|
||||
Info (12128): Elaborating entity "mod_n_counter_10bit" for hierarchy "mod_n_counter_10bit:div_3"
|
||||
Info (12128): Elaborating entity "mod_n_counter_10bit" for hierarchy "mod_n_counter_10bit:div_4"
|
||||
Info (12128): Elaborating entity "d_ff" for hierarchy "d_ff:d_ff_1"
|
||||
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
|
||||
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
|
||||
Info (21057): Implemented 79 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 2 input pins
|
||||
Info (21059): Implemented 3 output pins
|
||||
Info (21061): Implemented 74 logic cells
|
||||
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 4 warnings
|
||||
Info: Peak virtual memory: 4602 megabytes
|
||||
Info: Processing ended: Thu Feb 15 15:02:43 2024
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
Analysis & Synthesis Status : Successful - Thu Feb 15 15:02:42 2024
|
||||
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Revision Name : counters_leds
|
||||
Top-level Entity Name : counters_leds
|
||||
Family : Cyclone II
|
||||
Total logic elements : 74
|
||||
Total combinational functions : 74
|
||||
Dedicated logic registers : 43
|
||||
Total registers : 43
|
||||
Total pins : 5
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 0
|
||||
Embedded Multiplier 9-bit elements : 0
|
||||
Total PLLs : 0
|
||||
@@ -0,0 +1,742 @@
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
--
|
||||
-- This is a Quartus II output file. It is for reporting purposes only, and is
|
||||
-- not intended for use as a Quartus II input file. This file cannot be used
|
||||
-- to make Quartus II pin assignments - for instructions on how to make pin
|
||||
-- assignments, please see Quartus II help.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
-- NC : No Connect. This pin has no internal connection to the device.
|
||||
-- DNU : Do Not Use. This pin MUST NOT be connected.
|
||||
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
|
||||
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
|
||||
-- of its bank.
|
||||
-- Bank 1: 3.3V
|
||||
-- Bank 2: 3.3V
|
||||
-- Bank 3: 3.3V
|
||||
-- Bank 4: 3.3V
|
||||
-- Bank 5: 3.3V
|
||||
-- Bank 6: 3.3V
|
||||
-- Bank 7: 3.3V
|
||||
-- Bank 8: 3.3V
|
||||
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
|
||||
-- It can also be used to report unused dedicated pins. The connection
|
||||
-- on the board for unused dedicated pins depends on whether this will
|
||||
-- be used in a future design. One example is device migration. When
|
||||
-- using device migration, refer to the device pin-tables. If it is a
|
||||
-- GND pin in the pin table or if it will not be used in a future design
|
||||
-- for another purpose the it MUST be connected to GND. If it is an unused
|
||||
-- dedicated pin, then it can be connected to a valid signal on the board
|
||||
-- (low, high, or toggling) if that signal is required for a different
|
||||
-- revision of the design.
|
||||
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
|
||||
-- This pin should be connected to GND. It may also be connected to a
|
||||
-- valid signal on the board (low, high, or toggling) if that signal
|
||||
-- is required for a different revision of the design.
|
||||
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
|
||||
-- or leave it unconnected.
|
||||
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
|
||||
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
|
||||
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
|
||||
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
|
||||
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
CHIP "counters_leds" ASSIGNED TO AN: EP2C35F672C6
|
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
GND : A2 : gnd : : : :
|
||||
VCCIO3 : A3 : power : : 3.3V : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 3 :
|
||||
VCCIO3 : A11 : power : : 3.3V : 3 :
|
||||
GND : A12 : gnd : : : :
|
||||
GND+ : A13 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 4 :
|
||||
GND : A15 : gnd : : : :
|
||||
VCCIO4 : A16 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 4 :
|
||||
VCCIO4 : A24 : power : : 3.3V : 4 :
|
||||
GND : A25 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 1 :
|
||||
VCCA_PLL1 : AA8 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 7 :
|
||||
VCCA_PLL4 : AA19 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 7 :
|
||||
GND_PLL4 : AA21 : gnd : : : :
|
||||
VCCIO6 : AA22 : power : : 3.3V : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 1 :
|
||||
VCCIO1 : AB5 : power : : 3.3V : 1 :
|
||||
VCCIO8 : AB6 : power : : 3.3V : 8 :
|
||||
GND : AB7 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 8 :
|
||||
VCCIO8 : AB9 : power : : 3.3V : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 8 :
|
||||
GND : AB11 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 8 :
|
||||
VCCIO8 : AB13 : power : : 3.3V : 8 :
|
||||
VCCIO7 : AB14 : power : : 3.3V : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 7 :
|
||||
GND : AB16 : gnd : : : :
|
||||
VCCIO7 : AB17 : power : : 3.3V : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 7 :
|
||||
GND : AB19 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 7 :
|
||||
VCCIO7 : AB22 : power : : 3.3V : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 1 :
|
||||
GND : AC4 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC6 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 8 :
|
||||
GND+ : AC13 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC16 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 6 :
|
||||
NC : AC24 : : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC26 : : : : 6 :
|
||||
VCCIO1 : AD1 : power : : 3.3V : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 8 :
|
||||
GND : AD9 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 8 :
|
||||
GND+ : AD13 : : : : 8 :
|
||||
GND : AD14 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD16 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 7 :
|
||||
GND : AD18 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 7 :
|
||||
VCCIO7 : AD20 : power : : 3.3V : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD23 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 6 :
|
||||
VCCIO6 : AD26 : power : : 3.3V : 6 :
|
||||
GND : AE1 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 8 :
|
||||
GND+ : AE14 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 7 :
|
||||
LEDG[0] : AE22 : output : 3.3-V LVTTL : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 7 :
|
||||
~LVDS150p/nCEO~ : AE24 : output : 3.3-V LVTTL : : 6 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 6 :
|
||||
GND : AE26 : gnd : : : :
|
||||
GND : AF2 : gnd : : : :
|
||||
VCCIO8 : AF3 : power : : 3.3V : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 8 :
|
||||
VCCIO8 : AF11 : power : : 3.3V : 8 :
|
||||
GND : AF12 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 8 :
|
||||
GND+ : AF14 : : : : 7 :
|
||||
GND : AF15 : gnd : : : :
|
||||
VCCIO7 : AF16 : power : : 3.3V : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 7 :
|
||||
LEDG[1] : AF22 : output : 3.3-V LVTTL : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 7 :
|
||||
VCCIO7 : AF24 : power : : 3.3V : 7 :
|
||||
GND : AF25 : gnd : : : :
|
||||
GND : B1 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B9 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 3 :
|
||||
GND+ : B13 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B24 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 5 :
|
||||
GND : B26 : gnd : : : :
|
||||
VCCIO2 : C1 : power : : 3.3V : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 3 :
|
||||
GND+ : C13 : : : : 3 :
|
||||
GND : C14 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 4 :
|
||||
GND : C18 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 4 :
|
||||
VCCIO4 : C20 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 5 :
|
||||
VCCIO5 : C26 : power : : 3.3V : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 2 :
|
||||
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : input : 3.3-V LVTTL : : 2 : N
|
||||
GND : D4 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 3 :
|
||||
GND+ : D13 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 4 :
|
||||
VCCIO4 : D22 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 5 :
|
||||
GND : D24 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : : : : 2 :
|
||||
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : input : 3.3-V LVTTL : : 2 : N
|
||||
GND_PLL3 : E4 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 2 :
|
||||
VCCIO3 : E6 : power : : 3.3V : 3 :
|
||||
GND : E7 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 3 :
|
||||
VCCIO3 : E9 : power : : 3.3V : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 3 :
|
||||
GND : E11 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 3 :
|
||||
VCCIO3 : E13 : power : : 3.3V : 3 :
|
||||
VCCIO4 : E14 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 4 :
|
||||
GND : E16 : gnd : : : :
|
||||
VCCIO4 : E17 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 4 :
|
||||
GND : E19 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 4 :
|
||||
GND_PLL2 : E21 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 2 :
|
||||
VCCIO2 : F5 : power : : 3.3V : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 2 :
|
||||
GNDA_PLL3 : F8 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 4 :
|
||||
GNDA_PLL2 : F19 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 5 :
|
||||
VCCIO5 : F22 : power : : 3.3V : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F23 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 2 :
|
||||
GND_PLL3 : G7 : gnd : : : :
|
||||
VCCA_PLL3 : G8 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 4 :
|
||||
VCCA_PLL2 : G19 : power : : 1.2V : :
|
||||
GND_PLL2 : G20 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 5 :
|
||||
KEY[0] : G26 : input : 3.3-V LVTTL : : 5 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 2 :
|
||||
GND : H5 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 2 :
|
||||
VCCD_PLL3 : H7 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 3 :
|
||||
VCCIO3 : H9 : power : : 3.3V : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 3 :
|
||||
GND : H13 : gnd : : : :
|
||||
GND : H14 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 4 :
|
||||
VCCIO4 : H18 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 5 :
|
||||
VCCD_PLL2 : H20 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 5 :
|
||||
GND : H22 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 3 :
|
||||
VCCIO3 : J12 : power : : 3.3V : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 3 :
|
||||
VCCIO4 : J15 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 4 :
|
||||
VCCIO5 : J19 : power : : 3.3V : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 3 :
|
||||
VCCINT : K10 : power : : 1.2V : :
|
||||
VCCINT : K11 : power : : 1.2V : :
|
||||
VCCINT : K12 : power : : 1.2V : :
|
||||
VCCINT : K13 : power : : 1.2V : :
|
||||
VCCINT : K14 : power : : 1.2V : :
|
||||
VCCINT : K15 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K16 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 5 :
|
||||
GND : K20 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K24 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 5 :
|
||||
VCCIO2 : L1 : power : : 3.3V : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 2 :
|
||||
GND : L5 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 2 :
|
||||
TMS : L8 : input : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L10 : : : : 2 :
|
||||
VCCINT : L11 : power : : 1.2V : :
|
||||
GND : L12 : gnd : : : :
|
||||
GND : L13 : gnd : : : :
|
||||
GND : L14 : gnd : : : :
|
||||
GND : L15 : gnd : : : :
|
||||
VCCINT : L16 : power : : 1.2V : :
|
||||
VCCINT : L17 : power : : 1.2V : :
|
||||
VCCINT : L18 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L19 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 5 :
|
||||
GND : L22 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 5 :
|
||||
VCCIO5 : L26 : power : : 3.3V : 5 :
|
||||
GND : M1 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 2 :
|
||||
TCK : M6 : input : : : 2 :
|
||||
TDO : M7 : output : : : 2 :
|
||||
TDI : M8 : input : : : 2 :
|
||||
VCCIO2 : M9 : power : : 3.3V : 2 :
|
||||
VCCINT : M10 : power : : 1.2V : :
|
||||
VCCINT : M11 : power : : 1.2V : :
|
||||
GND : M12 : gnd : : : :
|
||||
GND : M13 : gnd : : : :
|
||||
GND : M14 : gnd : : : :
|
||||
GND : M15 : gnd : : : :
|
||||
VCCINT : M16 : power : : 1.2V : :
|
||||
VCCINT : M17 : power : : 1.2V : :
|
||||
VCCIO5 : M18 : power : : 3.3V : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 5 :
|
||||
GND : M26 : gnd : : : :
|
||||
GND+ : N1 : : : : 2 :
|
||||
CLOCK_50 : N2 : input : 3.3-V LVTTL : : 2 : Y
|
||||
DATA0 : N3 : input : : : 2 :
|
||||
nCE : N4 : : : : 2 :
|
||||
VCCIO2 : N5 : power : : 3.3V : 2 :
|
||||
DCLK : N6 : : : : 2 :
|
||||
nCONFIG : N7 : : : : 2 :
|
||||
GND : N8 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 2 :
|
||||
VCCINT : N10 : power : : 1.2V : :
|
||||
GND : N11 : gnd : : : :
|
||||
GND : N12 : gnd : : : :
|
||||
GND : N13 : gnd : : : :
|
||||
GND : N14 : gnd : : : :
|
||||
GND : N15 : gnd : : : :
|
||||
GND : N16 : gnd : : : :
|
||||
VCCINT : N17 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 5 :
|
||||
GND : N19 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 5 :
|
||||
NC : N21 : : : : :
|
||||
VCCIO5 : N22 : power : : 3.3V : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 5 :
|
||||
GND+ : N25 : : : : 5 :
|
||||
GND+ : N26 : : : : 5 :
|
||||
GND+ : P1 : : : : 1 :
|
||||
GND+ : P2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 1 :
|
||||
VCCIO1 : P5 : power : : 3.3V : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P6 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P7 : : : : 1 :
|
||||
GND : P8 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 2 :
|
||||
VCCINT : P10 : power : : 1.2V : :
|
||||
GND : P11 : gnd : : : :
|
||||
GND : P12 : gnd : : : :
|
||||
GND : P13 : gnd : : : :
|
||||
GND : P14 : gnd : : : :
|
||||
GND : P15 : gnd : : : :
|
||||
GND : P16 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P17 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P18 : : : : 5 :
|
||||
GND : P19 : gnd : : : :
|
||||
MSEL0 : P20 : : : : 6 :
|
||||
MSEL1 : P21 : : : : 6 :
|
||||
VCCIO6 : P22 : power : : 3.3V : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P23 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P24 : : : : 6 :
|
||||
GND+ : P25 : : : : 6 :
|
||||
GND+ : P26 : : : : 6 :
|
||||
GND : R1 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 1 :
|
||||
VCCIO1 : R9 : power : : 3.3V : 1 :
|
||||
VCCINT : R10 : power : : 1.2V : :
|
||||
VCCINT : R11 : power : : 1.2V : :
|
||||
GND : R12 : gnd : : : :
|
||||
GND : R13 : gnd : : : :
|
||||
GND : R14 : gnd : : : :
|
||||
GND : R15 : gnd : : : :
|
||||
VCCINT : R16 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R17 : : : : 6 :
|
||||
VCCIO6 : R18 : power : : 3.3V : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 6 :
|
||||
GND : R21 : gnd : : : :
|
||||
nSTATUS : R22 : : : : 6 :
|
||||
CONF_DONE : R23 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 6 :
|
||||
GND : R26 : gnd : : : :
|
||||
VCCIO1 : T1 : power : : 3.3V : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 1 :
|
||||
GND : T5 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T10 : : : : 1 :
|
||||
VCCINT : T11 : power : : 1.2V : :
|
||||
GND : T12 : gnd : : : :
|
||||
GND : T13 : gnd : : : :
|
||||
GND : T14 : gnd : : : :
|
||||
GND : T15 : gnd : : : :
|
||||
VCCINT : T16 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T17 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 6 :
|
||||
VCCIO6 : T26 : power : : 3.3V : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 1 :
|
||||
GND : U8 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 1 :
|
||||
VCCINT : U11 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U12 : : : : 8 :
|
||||
VCCINT : U13 : power : : 1.2V : :
|
||||
VCCINT : U14 : power : : 1.2V : :
|
||||
VCCINT : U15 : power : : 1.2V : :
|
||||
VCCINT : U16 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U18 : : : : 7 :
|
||||
GND : U19 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 1 :
|
||||
VCCIO1 : V8 : power : : 3.3V : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 8 :
|
||||
VCCIO8 : V12 : power : : 3.3V : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 8 :
|
||||
VCCIO7 : V15 : power : : 3.3V : 7 :
|
||||
VCCINT : V16 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 7 :
|
||||
VCCIO6 : V19 : power : : 3.3V : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 1 :
|
||||
GND : W5 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 1 :
|
||||
GND_PLL1 : W7 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 8 :
|
||||
VCCIO8 : W9 : power : : 3.3V : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 8 :
|
||||
GND : W13 : gnd : : : :
|
||||
GND : W14 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 7 :
|
||||
VCCIO7 : W18 : power : : 3.3V : 7 :
|
||||
LEDG[2] : W19 : output : 3.3-V LVTTL : : 7 : Y
|
||||
GND_PLL4 : W20 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 6 :
|
||||
GND : W22 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W23 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W24 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 1 :
|
||||
NC : Y2 : : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 1 :
|
||||
GND_PLL1 : Y6 : gnd : : : :
|
||||
VCCD_PLL1 : Y7 : power : : 1.2V : :
|
||||
GNDA_PLL1 : Y8 : gnd : : : :
|
||||
GND : Y9 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 7 :
|
||||
GND : Y17 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 7 :
|
||||
GNDA_PLL4 : Y19 : gnd : : : :
|
||||
VCCD_PLL4 : Y20 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 6 :
|
||||
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Reference in New Issue
Block a user