Hochladen der vorherigen Laborübungen.
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1708005769472 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1708005769473 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 15 15:02:49 2024 " "Processing started: Thu Feb 15 15:02:49 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1708005769473 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1708005769473 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off counters_leds -c counters_leds " "Command: quartus_asm --read_settings_files=off --write_settings_files=off counters_leds -c counters_leds" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1708005769473 ""}
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{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1708005770518 ""}
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{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1708005770565 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4560 " "Peak virtual memory: 4560 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1708005771005 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 15 15:02:51 2024 " "Processing ended: Thu Feb 15 15:02:51 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1708005771005 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1708005771005 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1708005771005 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1708005771005 ""}
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<?xml version="1.0" ?>
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<LOG_ROOT>
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<PROJECT NAME="counters_leds">
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</PROJECT>
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</LOG_ROOT>
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v1
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Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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Version_Index = 302049280
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Creation_Time = Thu Feb 15 15:02:22 2024
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{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1708005764164 ""}
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{ "Info" "IMPP_MPP_USER_DEVICE" "counters_leds EP2C35F672C6 " "Selected device EP2C35F672C6 for design \"counters_leds\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1708005764173 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1708005764196 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1708005764196 ""}
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{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1708005764290 ""}
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{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1708005764301 ""}
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{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Device EP2C50F672C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1708005764746 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Device EP2C70F672C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1708005764746 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1708005764746 ""}
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{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ E3 " "Pin ~ASDO~ is reserved at location E3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/quartus/" { { 0 { 0 ""} 0 636 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1708005764753 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ D3 " "Pin ~nCSO~ is reserved at location D3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/quartus/" { { 0 { 0 ""} 0 637 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1708005764753 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS150p/nCEO~ AE24 " "Pin ~LVDS150p/nCEO~ is reserved at location AE24" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~LVDS150p/nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~LVDS150p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/quartus/" { { 0 { 0 ""} 0 638 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1708005764753 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1708005764753 ""}
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{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "counters_leds.sdc " "Synopsys Design Constraints File file not found: 'counters_leds.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1708005764944 ""}
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||||
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1708005764944 ""}
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||||
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1708005764946 ""}
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||||
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50 (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) " "Automatically promoted node CLOCK_50 (placed in PIN N2 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1708005764953 ""} } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "../src/counters_leds.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 4 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/quartus/" { { 0 { 0 ""} 0 16 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1708005764953 ""}
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||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1708005765002 ""}
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||||
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1708005765002 ""}
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||||
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1708005765002 ""}
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||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1708005765003 ""}
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||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1708005765004 ""}
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{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1708005765005 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1708005765005 ""}
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||||
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1708005765005 ""}
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||||
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1708005765012 ""}
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{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1708005765013 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1708005765013 ""}
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{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1708005765025 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1708005765025 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1708005765025 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1708005765025 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1708005765025 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1708005765025 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_27 " "Node \"CLOCK_27\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1708005765025 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1708005765025 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1708005765025 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1708005765025 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0Line truncated
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{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1708005765045 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1708005766281 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1708005766367 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1708005766376 ""}
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{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1708005766900 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1708005766901 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1708005766945 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X55_Y24 X65_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X55_Y24 to location X65_Y36" { } { { "loc" "" { Generic "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/quartus/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X55_Y24 to location X65_Y36"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X55_Y24 to location X65_Y36"} 55 24 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1708005767624 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1708005767624 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1708005767859 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1708005767861 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1708005767861 ""}
|
||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.13 " "Total time spent on timing analysis during the Fitter is 0.13 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1708005767873 ""}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1708005767875 ""}
|
||||
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "3 " "Found 3 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[0\] 0 " "Pin \"LEDG\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1708005767878 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[1\] 0 " "Pin \"LEDG\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1708005767878 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[2\] 0 " "Pin \"LEDG\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1708005767878 ""} } { } 0 306006 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "Fitter" 0 -1 1708005767878 ""}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1708005767947 ""}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1708005767956 ""}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1708005768032 ""}
|
||||
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1708005768285 ""}
|
||||
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1708005768358 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/quartus/output_files/counters_leds.fit.smsg " "Generated suppressed messages file C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/quartus/output_files/counters_leds.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1708005768455 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 426 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 426 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4876 " "Peak virtual memory: 4876 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1708005768585 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 15 15:02:48 2024 " "Processing ended: Thu Feb 15 15:02:48 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1708005768585 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1708005768585 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1708005768585 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1708005768585 ""}
|
||||
@@ -0,0 +1,211 @@
|
||||
|counters_leds
|
||||
CLOCK_50 => clk.IN7
|
||||
KEY[0] => rst.IN7
|
||||
LEDG[0] <= d_ff:d_ff_1.Q
|
||||
LEDG[1] <= d_ff:d_ff_2.Q
|
||||
LEDG[2] <= d_ff:d_ff_3.Q
|
||||
|
||||
|
||||
|counters_leds|mod_n_counter_10bit:div_1
|
||||
CLK => Q[0]~reg0.CLK
|
||||
CLK => Q[1]~reg0.CLK
|
||||
CLK => Q[2]~reg0.CLK
|
||||
CLK => Q[3]~reg0.CLK
|
||||
CLK => Q[4]~reg0.CLK
|
||||
CLK => Q[5]~reg0.CLK
|
||||
CLK => Q[6]~reg0.CLK
|
||||
CLK => Q[7]~reg0.CLK
|
||||
CLK => Q[8]~reg0.CLK
|
||||
CLK => Q[9]~reg0.CLK
|
||||
RST => Q[0]~reg0.ACLR
|
||||
RST => Q[1]~reg0.ACLR
|
||||
RST => Q[2]~reg0.ACLR
|
||||
RST => Q[3]~reg0.ACLR
|
||||
RST => Q[4]~reg0.ACLR
|
||||
RST => Q[5]~reg0.ACLR
|
||||
RST => Q[6]~reg0.ACLR
|
||||
RST => Q[7]~reg0.ACLR
|
||||
RST => Q[8]~reg0.ACLR
|
||||
RST => Q[9]~reg0.ACLR
|
||||
EN => Q[9]~reg0.ENA
|
||||
EN => Q[8]~reg0.ENA
|
||||
EN => Q[7]~reg0.ENA
|
||||
EN => Q[6]~reg0.ENA
|
||||
EN => Q[5]~reg0.ENA
|
||||
EN => Q[4]~reg0.ENA
|
||||
EN => Q[3]~reg0.ENA
|
||||
EN => Q[2]~reg0.ENA
|
||||
EN => Q[1]~reg0.ENA
|
||||
EN => Q[0]~reg0.ENA
|
||||
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
TC <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|mod_n_counter_10bit:div_2
|
||||
CLK => Q[0]~reg0.CLK
|
||||
CLK => Q[1]~reg0.CLK
|
||||
CLK => Q[2]~reg0.CLK
|
||||
CLK => Q[3]~reg0.CLK
|
||||
CLK => Q[4]~reg0.CLK
|
||||
CLK => Q[5]~reg0.CLK
|
||||
CLK => Q[6]~reg0.CLK
|
||||
CLK => Q[7]~reg0.CLK
|
||||
CLK => Q[8]~reg0.CLK
|
||||
CLK => Q[9]~reg0.CLK
|
||||
RST => Q[0]~reg0.ACLR
|
||||
RST => Q[1]~reg0.ACLR
|
||||
RST => Q[2]~reg0.ACLR
|
||||
RST => Q[3]~reg0.ACLR
|
||||
RST => Q[4]~reg0.ACLR
|
||||
RST => Q[5]~reg0.ACLR
|
||||
RST => Q[6]~reg0.ACLR
|
||||
RST => Q[7]~reg0.ACLR
|
||||
RST => Q[8]~reg0.ACLR
|
||||
RST => Q[9]~reg0.ACLR
|
||||
EN => Q[9]~reg0.ENA
|
||||
EN => Q[8]~reg0.ENA
|
||||
EN => Q[7]~reg0.ENA
|
||||
EN => Q[6]~reg0.ENA
|
||||
EN => Q[5]~reg0.ENA
|
||||
EN => Q[4]~reg0.ENA
|
||||
EN => Q[3]~reg0.ENA
|
||||
EN => Q[2]~reg0.ENA
|
||||
EN => Q[1]~reg0.ENA
|
||||
EN => Q[0]~reg0.ENA
|
||||
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
TC <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|mod_n_counter_10bit:div_3
|
||||
CLK => Q[0]~reg0.CLK
|
||||
CLK => Q[1]~reg0.CLK
|
||||
CLK => Q[2]~reg0.CLK
|
||||
CLK => Q[3]~reg0.CLK
|
||||
CLK => Q[4]~reg0.CLK
|
||||
CLK => Q[5]~reg0.CLK
|
||||
CLK => Q[6]~reg0.CLK
|
||||
CLK => Q[7]~reg0.CLK
|
||||
CLK => Q[8]~reg0.CLK
|
||||
CLK => Q[9]~reg0.CLK
|
||||
RST => Q[0]~reg0.ACLR
|
||||
RST => Q[1]~reg0.ACLR
|
||||
RST => Q[2]~reg0.ACLR
|
||||
RST => Q[3]~reg0.ACLR
|
||||
RST => Q[4]~reg0.ACLR
|
||||
RST => Q[5]~reg0.ACLR
|
||||
RST => Q[6]~reg0.ACLR
|
||||
RST => Q[7]~reg0.ACLR
|
||||
RST => Q[8]~reg0.ACLR
|
||||
RST => Q[9]~reg0.ACLR
|
||||
EN => Q[0]~reg0.ENA
|
||||
EN => Q[9]~reg0.ENA
|
||||
EN => Q[8]~reg0.ENA
|
||||
EN => Q[7]~reg0.ENA
|
||||
EN => Q[6]~reg0.ENA
|
||||
EN => Q[5]~reg0.ENA
|
||||
EN => Q[4]~reg0.ENA
|
||||
EN => Q[3]~reg0.ENA
|
||||
EN => Q[2]~reg0.ENA
|
||||
EN => Q[1]~reg0.ENA
|
||||
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
TC <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|mod_n_counter_10bit:div_4
|
||||
CLK => Q[0]~reg0.CLK
|
||||
CLK => Q[1]~reg0.CLK
|
||||
CLK => Q[2]~reg0.CLK
|
||||
CLK => Q[3]~reg0.CLK
|
||||
CLK => Q[4]~reg0.CLK
|
||||
CLK => Q[5]~reg0.CLK
|
||||
CLK => Q[6]~reg0.CLK
|
||||
CLK => Q[7]~reg0.CLK
|
||||
CLK => Q[8]~reg0.CLK
|
||||
CLK => Q[9]~reg0.CLK
|
||||
RST => Q[0]~reg0.ACLR
|
||||
RST => Q[1]~reg0.ACLR
|
||||
RST => Q[2]~reg0.ACLR
|
||||
RST => Q[3]~reg0.ACLR
|
||||
RST => Q[4]~reg0.ACLR
|
||||
RST => Q[5]~reg0.ACLR
|
||||
RST => Q[6]~reg0.ACLR
|
||||
RST => Q[7]~reg0.ACLR
|
||||
RST => Q[8]~reg0.ACLR
|
||||
RST => Q[9]~reg0.ACLR
|
||||
EN => Q[0]~reg0.ENA
|
||||
EN => Q[9]~reg0.ENA
|
||||
EN => Q[8]~reg0.ENA
|
||||
EN => Q[7]~reg0.ENA
|
||||
EN => Q[6]~reg0.ENA
|
||||
EN => Q[5]~reg0.ENA
|
||||
EN => Q[4]~reg0.ENA
|
||||
EN => Q[3]~reg0.ENA
|
||||
EN => Q[2]~reg0.ENA
|
||||
EN => Q[1]~reg0.ENA
|
||||
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
TC <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|d_ff:d_ff_1
|
||||
D => Q~reg0.DATAIN
|
||||
CLK => Q~reg0.CLK
|
||||
RST => Q~reg0.ACLR
|
||||
ENA => Q~reg0.ENA
|
||||
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Qn <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|d_ff:d_ff_2
|
||||
D => Q~reg0.DATAIN
|
||||
CLK => Q~reg0.CLK
|
||||
RST => Q~reg0.ACLR
|
||||
ENA => Q~reg0.ENA
|
||||
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Qn <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|d_ff:d_ff_3
|
||||
D => Q~reg0.DATAIN
|
||||
CLK => Q~reg0.CLK
|
||||
RST => Q~reg0.ACLR
|
||||
ENA => Q~reg0.ENA
|
||||
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Qn <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,130 @@
|
||||
<TABLE>
|
||||
<TR bgcolor="#C0C0C0">
|
||||
<TH>Hierarchy</TH>
|
||||
<TH>Input</TH>
|
||||
<TH>Constant Input</TH>
|
||||
<TH>Unused Input</TH>
|
||||
<TH>Floating Input</TH>
|
||||
<TH>Output</TH>
|
||||
<TH>Constant Output</TH>
|
||||
<TH>Unused Output</TH>
|
||||
<TH>Floating Output</TH>
|
||||
<TH>Bidir</TH>
|
||||
<TH>Constant Bidir</TH>
|
||||
<TH>Unused Bidir</TH>
|
||||
<TH>Input only Bidir</TH>
|
||||
<TH>Output only Bidir</TH>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >d_ff_3</TD>
|
||||
<TD >4</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >d_ff_2</TD>
|
||||
<TD >4</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >d_ff_1</TD>
|
||||
<TD >4</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >div_4</TD>
|
||||
<TD >3</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >11</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >div_3</TD>
|
||||
<TD >3</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >11</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >div_2</TD>
|
||||
<TD >3</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >11</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >div_1</TD>
|
||||
<TD >3</TD>
|
||||
<TD >1</TD>
|
||||
<TD >0</TD>
|
||||
<TD >1</TD>
|
||||
<TD >11</TD>
|
||||
<TD >1</TD>
|
||||
<TD >1</TD>
|
||||
<TD >1</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
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|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Legal Partition Candidates ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; d_ff_3 ; 4 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; d_ff_2 ; 4 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; d_ff_1 ; 4 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; div_4 ; 3 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; div_3 ; 3 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; div_2 ; 3 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; div_1 ; 3 ; 1 ; 0 ; 1 ; 11 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
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|
||||
v1
|
||||
@@ -0,0 +1,18 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1708005761629 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1708005761630 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 15 15:02:41 2024 " "Processing started: Thu Feb 15 15:02:41 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1708005761630 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1708005761630 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off counters_leds -c counters_leds " "Command: quartus_map --read_settings_files=on --write_settings_files=off counters_leds -c counters_leds" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1708005761630 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1708005762025 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/mod_n_counter_10bit.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/mod_n_counter_10bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 mod_n_counter_10bit " "Found entity 1: mod_n_counter_10bit" { } { { "../src/mod_n_counter_10bit.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/mod_n_counter_10bit.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1708005762108 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1708005762108 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/d_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/d_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 d_ff " "Found entity 1: d_ff" { } { { "../src/d_ff.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/d_ff.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1708005762112 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1708005762112 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/counters_leds.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/counters_leds.v" { { "Info" "ISGN_ENTITY_NAME" "1 counters_leds " "Found entity 1: counters_leds" { } { { "../src/counters_leds.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1708005762115 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1708005762115 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "en_ff_1 counters_leds.v(60) " "Verilog HDL Implicit Net warning at counters_leds.v(60): created implicit net for \"en_ff_1\"" { } { { "../src/counters_leds.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 60 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1708005762116 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "en_ff_2 counters_leds.v(61) " "Verilog HDL Implicit Net warning at counters_leds.v(61): created implicit net for \"en_ff_2\"" { } { { "../src/counters_leds.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 61 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1708005762116 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "en_ff_3 counters_leds.v(62) " "Verilog HDL Implicit Net warning at counters_leds.v(62): created implicit net for \"en_ff_3\"" { } { { "../src/counters_leds.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 62 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1708005762116 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "counters_leds " "Elaborating entity \"counters_leds\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1708005762154 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mod_n_counter_10bit mod_n_counter_10bit:div_1 " "Elaborating entity \"mod_n_counter_10bit\" for hierarchy \"mod_n_counter_10bit:div_1\"" { } { { "../src/counters_leds.v" "div_1" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 71 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1708005762188 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mod_n_counter_10bit mod_n_counter_10bit:div_3 " "Elaborating entity \"mod_n_counter_10bit\" for hierarchy \"mod_n_counter_10bit:div_3\"" { } { { "../src/counters_leds.v" "div_3" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 89 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1708005762194 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mod_n_counter_10bit mod_n_counter_10bit:div_4 " "Elaborating entity \"mod_n_counter_10bit\" for hierarchy \"mod_n_counter_10bit:div_4\"" { } { { "../src/counters_leds.v" "div_4" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 98 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1708005762198 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d_ff d_ff:d_ff_1 " "Elaborating entity \"d_ff\" for hierarchy \"d_ff:d_ff_1\"" { } { { "../src/counters_leds.v" "d_ff_1" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 108 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1708005762201 ""}
|
||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1708005762907 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1708005762907 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "79 " "Implemented 79 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1708005762979 ""} { "Info" "ICUT_CUT_TM_OPINS" "3 " "Implemented 3 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1708005762979 ""} { "Info" "ICUT_CUT_TM_LCELLS" "74 " "Implemented 74 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1708005762979 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1708005762979 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4602 " "Peak virtual memory: 4602 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1708005763008 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 15 15:02:43 2024 " "Processing ended: Thu Feb 15 15:02:43 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1708005763008 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1708005763008 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1708005763008 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1708005763008 ""}
|
||||
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|
||||
v1
|
||||
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|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1708005776992 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 64-Bit " "Running Quartus II 64-Bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1708005776993 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 15 15:02:56 2024 " "Processing started: Thu Feb 15 15:02:56 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1708005776993 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1708005776993 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp counters_leds -c counters_leds --netlist_type=sgate " "Command: quartus_rpp counters_leds -c counters_leds --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1708005776993 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4428 " "Peak virtual memory: 4428 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1708005777034 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 15 15:02:57 2024 " "Processing ended: Thu Feb 15 15:02:57 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1708005777034 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1708005777034 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1708005777034 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1708005777034 ""}
|
||||
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|
||||
DONE
|
||||
@@ -0,0 +1,30 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1708005772017 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772017 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 15 15:02:51 2024 " "Processing started: Thu Feb 15 15:02:51 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1708005772017 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1708005772017 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta counters_leds -c counters_leds " "Command: quartus_sta counters_leds -c counters_leds" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1708005772018 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1708005772106 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1708005772259 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1708005772289 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1708005772289 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "counters_leds.sdc " "Synopsys Design Constraints File file not found: 'counters_leds.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1708005772362 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1708005772363 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772363 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772363 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1708005772365 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1708005772378 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1708005772383 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.423 " "Worst-case setup slack is -2.423" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772385 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772385 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.423 -80.978 CLOCK_50 " " -2.423 -80.978 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772385 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772385 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.391 " "Worst-case hold slack is 0.391" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772388 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772388 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.391 0.000 CLOCK_50 " " 0.391 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772388 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772388 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1708005772392 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1708005772394 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772397 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772397 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -44.380 CLOCK_50 " " -1.380 -44.380 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772397 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772397 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1708005772419 ""}
|
||||
{ "Info" "0" "" "Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1708005772421 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1708005772429 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.652 " "Worst-case setup slack is -0.652" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772432 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772432 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.652 -17.377 CLOCK_50 " " -0.652 -17.377 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772432 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772432 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.215 " "Worst-case hold slack is 0.215" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.215 0.000 CLOCK_50 " " 0.215 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772436 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772436 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1708005772439 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1708005772443 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772446 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772446 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -44.380 CLOCK_50 " " -1.380 -44.380 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772446 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772446 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1708005772471 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1708005772493 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1708005772493 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4544 " "Peak virtual memory: 4544 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1708005772554 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 15 15:02:52 2024 " "Processing ended: Thu Feb 15 15:02:52 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1708005772554 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1708005772554 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1708005772554 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1708005772554 ""}
|
||||
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|
||||
start_full_compilation:s:00:00:12
|
||||
start_analysis_synthesis:s:00:00:02-start_full_compilation
|
||||
start_analysis_elaboration:s-start_full_compilation
|
||||
start_fitter:s:00:00:06-start_full_compilation
|
||||
start_assembler:s:00:00:02-start_full_compilation
|
||||
start_timing_analyzer:s:00:00:02-start_full_compilation
|
||||
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Reference in new issue
Block a user