Hochladen der vorherigen Laborübungen.
Die Dateien selbst wurden nicht verändert.
This commit is contained in:
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1708005769472 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1708005769473 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 15 15:02:49 2024 " "Processing started: Thu Feb 15 15:02:49 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1708005769473 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1708005769473 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off counters_leds -c counters_leds " "Command: quartus_asm --read_settings_files=off --write_settings_files=off counters_leds -c counters_leds" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1708005769473 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1708005770518 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1708005770565 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4560 " "Peak virtual memory: 4560 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1708005771005 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 15 15:02:51 2024 " "Processing ended: Thu Feb 15 15:02:51 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1708005771005 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1708005771005 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1708005771005 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1708005771005 ""}
|
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<?xml version="1.0" ?>
|
||||
<LOG_ROOT>
|
||||
<PROJECT NAME="counters_leds">
|
||||
</PROJECT>
|
||||
</LOG_ROOT>
|
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v1
|
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Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
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Version_Index = 302049280
|
||||
Creation_Time = Thu Feb 15 15:02:22 2024
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|
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|counters_leds
|
||||
CLOCK_50 => clk.IN7
|
||||
KEY[0] => rst.IN7
|
||||
LEDG[0] <= d_ff:d_ff_1.Q
|
||||
LEDG[1] <= d_ff:d_ff_2.Q
|
||||
LEDG[2] <= d_ff:d_ff_3.Q
|
||||
|
||||
|
||||
|counters_leds|mod_n_counter_10bit:div_1
|
||||
CLK => Q[0]~reg0.CLK
|
||||
CLK => Q[1]~reg0.CLK
|
||||
CLK => Q[2]~reg0.CLK
|
||||
CLK => Q[3]~reg0.CLK
|
||||
CLK => Q[4]~reg0.CLK
|
||||
CLK => Q[5]~reg0.CLK
|
||||
CLK => Q[6]~reg0.CLK
|
||||
CLK => Q[7]~reg0.CLK
|
||||
CLK => Q[8]~reg0.CLK
|
||||
CLK => Q[9]~reg0.CLK
|
||||
RST => Q[0]~reg0.ACLR
|
||||
RST => Q[1]~reg0.ACLR
|
||||
RST => Q[2]~reg0.ACLR
|
||||
RST => Q[3]~reg0.ACLR
|
||||
RST => Q[4]~reg0.ACLR
|
||||
RST => Q[5]~reg0.ACLR
|
||||
RST => Q[6]~reg0.ACLR
|
||||
RST => Q[7]~reg0.ACLR
|
||||
RST => Q[8]~reg0.ACLR
|
||||
RST => Q[9]~reg0.ACLR
|
||||
EN => Q[9]~reg0.ENA
|
||||
EN => Q[8]~reg0.ENA
|
||||
EN => Q[7]~reg0.ENA
|
||||
EN => Q[6]~reg0.ENA
|
||||
EN => Q[5]~reg0.ENA
|
||||
EN => Q[4]~reg0.ENA
|
||||
EN => Q[3]~reg0.ENA
|
||||
EN => Q[2]~reg0.ENA
|
||||
EN => Q[1]~reg0.ENA
|
||||
EN => Q[0]~reg0.ENA
|
||||
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
TC <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|mod_n_counter_10bit:div_2
|
||||
CLK => Q[0]~reg0.CLK
|
||||
CLK => Q[1]~reg0.CLK
|
||||
CLK => Q[2]~reg0.CLK
|
||||
CLK => Q[3]~reg0.CLK
|
||||
CLK => Q[4]~reg0.CLK
|
||||
CLK => Q[5]~reg0.CLK
|
||||
CLK => Q[6]~reg0.CLK
|
||||
CLK => Q[7]~reg0.CLK
|
||||
CLK => Q[8]~reg0.CLK
|
||||
CLK => Q[9]~reg0.CLK
|
||||
RST => Q[0]~reg0.ACLR
|
||||
RST => Q[1]~reg0.ACLR
|
||||
RST => Q[2]~reg0.ACLR
|
||||
RST => Q[3]~reg0.ACLR
|
||||
RST => Q[4]~reg0.ACLR
|
||||
RST => Q[5]~reg0.ACLR
|
||||
RST => Q[6]~reg0.ACLR
|
||||
RST => Q[7]~reg0.ACLR
|
||||
RST => Q[8]~reg0.ACLR
|
||||
RST => Q[9]~reg0.ACLR
|
||||
EN => Q[9]~reg0.ENA
|
||||
EN => Q[8]~reg0.ENA
|
||||
EN => Q[7]~reg0.ENA
|
||||
EN => Q[6]~reg0.ENA
|
||||
EN => Q[5]~reg0.ENA
|
||||
EN => Q[4]~reg0.ENA
|
||||
EN => Q[3]~reg0.ENA
|
||||
EN => Q[2]~reg0.ENA
|
||||
EN => Q[1]~reg0.ENA
|
||||
EN => Q[0]~reg0.ENA
|
||||
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
TC <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|mod_n_counter_10bit:div_3
|
||||
CLK => Q[0]~reg0.CLK
|
||||
CLK => Q[1]~reg0.CLK
|
||||
CLK => Q[2]~reg0.CLK
|
||||
CLK => Q[3]~reg0.CLK
|
||||
CLK => Q[4]~reg0.CLK
|
||||
CLK => Q[5]~reg0.CLK
|
||||
CLK => Q[6]~reg0.CLK
|
||||
CLK => Q[7]~reg0.CLK
|
||||
CLK => Q[8]~reg0.CLK
|
||||
CLK => Q[9]~reg0.CLK
|
||||
RST => Q[0]~reg0.ACLR
|
||||
RST => Q[1]~reg0.ACLR
|
||||
RST => Q[2]~reg0.ACLR
|
||||
RST => Q[3]~reg0.ACLR
|
||||
RST => Q[4]~reg0.ACLR
|
||||
RST => Q[5]~reg0.ACLR
|
||||
RST => Q[6]~reg0.ACLR
|
||||
RST => Q[7]~reg0.ACLR
|
||||
RST => Q[8]~reg0.ACLR
|
||||
RST => Q[9]~reg0.ACLR
|
||||
EN => Q[0]~reg0.ENA
|
||||
EN => Q[9]~reg0.ENA
|
||||
EN => Q[8]~reg0.ENA
|
||||
EN => Q[7]~reg0.ENA
|
||||
EN => Q[6]~reg0.ENA
|
||||
EN => Q[5]~reg0.ENA
|
||||
EN => Q[4]~reg0.ENA
|
||||
EN => Q[3]~reg0.ENA
|
||||
EN => Q[2]~reg0.ENA
|
||||
EN => Q[1]~reg0.ENA
|
||||
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
TC <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|mod_n_counter_10bit:div_4
|
||||
CLK => Q[0]~reg0.CLK
|
||||
CLK => Q[1]~reg0.CLK
|
||||
CLK => Q[2]~reg0.CLK
|
||||
CLK => Q[3]~reg0.CLK
|
||||
CLK => Q[4]~reg0.CLK
|
||||
CLK => Q[5]~reg0.CLK
|
||||
CLK => Q[6]~reg0.CLK
|
||||
CLK => Q[7]~reg0.CLK
|
||||
CLK => Q[8]~reg0.CLK
|
||||
CLK => Q[9]~reg0.CLK
|
||||
RST => Q[0]~reg0.ACLR
|
||||
RST => Q[1]~reg0.ACLR
|
||||
RST => Q[2]~reg0.ACLR
|
||||
RST => Q[3]~reg0.ACLR
|
||||
RST => Q[4]~reg0.ACLR
|
||||
RST => Q[5]~reg0.ACLR
|
||||
RST => Q[6]~reg0.ACLR
|
||||
RST => Q[7]~reg0.ACLR
|
||||
RST => Q[8]~reg0.ACLR
|
||||
RST => Q[9]~reg0.ACLR
|
||||
EN => Q[0]~reg0.ENA
|
||||
EN => Q[9]~reg0.ENA
|
||||
EN => Q[8]~reg0.ENA
|
||||
EN => Q[7]~reg0.ENA
|
||||
EN => Q[6]~reg0.ENA
|
||||
EN => Q[5]~reg0.ENA
|
||||
EN => Q[4]~reg0.ENA
|
||||
EN => Q[3]~reg0.ENA
|
||||
EN => Q[2]~reg0.ENA
|
||||
EN => Q[1]~reg0.ENA
|
||||
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
TC <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|d_ff:d_ff_1
|
||||
D => Q~reg0.DATAIN
|
||||
CLK => Q~reg0.CLK
|
||||
RST => Q~reg0.ACLR
|
||||
ENA => Q~reg0.ENA
|
||||
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Qn <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|d_ff:d_ff_2
|
||||
D => Q~reg0.DATAIN
|
||||
CLK => Q~reg0.CLK
|
||||
RST => Q~reg0.ACLR
|
||||
ENA => Q~reg0.ENA
|
||||
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Qn <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|d_ff:d_ff_3
|
||||
D => Q~reg0.DATAIN
|
||||
CLK => Q~reg0.CLK
|
||||
RST => Q~reg0.ACLR
|
||||
ENA => Q~reg0.ENA
|
||||
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Qn <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
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|
||||
<TABLE>
|
||||
<TR bgcolor="#C0C0C0">
|
||||
<TH>Hierarchy</TH>
|
||||
<TH>Input</TH>
|
||||
<TH>Constant Input</TH>
|
||||
<TH>Unused Input</TH>
|
||||
<TH>Floating Input</TH>
|
||||
<TH>Output</TH>
|
||||
<TH>Constant Output</TH>
|
||||
<TH>Unused Output</TH>
|
||||
<TH>Floating Output</TH>
|
||||
<TH>Bidir</TH>
|
||||
<TH>Constant Bidir</TH>
|
||||
<TH>Unused Bidir</TH>
|
||||
<TH>Input only Bidir</TH>
|
||||
<TH>Output only Bidir</TH>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >d_ff_3</TD>
|
||||
<TD >4</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >d_ff_2</TD>
|
||||
<TD >4</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >d_ff_1</TD>
|
||||
<TD >4</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >div_4</TD>
|
||||
<TD >3</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >11</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >div_3</TD>
|
||||
<TD >3</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >11</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >div_2</TD>
|
||||
<TD >3</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >11</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >div_1</TD>
|
||||
<TD >3</TD>
|
||||
<TD >1</TD>
|
||||
<TD >0</TD>
|
||||
<TD >1</TD>
|
||||
<TD >11</TD>
|
||||
<TD >1</TD>
|
||||
<TD >1</TD>
|
||||
<TD >1</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
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@@ -0,0 +1,13 @@
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Legal Partition Candidates ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; d_ff_3 ; 4 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; d_ff_2 ; 4 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; d_ff_1 ; 4 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; div_4 ; 3 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; div_3 ; 3 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; div_2 ; 3 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; div_1 ; 3 ; 1 ; 0 ; 1 ; 11 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
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|
||||
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|
||||
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|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1708005761629 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1708005761630 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 15 15:02:41 2024 " "Processing started: Thu Feb 15 15:02:41 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1708005761630 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1708005761630 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off counters_leds -c counters_leds " "Command: quartus_map --read_settings_files=on --write_settings_files=off counters_leds -c counters_leds" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1708005761630 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1708005762025 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/mod_n_counter_10bit.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/mod_n_counter_10bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 mod_n_counter_10bit " "Found entity 1: mod_n_counter_10bit" { } { { "../src/mod_n_counter_10bit.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/mod_n_counter_10bit.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1708005762108 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1708005762108 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/d_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/d_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 d_ff " "Found entity 1: d_ff" { } { { "../src/d_ff.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/d_ff.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1708005762112 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1708005762112 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/counters_leds.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/counters_leds.v" { { "Info" "ISGN_ENTITY_NAME" "1 counters_leds " "Found entity 1: counters_leds" { } { { "../src/counters_leds.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1708005762115 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1708005762115 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "en_ff_1 counters_leds.v(60) " "Verilog HDL Implicit Net warning at counters_leds.v(60): created implicit net for \"en_ff_1\"" { } { { "../src/counters_leds.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 60 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1708005762116 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "en_ff_2 counters_leds.v(61) " "Verilog HDL Implicit Net warning at counters_leds.v(61): created implicit net for \"en_ff_2\"" { } { { "../src/counters_leds.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 61 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1708005762116 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "en_ff_3 counters_leds.v(62) " "Verilog HDL Implicit Net warning at counters_leds.v(62): created implicit net for \"en_ff_3\"" { } { { "../src/counters_leds.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 62 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1708005762116 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "counters_leds " "Elaborating entity \"counters_leds\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1708005762154 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mod_n_counter_10bit mod_n_counter_10bit:div_1 " "Elaborating entity \"mod_n_counter_10bit\" for hierarchy \"mod_n_counter_10bit:div_1\"" { } { { "../src/counters_leds.v" "div_1" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 71 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1708005762188 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mod_n_counter_10bit mod_n_counter_10bit:div_3 " "Elaborating entity \"mod_n_counter_10bit\" for hierarchy \"mod_n_counter_10bit:div_3\"" { } { { "../src/counters_leds.v" "div_3" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 89 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1708005762194 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mod_n_counter_10bit mod_n_counter_10bit:div_4 " "Elaborating entity \"mod_n_counter_10bit\" for hierarchy \"mod_n_counter_10bit:div_4\"" { } { { "../src/counters_leds.v" "div_4" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 98 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1708005762198 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d_ff d_ff:d_ff_1 " "Elaborating entity \"d_ff\" for hierarchy \"d_ff:d_ff_1\"" { } { { "../src/counters_leds.v" "d_ff_1" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 108 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1708005762201 ""}
|
||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1708005762907 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1708005762907 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "79 " "Implemented 79 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1708005762979 ""} { "Info" "ICUT_CUT_TM_OPINS" "3 " "Implemented 3 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1708005762979 ""} { "Info" "ICUT_CUT_TM_LCELLS" "74 " "Implemented 74 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1708005762979 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1708005762979 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4602 " "Peak virtual memory: 4602 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1708005763008 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 15 15:02:43 2024 " "Processing ended: Thu Feb 15 15:02:43 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1708005763008 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1708005763008 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1708005763008 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1708005763008 ""}
|
||||
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|
||||
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|
||||
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|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1708005776992 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 64-Bit " "Running Quartus II 64-Bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1708005776993 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 15 15:02:56 2024 " "Processing started: Thu Feb 15 15:02:56 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1708005776993 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1708005776993 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp counters_leds -c counters_leds --netlist_type=sgate " "Command: quartus_rpp counters_leds -c counters_leds --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1708005776993 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4428 " "Peak virtual memory: 4428 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1708005777034 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 15 15:02:57 2024 " "Processing ended: Thu Feb 15 15:02:57 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1708005777034 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1708005777034 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1708005777034 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1708005777034 ""}
|
||||
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|
||||
DONE
|
||||
@@ -0,0 +1,30 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1708005772017 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772017 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 15 15:02:51 2024 " "Processing started: Thu Feb 15 15:02:51 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1708005772017 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1708005772017 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta counters_leds -c counters_leds " "Command: quartus_sta counters_leds -c counters_leds" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1708005772018 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1708005772106 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1708005772259 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1708005772289 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1708005772289 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "counters_leds.sdc " "Synopsys Design Constraints File file not found: 'counters_leds.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1708005772362 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1708005772363 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772363 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772363 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1708005772365 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1708005772378 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1708005772383 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.423 " "Worst-case setup slack is -2.423" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772385 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772385 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.423 -80.978 CLOCK_50 " " -2.423 -80.978 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772385 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772385 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.391 " "Worst-case hold slack is 0.391" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772388 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772388 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.391 0.000 CLOCK_50 " " 0.391 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772388 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772388 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1708005772392 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1708005772394 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772397 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772397 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -44.380 CLOCK_50 " " -1.380 -44.380 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772397 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772397 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1708005772419 ""}
|
||||
{ "Info" "0" "" "Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1708005772421 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1708005772429 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.652 " "Worst-case setup slack is -0.652" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772432 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772432 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.652 -17.377 CLOCK_50 " " -0.652 -17.377 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772432 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772432 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.215 " "Worst-case hold slack is 0.215" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.215 0.000 CLOCK_50 " " 0.215 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772436 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772436 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1708005772439 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1708005772443 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772446 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772446 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -44.380 CLOCK_50 " " -1.380 -44.380 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1708005772446 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1708005772446 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1708005772471 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1708005772493 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1708005772493 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4544 " "Peak virtual memory: 4544 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1708005772554 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 15 15:02:52 2024 " "Processing ended: Thu Feb 15 15:02:52 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1708005772554 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1708005772554 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1708005772554 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1708005772554 ""}
|
||||
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|
||||
start_full_compilation:s:00:00:12
|
||||
start_analysis_synthesis:s:00:00:02-start_full_compilation
|
||||
start_analysis_elaboration:s-start_full_compilation
|
||||
start_fitter:s:00:00:06-start_full_compilation
|
||||
start_assembler:s:00:00:02-start_full_compilation
|
||||
start_timing_analyzer:s:00:00:02-start_full_compilation
|
||||
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Reference in New Issue
Block a user