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labor_2/counters_leds/src/counters_leds.v

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+// counters_leds
+module counters_leds (
+
+input CLOCK_50,
+input [0:0] KEY,
+output [2:0] LEDG
+
+);
+
+// Divider values with option for fast simulation
+//`define SIMULATION
+
+`ifndef SIMULATION
+  localparam DIVVAL_1 = 1000;
+  localparam DIVVAL_2 = 1000;
+  localparam DIVVAL_3 = 25;
+  localparam DIVVAL_4 = 5;
+`else
+  localparam DIVVAL_1 = 5;
+  localparam DIVVAL_2 = 5;
+  localparam DIVVAL_3 = 4;
+  localparam DIVVAL_4 = 3;
+`endif
+
+// Wire definitions 
+wire clk;
+wire rst;
+
+wire [9:0] q_tb_div_1;
+wire [9:0] q_tb_div_2;
+wire [9:0] q_tb_div_3;
+wire [9:0] q_tb_div_4;
+
+wire tc_div_1;
+wire tc_div_2;  
+wire tc_div_3;  
+wire tc_div_4;  
+
+wire en_div_1;
+wire en_div_2;
+wire en_div_3;
+wire en_div_4;
+
+wire [2:0] q;
+
+assign LEDG[0] = q[0];
+assign LEDG[1] = q[1];
+assign LEDG[2] = q[2];
+
+wire [2:0] q_n;
+
+assign clk = CLOCK_50;
+assign rst = ~KEY[0];
+
+assign en_div_1 = 1'b1;
+assign en_div_2 = tc_div_1;
+assign en_div_3 = tc_div_1 & tc_div_2;
+assign en_div_4 = tc_div_3 & en_div_3;
+
+assign en_ff_1 = tc_div_1 & tc_div_2;
+assign en_ff_2 = tc_div_3 & en_div_3;
+assign en_ff_3 = tc_div_4 & en_div_4;
+
+// instance of div_1
+mod_n_counter_10bit #(.N(DIVVAL_1)) div_1(
+  .CLK(clk),
+  .RST(rst),
+  .EN(en_div_1),
+  .Q(q_tb_div_1),
+  .TC(tc_div_1)
+);
+
+// instance of div_2
+mod_n_counter_10bit #(.N(DIVVAL_2)) div_2(
+  .CLK(clk),
+  .RST(rst),
+  .EN(en_div_2),
+  .Q(q_tb_div_2),
+  .TC(tc_div_2)
+);
+
+// instance of div_3
+mod_n_counter_10bit #(.N(DIVVAL_3)) div_3(
+  .CLK(clk),
+  .RST(rst),
+  .EN(en_div_3),
+  .Q(q_tb_div_3),
+  .TC(tc_div_3)
+);
+
+// instance of div_4
+mod_n_counter_10bit #(.N(DIVVAL_4)) div_4(
+  .CLK(clk),
+  .RST(rst),
+  .EN(en_div_4),
+  .Q(q_tb_div_4),
+  .TC(tc_div_4)
+);
+
+// instance of d_ff_1
+d_ff d_ff_1(
+  .D(q_n[0]),
+  .CLK(clk),
+  .RST(rst),
+  .ENA(en_ff_1),
+  .Q(q[0]),
+  .Qn(q_n[0])
+);
+// LEDG[0] 25 Hz
+
+// instance of d_ff_2
+d_ff d_ff_2(
+  .D(q_n[1]),
+  .CLK(clk),
+  .RST(rst),
+  .ENA(en_ff_2),
+  .Q(q[1]),
+  .Qn(q_n[1])
+);
+// LEDG[1] 1 Hz
+
+// instance of d_ff_3
+d_ff d_ff_3(
+  .D(q_n[2]),
+  .CLK(clk),
+  .RST(rst),
+  .ENA(en_ff_3),
+  .Q(q[2]),
+  .Qn(q_n[2])
+);
+// LEDG[2] 0.2 Hz
+
+endmodule

labor_2/counters_leds/src/counters_leds_template.v

@@ -0,0 +1,66 @@
+// counters_leds
+module counters_leds (
+
+input CLOCK_50,
+input [0:0] KEY,
+output [2:0] LEDG
+
+);
+
+// Divider values with option for fast simulation
+//`define SIMULATION
+
+`ifndef SIMULATION
+  localparam DIVVAL_1 = ???;
+  localparam DIVVAL_2 = ???;
+  localparam DIVVAL_3 = ???;
+  localparam DIVVAL_4 = ???;
+`else
+  localparam DIVVAL_1 = 5;
+  localparam DIVVAL_2 = 5;
+  localparam DIVVAL_3 = 4;
+  localparam DIVVAL_4 = 3;
+`endif
+
+// Wire definitions 
+wire clk;
+wire rst;
+
+wire tc_div_1;
+wire tc_div_2;  
+wire tc_div_3;  
+wire tc_div_4;  
+
+wire en_div_3;
+wire en_div_4;
+
+wire [2:0] q_n;
+
+assign clk = CLOCK_50;
+assign rst = ~KEY[0];
+
+assign en_div_3 = ...;
+assign en_div_4 = ...;
+
+assign en_ff_1 = ...;
+assign en_ff_2 = ...;
+assign en_ff_3 = ...;
+
+// instance of div_1
+
+// instance of div_2
+
+// instance of div_3
+
+// instance of div_4
+
+// instance of d_ff_1
+// LEDG[0] 25 Hz
+
+// instance of d_ff_2
+// LEDG[1] 1 Hz
+
+// instance of d_ff_3
+// LEDG[2] 0.2 Hz
+
+endmodule

labor_2/counters_leds/src/d_ff.v

@@ -0,0 +1,26 @@
+module d_ff(
+	// module inputs
+	D, // Data inputs
+	CLK, // Clock inputs
+	RST,
+	ENA,
+	// module outputs
+	Q, // Noninverting data outputs
+	Qn // Inverting data outputs
+	);
+	
+	input D, CLK, RST, ENA;		// Deklaration von D und CLK als inputs des d_ff module. Inputs und outputs sind per default wires.
+	output reg Q;	// Deklaration von Q und Qn als outputs des d_ff module. Anstatt des defaults "wire" werden Q und Qn regs.
+	output wire Qn;
+	assign Qn = ~Q;
+	
+	always @ (posedge CLK or posedge RST) begin
+		if (RST) begin
+			Q <= 1'b0;
+		end else if (ENA) begin
+			Q <= D;
+		//Qn <= ~D;
+		end
+	end
+
+endmodule // d_ff

labor_2/counters_leds/src/mod_n_counter_10bit.v

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+// modulo n counter implementation with localparam
+module mod_n_counter_10bit
+  // parameters to pass at instantiation 
+# (parameter N = 10)
+(
+  // module inputs
+  input CLK,
+  input RST,
+  input EN,
+  // module outputs
+  output reg [9:0] Q,
+  output TC
+);
+
+localparam TERMINAL_COUNT = N-1;
+
+always @(posedge CLK or posedge RST) begin
+  if (RST) begin
+    Q <= 10'd0;
+  end else if (EN) begin
+    if (Q == TERMINAL_COUNT) begin
+      Q <= 10'd0;
+    end else begin
+      Q<= Q + 10'd1;
+    end
+  end else begin
+    Q <= Q;
+  end
+end
+
+assign TC = (Q == TERMINAL_COUNT);
+
+endmodule

labor_2/counters_leds/src/mod_n_counter_10bit_template.v

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+// modulo n counter implementation with localparam
+
+module mod_n_counter_10bit
+  // parameters to pass at instantiation 
+(
+  // module inputs
+
+  // module outputs
+
+);
+
+endmodule