Lösung vom Drive kopiert und mit ChatGPT korrigieren lassen.

labor_3/res/ampel/sim __quartus13.1__/work/_info

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labor_3/res/ampel/sim/work/_info

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labor_3/Übungen/ampel/sim/sim.tcl

@@ -1,23 +0,0 @@
-#JZ 2020
-
-#remove working directory
-file delete -force work
-
-#Creating the work lib
-vlib work
-#vmap ampel "designlib/ampel"
-vmap work work
-
-#Top level testbench
-vlog tb_ampel.v
-vlog ../src/ampel.v +define+SIMULATION
-vlog ../src/mod_n_counter_10bit.v
-
-#Simulate
-#vsim -c -t ps -L ampel tb_ampel
-vsim -c -t ps tb_ampel
-
-#get wave
-do wave.do
-
-run 1500 us

labor_3/Übungen/ampel/sim/tb_ampel.v

@@ -1,67 +0,0 @@
-/******************************************************
-*                                                     
-*  Description:  tb_ampel                                
-*         Date:  13.01.2018                           
-*    File Name:  tb_ampel.v                              
-*      Version:  1.0                                  
-*       Target:  Simulation             
-*   Technology:                                       
-*                                                     
-* Rev   Author   Date          Changes                
-* -----------------------------------------------------        
-* 1.0   JZ       13.01.2018    Testbench zur Ampelsteuerung
-*******************************************************/
-
-`timescale 1ns / 1ps
-
-module tb_ampel;
-
-reg CLK;
-reg RSTn;
-reg SW;
-
-wire [2:0] HAUPTSTR_LINKS;
-wire [2:0] NEBENSTR_LINKS;
-wire [1:0] FUSSGAENGER_LINKS;
-wire [2:0] HAUPTSTR_RECHTS;
-wire [2:0] NEBENSTR_RECHTS;
-wire [1:0] FUSSGAENGER_RECHTS;
-
-//50 MHz clock
-initial
-  begin
-  CLK  = 1'b0;
-  end
-
-always
-  CLK = #10 ~CLK;
-
-//push buttons
-initial
-  begin
-  RSTn = 1'b1;
-  SW = 1'b1;
-  #100;
-  RSTn = 1'b0;
-  #10;
-  RSTn = 1'b1;
-  #50_000;
-  SW = 1'b0;
-  #100;
-  SW = 1'b1;
-  end
-
-ampel ampel(
-.CLOCK_50 (CLK),
-.KEY ({RSTn, SW}),
-.LEDH_L(HAUPTSTR_LINKS),
-.LEDN_L(NEBENSTR_LINKS),
-.LEDF_L(FUSSGAENGER_LINKS),
-.LEDH_R(HAUPTSTR_RECHTS),
-.LEDN_R(NEBENSTR_RECHTS),
-.LEDF_R(FUSSGAENGER_RECHTS)
-);
-
-
-
-endmodule

labor_3/Übungen/ampel/sim/wave.do

@@ -1,30 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate /tb_ampel/CLK
-add wave -noupdate /tb_ampel/RSTn
-add wave -noupdate /tb_ampel/SW
-add wave -noupdate -expand -subitemconfig {{/tb_ampel/HAUPTSTR_LINKS[2]} {-color Red} {/tb_ampel/HAUPTSTR_LINKS[1]} {-color Gold}} /tb_ampel/HAUPTSTR_LINKS
-add wave -noupdate -expand -subitemconfig {{/tb_ampel/NEBENSTR_LINKS[2]} {-color Red} {/tb_ampel/NEBENSTR_LINKS[1]} {-color Gold}} /tb_ampel/NEBENSTR_LINKS
-add wave -noupdate -expand -subitemconfig {{/tb_ampel/FUSSGAENGER_LINKS[1]} {-color Red}} /tb_ampel/FUSSGAENGER_LINKS
-add wave -noupdate -expand -subitemconfig {{/tb_ampel/HAUPTSTR_RECHTS[2]} {-color Red} {/tb_ampel/HAUPTSTR_RECHTS[1]} {-color Gold}} /tb_ampel/HAUPTSTR_RECHTS
-add wave -noupdate -expand -subitemconfig {{/tb_ampel/NEBENSTR_RECHTS[2]} {-color Red} {/tb_ampel/NEBENSTR_RECHTS[1]} {-color Gold}} /tb_ampel/NEBENSTR_RECHTS
-add wave -noupdate -expand -subitemconfig {{/tb_ampel/FUSSGAENGER_RECHTS[1]} {-color Red}} /tb_ampel/FUSSGAENGER_RECHTS
-add wave -position end  sim:/tb_ampel/ampel/CLOCK_ENABLE
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {833117378 ps} 0}
-quietly wave cursor active 1
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 0
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 5000
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ns
-update
-WaveRestoreZoom {0 ps} {1575 us}

labor_3/Übungen/ampel/sim/work/_info

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labor_3/Übungen/ampel/sim/work/ampel/_primary.vhd

@@ -1,32 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity ampel is
-    generic(
-        FUSS_AUS        : vl_logic_vector(0 to 1) := (Hi0, Hi0);
-        FUSS_ROT        : vl_logic_vector(0 to 1) := (Hi1, Hi0);
-        FUSS_GRUEN      : vl_logic_vector(0 to 1) := (Hi0, Hi1);
-        AUTO_AUS        : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi0);
-        AUTO_ROT        : vl_logic_vector(0 to 2) := (Hi1, Hi0, Hi0);
-        AUTO_GELB       : vl_logic_vector(0 to 2) := (Hi0, Hi1, Hi0);
-        AUTO_GRUEN      : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi1)
-    );
-    port(
-        CLOCK_50        : in     vl_logic;
-        KEY             : in     vl_logic_vector(1 downto 0);
-        LEDH_L          : out    vl_logic_vector(2 downto 0);
-        LEDH_R          : out    vl_logic_vector(2 downto 0);
-        LEDN_L          : out    vl_logic_vector(2 downto 0);
-        LEDN_R          : out    vl_logic_vector(2 downto 0);
-        LEDF_L          : out    vl_logic_vector(1 downto 0);
-        LEDF_R          : out    vl_logic_vector(1 downto 0);
-        DBG             : out    vl_logic
-    );
-    attribute mti_svvh_generic_type : integer;
-    attribute mti_svvh_generic_type of FUSS_AUS : constant is 1;
-    attribute mti_svvh_generic_type of FUSS_ROT : constant is 1;
-    attribute mti_svvh_generic_type of FUSS_GRUEN : constant is 1;
-    attribute mti_svvh_generic_type of AUTO_AUS : constant is 1;
-    attribute mti_svvh_generic_type of AUTO_ROT : constant is 1;
-    attribute mti_svvh_generic_type of AUTO_GELB : constant is 1;
-    attribute mti_svvh_generic_type of AUTO_GRUEN : constant is 1;
-end ampel;

labor_3/Übungen/ampel/sim/work/mod_n_counter_10bit/_primary.vhd

@@ -1,16 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity mod_n_counter_10bit is
-    generic(
-        N               : integer := 10
-    );
-    port(
-        CLK             : in     vl_logic;
-        RST             : in     vl_logic;
-        EN              : in     vl_logic;
-        Q               : out    vl_logic_vector(9 downto 0);
-        TC              : out    vl_logic
-    );
-    attribute mti_svvh_generic_type : integer;
-    attribute mti_svvh_generic_type of N : constant is 1;
-end mod_n_counter_10bit;

labor_3/Übungen/ampel/src/ampel.v

@@ -1,335 +0,0 @@
-/******************************************************
-*                                                     
-*  Description:  Vorlage Ampelsteurerung                                
-*         Date:  05.01.2018                          
-*    File Name:  ampel_wo_src.v                              
-*      Version:  1.2                                  
-*       Target:  Simulation and Synthesis             
-*   Technology:                                       
-*                                                     
-* Rev   Author   Date          Changes                
-* -----------------------------------------------------
-* 1.0   RHK      10.10.2011    Initial Release        
-* 1.1   JZ       10.03.2016    several bugfixes
-* 1.2   JZ       05.01.2018    angepasst auf neues Ampelboard
-* 1.3   MW       07.03.2019    STATE Konstanten angepasst
-*******************************************************/
-
-`timescale 1ns / 1ps
-
-module ampel (
-  input              CLOCK_50,
-  input        [1:0] KEY,
-  output       [2:0] LEDH_L,
-  output       [2:0] LEDH_R,
-  output       [2:0] LEDN_L,
-  output       [2:0] LEDN_R,
-  output       [1:0] LEDF_L,
-  output       [1:0] LEDF_R, 
-  output reg			DBG  
-);
-
-reg [9:0] CLKDIV1;
-reg [9:0] CLKDIV2;
-reg [9:0] CLKDIV3;
-
-reg MELDER;
-reg MELDER_Q;
-reg MELDER_QQ;
-reg MELDER_ACK;
-reg CLOCK_ENABLE;
-
-reg START_WARTEN;
-reg [3:0] STATE;
-reg [2:0] HAUPTSTR;
-reg [2:0] NEBENSTR;
-reg [1:0] FUSSGAENGER;
-
-reg [3:0] WARTEZAEHLER;
-reg [3:0] WARTEWERT;
-
-wire en_div_1;
-wire en_div_2;
-wire en_div_3;
-
-wire [9:0] q_div_1;
-wire [9:0] q_div_2;
-wire [9:0] q_div_3;
-
-wire tc_div_1;
-wire tc_div_2;
-wire tc_div_3;
-
-//                       R Gr
-parameter FUSS_AUS   = 2'b00;
-parameter FUSS_ROT   = 2'b10;
-parameter FUSS_GRUEN = 2'b01;
-//                      R Ge Gr
-parameter AUTO_AUS   = 3'b000;
-parameter AUTO_ROT   = 3'b100;
-parameter AUTO_GELB  = 3'b010;
-parameter AUTO_GRUEN = 3'b001;
-
-assign RESET                     = ~KEY[1];
-
-assign LEDH_L  = HAUPTSTR;
-assign LEDH_R  = HAUPTSTR;
-assign LEDN_L = NEBENSTR;
-assign LEDN_R = NEBENSTR;
-assign LEDF_L = FUSSGAENGER;
-assign LEDF_R = FUSSGAENGER;
-
-`ifdef SIMULATION
-`define DIVVAL1 10-1
-`define DIVVAL3 5-1
-`else
-`define DIVVAL1 1000-1
-`define DIVVAL3 50-1
-`endif
-
-`define FUSS_WARTEN       4  //Wartezeit
-`define GELB_DAUER        4  //Wartezeit 
-`define FUSS_GRUEN_DAUER  4  //Wartezeit
-`define ALLE_ROT_DAUER    4  //Wartezeit
-
-`define HAUPT_GRUEN_DAUER 4  //Wartezeit
-`define NEBEN_GRUEN_DAUER 4  //Wartezeit
-
-
-`define PHASEVAL 8
-
-//clock divider to generate 1 Hz
-//Clock Enable Generation
-assign en_div_1 = 1'b1;
-assign en_div_2 = tc_div_1;
-assign en_div_3 = tc_div_1 & tc_div_2;
-
-always @(en_div_3) begin
-      CLOCK_ENABLE <= en_div_3;
-end
-
-
-// synchronisze KEY to CLOCK_50
-always @(posedge CLOCK_50) begin
-      MELDER_Q = ~KEY[0];
-      MELDER_QQ = MELDER_Q;
-end
-
-// Melder sofort setzen 
-// Melder zuruecksetzen wenn die Anforderung von der Statemachine verarbeitet
-// wurde. Die Ampelanlage gibt den FUSSGAENGERn nur dann gruen wenn
-// ein Melder anstehst...			
-always @(posedge CLOCK_50 or posedge RESET) begin
-  if (RESET)
-    MELDER <= 1'b0;
-  else begin
-      case ({MELDER_QQ,MELDER_ACK})
-            2'b00: ;
-            2'b01: MELDER <= 1'b0;
-            2'b10: MELDER <= 1'b1;
-            2'b11: MELDER <= ~MELDER;
-      endcase
-  end 	
-end            
-
-//Wartezaehler
-
-assign WARTEN_FERTIG = (WARTEZAEHLER == 1'b0);
-
-always @(posedge CLOCK_50 or posedge RESET) begin
-      if (RESET) begin
-            WARTEZAEHLER <= WARTEWERT;
-      end
-      else if (CLOCK_ENABLE) begin
-            if (~WARTEN_FERTIG) begin
-                  WARTEZAEHLER <= WARTEZAEHLER - 1'b1;
-            end
-            else if (START_WARTEN) begin
-                  START_WARTEN <= ~START_WARTEN;
-                  WARTEZAEHLER <= WARTEWERT;
-            end
-      end
-end
-
-
-always @(posedge CLOCK_50 or posedge RESET)
-  if (RESET)
-    begin
-    HAUPTSTR     <= AUTO_GRUEN;
-    NEBENSTR     <= AUTO_ROT;
-    FUSSGAENGER  <= FUSS_ROT;
-    START_WARTEN <= 1'b0;
-    STATE        <= 4'd0;
-    MELDER_ACK   <= 1'b0;
-    end
-  else
-  if (CLOCK_ENABLE)
-  case (STATE)
-    4'd0: begin
-            if (~WARTEN_FERTIG) begin
-                  START_WARTEN <= 1'b0;
-                  STATE <= 4'd0;
-            end
-            else begin
-                  HAUPTSTR <= AUTO_GRUEN;
-                  NEBENSTR <= AUTO_ROT;
-                  FUSSGAENGER <= FUSS_ROT;
-                  START_WARTEN <= 1'b1;
-                  WARTEWERT <= `HAUPT_GRUEN_DAUER;
-                  STATE <= 4'd1;
-            end
-          end        
-
-    4'd1: begin
-            if(~WARTEN_FERTIG) begin
-                  START_WARTEN <= 1'b0;
-                  STATE <= 4'd1;
-            end
-            else begin
-                  HAUPTSTR <= AUTO_GELB;
-                  NEBENSTR <= AUTO_ROT;
-                  FUSSGAENGER <= FUSS_ROT;
-                  START_WARTEN <= 1'b1;
-                  WARTEWERT <= `GELB_DAUER;
-                  STATE <= 4'd2;
-            end
-
-          end
-    4'd2: begin
-            if (~WARTEN_FERTIG) begin
-                  START_WARTEN <= 1'b0;
-                  STATE <= 4'd2;
-            end
-            else if (WARTEN_FERTIG && MELDER) begin
-                  HAUPTSTR <= AUTO_ROT;
-                  NEBENSTR <= AUTO_ROT;
-                  FUSSGAENGER <= FUSS_ROT;
-                  START_WARTEN <= 1'b1;
-                  WARTEWERT <= `FUSS_WARTEN;
-                  MELDER_ACK <= 1'b1;
-                  STATE <= 4'd3;
-            end
-            else if (WARTEN_FERTIG && ~MELDER) begin
-                  HAUPTSTR <= AUTO_ROT;
-                  NEBENSTR <= AUTO_ROT;
-                  FUSSGAENGER <= FUSS_ROT;
-                  START_WARTEN <= 1'b1;
-                  WARTEWERT <= `ALLE_ROT_DAUER;
-                  STATE <= 4'd4;
-            end
-
-          end
-    4'd3: begin
-            if (~WARTEN_FERTIG) begin
-                  START_WARTEN <= 1'b0;
-                  STATE <= 4'd3;
-            end
-            else begin
-                  HAUPTSTR <= AUTO_ROT;
-                  NEBENSTR <= AUTO_ROT;
-                  FUSSGAENGER <= FUSS_GRUEN;
-                  START_WARTEN <= 1'b1;
-                  WARTEWERT <= `FUSS_GRUEN_DAUER;
-                  MELDER_ACK <= 1'b0;
-                  STATE <= 4'd2;
-            end
-          end 
-    4'd4: begin
-            if (~WARTEN_FERTIG) begin
-                  START_WARTEN <= 1'b0;
-                  STATE <= 4'd4;
-            end
-            else begin
-                  HAUPTSTR <= AUTO_ROT;
-                  NEBENSTR <= AUTO_GELB | AUTO_ROT;
-                  FUSSGAENGER <= FUSS_ROT;
-                  START_WARTEN <= 1'b1;
-                  WARTEWERT <= `GELB_DAUER;
-                  STATE <= 4'd5;
-            end
-          end
-    4'd5: begin
-            if (~WARTEN_FERTIG) begin
-                  START_WARTEN <= 1'b0;
-                  STATE <= 4'd5;
-            end
-            else begin
-                  HAUPTSTR <= AUTO_ROT;
-                  NEBENSTR <= AUTO_GRUEN;
-                  FUSSGAENGER <= FUSS_ROT;
-                  START_WARTEN <= 1'b1;
-                  WARTEWERT <= `NEBEN_GRUEN_DAUER;
-                  STATE <= 4'd6;
-            end
-          end
-    4'd6: begin
-            if (~WARTEN_FERTIG) begin
-                  START_WARTEN <= 1'b0;
-                  STATE <= 4'd6;
-            end
-            else begin
-                  HAUPTSTR <= AUTO_ROT;
-                  NEBENSTR <= AUTO_GELB;
-                  FUSSGAENGER <= FUSS_ROT;
-                  START_WARTEN <= 1'b1;
-                  WARTEWERT <= `GELB_DAUER;
-                  STATE <= 4'd7;
-            end
-          end     
-    4'd7: begin
-            if (~WARTEN_FERTIG) begin
-                  START_WARTEN <= 1'b0;
-                  STATE <= 4'd7;
-            end
-            else begin
-                  HAUPTSTR <= AUTO_ROT;
-                  NEBENSTR <= AUTO_ROT;
-                  FUSSGAENGER <= FUSS_ROT;
-                  START_WARTEN <= 1'b1;
-                  WARTEWERT <= `ALLE_ROT_DAUER;
-                  STATE <= 4'd8;
-            end
-          end         
-    4'd8: begin
-            if (~WARTEN_FERTIG) begin
-                  START_WARTEN <= 1'b0;
-                  STATE <= 4'd8;
-            end
-            else begin
-                  HAUPTSTR <= AUTO_GELB | AUTO_ROT;
-                  NEBENSTR <= AUTO_ROT;
-                  FUSSGAENGER <= FUSS_ROT;
-                  START_WARTEN <= 1'b1;
-                  WARTEWERT <= `GELB_DAUER;
-                  STATE <= 4'd0;
-            end
-          end     
-    default:                      
-          STATE <= 4'd1;
-  endcase
-
-mod_n_counter_10bit #(.N(`DIVVAL1)) divider_1(
-      .CLK(CLOCK_50),
-      .RST(RESET),
-      .EN(en_div_1),
-      .Q(q_div_1),
-      .TC(tc_div_1)
-);
-
-mod_n_counter_10bit #(.N(`DIVVAL1)) divider_2(
-      .CLK(CLOCK_50),
-      .RST(RESET),
-      .EN(en_div_2),
-      .Q(q_div_2),
-      .TC(tc_div_2)
-);
-
-mod_n_counter_10bit #(.N(`DIVVAL3)) divider_3(
-      .CLK(CLOCK_50),
-      .RST(RESET),
-      .EN(en_div_3),
-      .Q(q_div_3),
-      .TC(tc_div_3)
-);
-                        
-endmodule

labor_3/Übungen/ampel/src/mod_n_counter_10bit.v

@@ -1,31 +0,0 @@
-module mod_n_counter_10bit
-# (parameter N = 10)
-(
-  // module inputs
-  input CLK,
-  input RST,
-  input EN,
-  // module outputs
-  output reg [9:0] Q,
-  output TC
-);
-
-localparam TERMINAL_COUNT = N-1;
-
-always @ (posedge CLK or posedge RST) begin
-  if (RST) begin
-    Q <= 10'd0;
-  end else if (EN) begin
-    if (Q == TERMINAL_COUNT) begin
-      Q <= 10'd0;
-    end else begin
-      Q <= Q + 10'd1;
-    end
-  end else begin
-    Q <= Q;
-  end
-end
-
-assign TC = (Q == TERMINAL_COUNT);
-
-endmodule

labor_4/Aufgabe_6-3/quartus/db/prev_cmp_sclk_gen.qmsg

@@ -0,0 +1,9 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1709148267302 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1709148267302 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 28 20:24:27 2024 " "Processing started: Wed Feb 28 20:24:27 2024" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1709148267302 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1709148267302 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sclk_gen -c sclk_gen " "Command: quartus_map --read_settings_files=on --write_settings_files=off sclk_gen -c sclk_gen" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1709148267302 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1709148267633 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/erdem/desktop/labor_eds/labor_4/aufgabe_6-3/src/sclk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/erdem/desktop/labor_eds/labor_4/aufgabe_6-3/src/sclk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 SCLK_gen " "Found entity 1: SCLK_gen" {  } { { "../src/sclk_gen.v" "" { Text "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/src/sclk_gen.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1709148267664 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1709148267664 ""}
+{ "Warning" "WSGN_FILE_IS_MISSING" "../src/d_ff.v " "Can't analyze file -- file ../src/d_ff.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1709148267680 ""}
+{ "Error" "ESGN_TOP_ENTITY_IS_MISSING" "sclk_gen " "Top-level design entity \"sclk_gen\" is undefined" {  } {  } 0 12007 "Top-level design entity \"%1!s!\" is undefined" 0 0 "Quartus II" 0 -1 1709148267711 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  2 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was unsuccessful. 1 error, 2 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "373 " "Peak virtual memory: 373 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1709148267758 ""} { "Error" "EQEXE_END_BANNER_TIME" "Wed Feb 28 20:24:27 2024 " "Processing ended: Wed Feb 28 20:24:27 2024" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1709148267758 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1709148267758 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1709148267758 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1709148267758 ""}
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 2 s " "Quartus II Full Compilation was unsuccessful. 3 errors, 2 warnings" {  } {  } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1709148268356 ""}

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.asm.qmsg

@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1709148352099 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1709148352099 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 28 20:25:51 2024 " "Processing started: Wed Feb 28 20:25:51 2024" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1709148352099 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1709148352099 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off sclk_gen -c sclk_gen " "Command: quartus_asm --read_settings_files=off --write_settings_files=off sclk_gen -c sclk_gen" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1709148352099 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1709148352831 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1709148352862 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "379 " "Peak virtual memory: 379 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1709148353177 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 28 20:25:53 2024 " "Processing ended: Wed Feb 28 20:25:53 2024" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1709148353177 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1709148353177 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1709148353177 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1709148353177 ""}

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.cbx.xml

@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="sclk_gen">
+	</PROJECT>
+</LOG_ROOT>

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.cmp.logdb

@@ -0,0 +1,49 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,0;0;0;0;0;7;0;0;7;7;0;1;0;0;6;0;1;6;0;0;0;1;0;0;0;0;0;7;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,7;7;7;7;7;0;7;7;0;0;7;6;7;7;1;7;6;1;7;7;7;6;7;7;7;7;7;0;7;7,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,SCLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CPHA,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CPOL,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,RESETn,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SYNC,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ENA,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.db_info

@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Version_Index = 302049280
+Creation_Time = Wed Feb 28 19:17:51 2024

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.hier_info

@@ -0,0 +1,14 @@
+|sclk_gen
+ENA => T1.IN1
+SYNC => Q1.ENA
+SYNC => T1.ENA
+RESETn => Q1.ACLR
+RESETn => T1.ACLR
+CPHA => SCLK_1.IN1
+CPHA => SCLK_0.IN1
+CLK => Q1.CLK
+CLK => T1.CLK
+CPOL => SCLK_3.IN1
+SCLK <= SCLK_3.DB_MAX_OUTPUT_PORT_TYPE
+
+

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.lpc.html

@@ -0,0 +1,18 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+</TABLE>

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.lpc.txt

@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.map.logdb

@@ -0,0 +1 @@
+v1

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.map.qmsg

@@ -0,0 +1,11 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1709148343874 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1709148343874 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 28 20:25:43 2024 " "Processing started: Wed Feb 28 20:25:43 2024" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1709148343874 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1709148343874 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sclk_gen -c sclk_gen " "Command: quartus_map --read_settings_files=on --write_settings_files=off sclk_gen -c sclk_gen" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1709148343874 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1709148344189 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/erdem/desktop/labor_eds/labor_4/aufgabe_6-3/src/sclk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/erdem/desktop/labor_eds/labor_4/aufgabe_6-3/src/sclk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 sclk_gen " "Found entity 1: sclk_gen" {  } { { "../src/sclk_gen.v" "" { Text "C:/Users/Erdem/Desktop/labor_eds/labor_4/Aufgabe_6-3/src/sclk_gen.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1709148344236 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1709148344236 ""}
+{ "Warning" "WSGN_FILE_IS_MISSING" "../src/d_ff.v " "Can't analyze file -- file ../src/d_ff.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1709148344236 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "sclk_gen " "Elaborating entity \"sclk_gen\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1709148344267 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1709148344755 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1709148344961 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1709148344961 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "10 " "Implemented 10 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1709148344977 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1709148344977 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3 " "Implemented 3 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1709148344977 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1709148344977 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "390 " "Peak virtual memory: 390 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1709148344993 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 28 20:25:44 2024 " "Processing ended: Wed Feb 28 20:25:44 2024" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1709148344993 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1709148344993 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1709148344993 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1709148344993 ""}

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.map_bb.logdb

@@ -0,0 +1 @@
+v1

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.rpp.qmsg

@@ -0,0 +1,4 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1709148362091 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 32-bit " "Running Quartus II 32-bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1709148362091 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 28 20:26:01 2024 " "Processing started: Wed Feb 28 20:26:01 2024" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1709148362091 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1709148362091 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp sclk_gen -c sclk_gen --netlist_type=sgate " "Command: quartus_rpp sclk_gen -c sclk_gen --netlist_type=sgate" {  } {  } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1709148362091 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "245 " "Peak virtual memory: 245 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1709148362123 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 28 20:26:02 2024 " "Processing ended: Wed Feb 28 20:26:02 2024" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1709148362123 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1709148362123 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1709148362123 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1709148362123 ""}

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.smart_action.txt

@@ -0,0 +1 @@
+DONE

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.sta.qmsg

@@ -0,0 +1,41 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1709148354172 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354172 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 28 20:25:53 2024 " "Processing started: Wed Feb 28 20:25:53 2024" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1709148354172 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1709148354172 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta sclk_gen -c sclk_gen " "Command: quartus_sta sclk_gen -c sclk_gen" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1709148354172 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1709148354251 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1709148354392 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1709148354424 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1709148354424 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "sclk_gen.sdc " "Synopsys Design Constraints File file not found: 'sclk_gen.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1709148354675 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1709148354675 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK CLK " "create_clock -period 1.000 -name CLK CLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354690 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354690 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1709148354769 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354769 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1709148354769 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1709148354785 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.092 " "Worst-case setup slack is 0.092" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.092         0.000 CLK  " "    0.092         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.359 " "Worst-case hold slack is 0.359" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.359         0.000 CLK  " "    0.359         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148354785 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148354785 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148354785 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1709148354800 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1709148354800 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354800 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354800 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -5.000 CLK  " "   -3.000        -5.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148354800 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148354800 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1709148354816 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1709148354832 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1709148355036 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.186 " "Worst-case setup slack is 0.186" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.186         0.000 CLK  " "    0.186         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.318 " "Worst-case hold slack is 0.318" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.318         0.000 CLK  " "    0.318         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148355067 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148355067 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1709148355067 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1709148355067 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -5.000 CLK  " "   -3.000        -5.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355067 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1709148355099 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.506 " "Worst-case setup slack is 0.506" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.506         0.000 CLK  " "    0.506         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.193         0.000 CLK  " "    0.193         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355272 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148355287 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1709148355287 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1709148355287 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1709148355287 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -5.052 CLK  " "   -3.000        -5.052 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1709148355287 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1709148355287 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1709148355776 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1709148355776 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "376 " "Peak virtual memory: 376 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1709148355823 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 28 20:25:55 2024 " "Processing ended: Wed Feb 28 20:25:55 2024" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1709148355823 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1709148355823 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1709148355823 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1709148355823 ""}

labor_4/Aufgabe_6-3/quartus/db/sclk_gen.tmw_info

@@ -0,0 +1,6 @@
+start_full_compilation:s:00:00:13
+start_analysis_synthesis:s:00:00:02-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:06-start_full_compilation
+start_assembler:s:00:00:02-start_full_compilation
+start_timing_analyzer:s:00:00:03-start_full_compilation

labor_4/Aufgabe_6-3/quartus/incremental_db/README

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+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+

labor_4/Aufgabe_6-3/quartus/incremental_db/compiled_partitions/sclk_gen.db_info

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+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Version_Index = 302049280
+Creation_Time = Wed Feb 28 19:18:03 2024