97 lines
1.7 KiB
Verilog
97 lines
1.7 KiB
Verilog
//cola testbench
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`timescale 1ns/1ps
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module tb_cola();
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reg tb_clk;
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reg tb_rst;
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reg tb_enable;
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reg dut_eineuro;
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reg dut_zweieuro;
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wire [1:0] dut_ausgabe;
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wire [1:0] dut_zustand;
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integer i = 0;
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initial begin
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tb_clk = 1'b0;
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tb_rst = 1'b0;
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tb_enable = 1'b0;
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end
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always begin
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#10;
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tb_clk = ~tb_clk;
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end
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initial begin
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for (i=0; i<4; i=i+1) begin
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@(negedge tb_clk);
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end
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dut_eineuro = 1'b0;
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dut_zweieuro = 1'b0;
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tb_rst = 1'b1;
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@(negedge tb_clk)
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tb_rst = 1'b0;
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@(negedge tb_clk)
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tb_enable = 1'b1;
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for (i=0; i<8; i=i+1) begin
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@(negedge tb_clk);
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end
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//Fall 1: 3 mal 1 Euro
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for (i=0; i<3; i=i+1) begin
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dut_eineuro = 1'b1;
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@(negedge tb_clk);
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dut_eineuro = 1'b0;
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@(negedge tb_clk);
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end
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for (i=0; i<=4; i=i+1) begin
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@(negedge tb_clk);
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end
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tb_rst = 1'b1;
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@(negedge tb_clk)
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tb_rst = 1'b0;
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@(negedge tb_clk)
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for (i=0; i<4; i=i+1) begin
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@(negedge tb_clk);
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end
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//Fall 2: 2 Euro + 1 Euro
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dut_zweieuro = 1'b1;
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@(negedge tb_clk);
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dut_zweieuro = 1'b0;
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@(negedge tb_clk);
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dut_eineuro = 1'b1;
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@(negedge tb_clk);
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dut_eineuro = 1'b0;
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@(negedge tb_clk);
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for (i=0; i<4; i=i+1) begin
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@(negedge tb_clk);
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end
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end
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cola cola_dut(
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.CLK(tb_clk),
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.RST(tb_rst),
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.ENABLE(tb_enable),
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.EINEURO(dut_eineuro),
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.ZWEIEURO(dut_zweieuro),
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.AUSGABE(dut_ausgabe),
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.ZUSTAND(dut_zustand)
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);
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endmodule |