Ressourcen für Labor 4 kopiert

labor_4/res/spi_master/sim/libs/spi_master/_info

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+m255
+K3
+13
+cModel Technology
+dC:\digitale_systeme\spi_master\sim
+vspi_master
+!s100 PDm=HJzS7gNQJSYmeO1UX1
+IN33U<eK;gRE;z6ImB8iaH3
+VVAEF_7[2`JEP650]dTjC60
+d.
+Fnofile
+L0 4
+OV;L;10.1b;51
+r1
+!s85 0
+31
+!s108 1521123190.954000
+!s107 ../src/spi_master.v|
+!s90 -reportprogress|300|-quiet|-nodebug|-work|spi_master|../src/spi_master.v|
+!s101 -O0
+o-quiet -nodebug -nodebug -work spi_master -O0

labor_4/res/spi_master/sim/libs/spi_master/_vmake

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+m255
+K3
+cModel Technology

labor_4/res/spi_master/sim/libs/spi_master/spi_master/_primary.vhd

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+library verilog;
+use verilog.vl_types.all;
+entity spi_master is
+    port(
+        RESETn          : in     vl_logic;
+        CLK             : in     vl_logic;
+        CLK_DIVIDER     : in     vl_logic_vector(7 downto 0);
+        SLAVE_SELECT    : in     vl_logic_vector(7 downto 0);
+        DATA_LENGTH     : in     vl_logic_vector(1 downto 0);
+        MODE            : in     vl_logic_vector(1 downto 0);
+        MISO            : in     vl_logic;
+        TX              : in     vl_logic_vector(31 downto 0);
+        RUN             : in     vl_logic;
+        RX              : out    vl_logic_vector(31 downto 0);
+        SCLK            : out    vl_logic;
+        MOSI            : out    vl_logic;
+        SSn             : out    vl_logic_vector(7 downto 0);
+        BUSY            : out    vl_logic;
+        SYNC_TEST       : out    vl_logic;
+        STATE_TEST      : out    vl_logic_vector(2 downto 0);
+        ENA_TEST        : out    vl_logic
+    );
+end spi_master;

labor_4/res/spi_master/sim/sim.do

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+#remove working directory
+file delete -force work
+
+#Creating the work lib
+vlib work
+vmap work work
+
+
+#Top level testbench
+vlog spi_master_tb.v \
+     ../src/spi_master.v
+
+#Simulate
+vsim -c -t ps spi_master_tb 
+
+#get wave
+do wave.do
+
+run 25 us

labor_4/res/spi_master/sim/sim_w_lib.do

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+#remove working directory
+file delete -force work
+
+#Creating the work lib
+vlib work
+vmap work work
+vlib "libs/spi_master"
+vmap spi_master "libs/spi_master"
+
+#Top level testbench
+vlog spi_master_tb.v 
+
+#Simulate
+vsim -c -t ps -L spi_master spi_master_tb 
+
+#get wave
+do wave.do
+
+run 25 us

labor_4/res/spi_master/sim/spi_master_tb.v

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+`timescale 1ns/1ps
+
+module spi_master_tb;
+// top level testbench, no inputs or outputs
+
+  reg RESETn_TB, RUN_TB, CLOCK_50_TB;
+  reg [7:0] CLK_DIVIDER_TB, SLAVE_SELECT_TB;
+  reg [1:0] DATA_LENGTH_TB, MODE_TB;
+  reg [31:0] TX_TB;
+
+//DUT module outputs
+  wire [31:0] RX_TB;
+  wire [7:0]  SSn_TB;
+  wire SCLK_TB, MOSI_TB, BUSY_TB, MISO_TB;
+  
+//DUT test signals
+  wire [2:0] STATE_TEST_TB;
+  wire SYNC_TEST_TB, ENA_TEST_TB;
+  
+  assign MISO_TB = 1'b0;
+  
+  initial begin
+    // Reset
+    CLOCK_50_TB <= 1'b0;
+    RESETn_TB <= 1'b1;
+    
+    TX_TB <= 32'h0;
+    CLK_DIVIDER_TB <= 8'h0;
+    SLAVE_SELECT_TB <= 8'h0;
+    DATA_LENGTH_TB <= 2'b00;
+    MODE_TB <= 2'b00;
+    RUN_TB <= 1'b0;
+    
+    #20 RESETn_TB <= 1'b0;
+    #80 RESETn_TB <= 1'b1;
+    
+    // spi_master setup: 8 Bit Daten, Mode 0
+        
+    TX_TB <= 32'h000000AA;
+    CLK_DIVIDER_TB <= 8'h1;
+    SLAVE_SELECT_TB <= 8'h1;
+    DATA_LENGTH_TB <= 2'b00;
+    MODE_TB <= 2'b00;
+    
+    #100 RUN_TB <= 1'b1;
+    #100 RUN_TB <= 1'b0;
+
+    #5000
+
+    // spi_master setup: 16 Bit Daten, Mode 3    
+    TX_TB <= 32'h000084A8;
+    CLK_DIVIDER_TB <= 8'h4;
+    SLAVE_SELECT_TB <= 8'h1;
+    DATA_LENGTH_TB <= 2'b01;
+    MODE_TB <= 2'b11;
+    
+    #100 RUN_TB <= 1'b1;
+    #100 RUN_TB <= 1'b0;
+    
+    #7000
+    
+    // spi_master setup: 8 Bit Daten, Mode 2    
+    TX_TB <= 32'h000084A8;
+    CLK_DIVIDER_TB <= 8'h4;
+    SLAVE_SELECT_TB <= 8'h2;
+    DATA_LENGTH_TB <= 2'b00;
+    MODE_TB <= 2'b10;
+    
+    #100 RUN_TB <= 1'b1;
+    #100 RUN_TB <= 1'b0;
+    
+  end
+  
+  always begin
+    #10 CLOCK_50_TB <= ~CLOCK_50_TB;
+  end
+  
+  spi_master spi_master_test(
+  .RESETn(RESETn_TB),
+  .CLK(CLOCK_50_TB),
+  .RUN(RUN_TB),
+  .MODE(MODE_TB),
+  .DATA_LENGTH(DATA_LENGTH_TB),
+  .CLK_DIVIDER(CLK_DIVIDER_TB),
+  .SLAVE_SELECT(SLAVE_SELECT_TB),
+  .TX(TX_TB),
+  .SCLK(SCLK_TB),
+  .MISO(MISO_TB),
+  .MOSI(MOSI_TB),
+  .SSn(SSn_TB),
+  .RX(RX_TB),
+  .BUSY(BUSY_TB),
+  .SYNC_TEST(SYNC_TEST_TB),
+  .STATE_TEST(STATE_TEST_TB),
+  .ENA_TEST(ENA_TEST_TB));  
+endmodule

labor_4/res/spi_master/sim/wave.do

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+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /spi_master_tb/RESETn_TB
+add wave -noupdate /spi_master_tb/RUN_TB
+add wave -noupdate /spi_master_tb/CLOCK_50_TB
+add wave -noupdate -radix unsigned /spi_master_tb/CLK_DIVIDER_TB
+add wave -noupdate /spi_master_tb/SLAVE_SELECT_TB
+add wave -noupdate /spi_master_tb/DATA_LENGTH_TB
+add wave -noupdate -radix unsigned /spi_master_tb/MODE_TB
+add wave -noupdate -radix hexadecimal /spi_master_tb/TX_TB
+add wave -noupdate -radix hexadecimal /spi_master_tb/RX_TB
+add wave -noupdate -divider {SPI Interface}
+add wave -noupdate /spi_master_tb/SSn_TB
+add wave -noupdate /spi_master_tb/SCLK_TB
+add wave -noupdate /spi_master_tb/MOSI_TB
+add wave -noupdate /spi_master_tb/BUSY_TB
+add wave -noupdate /spi_master_tb/MISO_TB
+add wave -noupdate -divider {SPI Master intern}
+add wave -noupdate /spi_master_tb/SYNC_TEST_TB
+add wave -noupdate -radix unsigned -childformat {{{/spi_master_tb/STATE_TEST_TB[2]} -radix unsigned} {{/spi_master_tb/STATE_TEST_TB[1]} -radix unsigned} {{/spi_master_tb/STATE_TEST_TB[0]} -radix unsigned}} -subitemconfig {{/spi_master_tb/STATE_TEST_TB[2]} {-radix unsigned} {/spi_master_tb/STATE_TEST_TB[1]} {-radix unsigned} {/spi_master_tb/STATE_TEST_TB[0]} {-radix unsigned}} /spi_master_tb/STATE_TEST_TB
+add wave -noupdate /spi_master_tb/ENA_TEST_TB
+add wave -noupdate /spi_master_tb/spi_master_test/BUSY
+add wave -noupdate -radix hexadecimal /spi_master_tb/spi_master_test/TX_SR
+add wave -noupdate -radix hexadecimal /spi_master_tb/spi_master_test/RX_SR
+add wave -noupdate -radix unsigned /spi_master_tb/spi_master_test/CYCLE_CTR
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+quietly wave cursor active 0
+configure wave -namecolwidth 232
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {1640626 ps}