Ressourcen für Labor 4 kopiert

labor_4/res/spi_master/src/led_chaser.v

@@ -0,0 +1,93 @@
+module led_chaser(
+// module inputs
+CLOCK_50,
+KEY,
+SW,
+// module outputs
+SSn_D,
+MOSI_D,
+SCLK_D,
+LEDR
+);
+
+input [3:0] KEY;
+input CLOCK_50;
+input [15:0] SW;
+output [3:0] SSn_D;
+output MOSI_D, SCLK_D;
+output [15:0] LEDR;
+
+assign LEDR = LEDS;
+
+// Reset wire
+wire RESETn;
+assign RESETn = KEY[0];
+
+wire [15:0] LEDS;
+reg [9:0] CLKDIV0, CLKDIV1, CLKDIV2;
+
+`define DIVVAL0 1000-1
+`define DIVVAL1 1000-1
+`define DIVVAL2 50-1
+
+// Clock Divider
+always @(posedge CLOCK_50 or negedge RESETn)
+	if (~RESETn) CLKDIV0 <=`DIVVAL0;
+	else if (CLKDIV0 > 10'b0)
+      CLKDIV0[9:0] <= CLKDIV0[9:0] - 1'b1;
+    else
+      CLKDIV0[9:0] <= `DIVVAL0;
+
+always @(posedge CLOCK_50 or negedge RESETn)
+	if (~RESETn) CLKDIV1 <=`DIVVAL1;
+	else if (CLKDIV0[9:0] == 10'b0)
+      begin
+      if (CLKDIV1 > 10'b0)
+        CLKDIV1[9:0] <= CLKDIV1[9:0] - 1'b1;
+      else
+        CLKDIV1[9:0] <= `DIVVAL1;
+      end
+		
+always @(posedge CLOCK_50 or negedge RESETn)
+	if (~RESETn) CLKDIV2<=`DIVVAL2;
+	else if ((CLKDIV1[9:0] == 10'b0) & (CLKDIV0[9:0] == 10'b0))
+      begin
+      if (CLKDIV2 > 10'b0)
+        CLKDIV2[9:0] <= CLKDIV2[9:0] - 1'b1;
+      else
+        CLKDIV2[9:0] <= `DIVVAL2;
+      end
+
+// ring_sr
+
+ring_sr ring_shift_reg(
+	.CLK(CLOCK_50),
+	.RSTn(RESETn),
+	.ENA((CLKDIV0[9:0] == 10'b0) & (CLKDIV1[9:0] == 10'b0) & (CLKDIV2[9:0] == 10'b0)),
+	.PATTERN(SW),
+	.Q(LEDS[15:0]));
+	
+// SPI-Master
+spi_master spimaster(
+  .RESETn(RESETn),
+  .CLK(CLOCK_50),
+  .CLK_DIVIDER(8'd10),
+  .SLAVE_SELECT(8'h1),
+  .DATA_LENGTH(2'd1),
+  .MODE(2'd1),
+  .MISO(1'b1),
+  .TX({16'h0,LEDS}),
+  .RUN((CLKDIV0[9:0] == 10'b0) & (CLKDIV1[9:0] == 10'b0) & (CLKDIV2[9:0] == 10'b0)),
+  //module outputs
+  .RX(),
+  .SCLK(SCLK_D),
+  .MOSI(MOSI_D),
+  .SSn(SSn_D),
+  .BUSY(),
+  // module test outputs
+  .SYNC_TEST(),
+  .STATE_TEST(),
+  .ENA_TEST()  
+);
+	
+endmodule

labor_4/res/spi_master/src/ring_sr.v

@@ -0,0 +1,23 @@
+module ring_sr(
+  //inputs
+  PATTERN,
+  CLK,
+  RSTn,
+  ENA,
+  //outputs
+  Q);
+  
+  input [15:0] PATTERN;
+  input CLK,RSTn,ENA;
+  output reg [15:0] Q;
+  
+  always @(posedge CLK)
+    if(~RSTn) Q <= PATTERN;
+    
+    else if (ENA) 
+      begin
+        Q[15:1] <= Q[14:0];
+        Q[0] <= Q[15];
+      end
+      
+endmodule // ring_sr 

labor_4/res/spi_master/src/spi_master_template.v

@@ -0,0 +1,86 @@
+// module spi_master
+// Author: M. Walz
+
+module spi_master(
+  //module inputs
+  // --- Definition of control inputs ---
+  input wire        RESETn,
+  input wire        CLK,
+  input wire [7:0]  CLK_DIVIDER,
+  input wire [7:0]  SLAVE_SELECT,
+  input wire [1:0]  DATA_LENGTH,
+  input wire [1:0]  MODE,
+  input wire        MISO,
+  input wire [31:0] TX,
+  input wire RUN,
+  //module outputs
+  output reg [31:0] RX,
+  output            SCLK,
+  output reg        MOSI,
+  output reg [7:0]  SSn,
+  output reg        BUSY,
+  // module test outputs
+  output wire       SYNC_TEST,
+  output wire [2:0] STATE_TEST,
+  output wire       ENA_TEST  
+  );
+
+
+  
+  
+// --- Definition of internal varibles ---
+  reg [31:0]TX_SR, RX_SR;
+  reg [7:0] CLK_DIVIDER_REG;
+  reg [5:0] CYCLE_CTR;
+  reg [2:0] STATE;
+  reg ENA;                // Enables operation of SCLK generator
+  reg T1, Q1;             // Used for SLCK generation
+  wire CPOL, CPHA;        // SPI Mode
+  wire SYNC;              // SYNC Signal
+  
+// --- Implementation ---
+
+// assignments of test signals
+  assign STATE_TEST = STATE;
+  assign ENA_TEST = ENA;
+  assign SYNC_TEST = SYNC;
+
+// assignments MODE to control wires  
+  assign CPOL = MODE [1];
+  assign CPHA = MODE [0];
+  
+// Clockdivider for generation of SYNC signal
+
+always @ (posedge CLK or negedge RESETn) begin
+end
+
+// SPI-interface control logic
+
+always @ (posedge CLK or negedge RESETn) begin
+  if (~RESETn) begin
+  end 
+  else case (STATE)
+    // STATE: Wait
+    
+    // STATE: Initialize
+
+    // STATE: Shift
+
+    // STATE: Latch
+
+    // STATE:  
+
+	// When transfering data from RX to RX_SR, ignore previously received bytes
+				case (DATA_LENGTH[1:0])
+					2'h0 : RX[31:0] <= {24'h0, RX_SR[ 7:0]};	// 1 Byte received
+					2'h1 :  // 2 Bytes received	
+					2'h2 : // 3 Bytes received
+					2'h3 :   // 4 Bytes received
+				endcase
+
+  endcase
+end
+
+//  SPI SCLK generation
+
+endmodule