Hochladen der vorherigen Laborübungen.
Die Dateien selbst wurden nicht verändert.
This commit is contained in:
@@ -0,0 +1,17 @@
|
||||
i = 0, i-1 = -1; $clog2(i) = 0
|
||||
i = 1, i-1 = 0; $clog2(i) = 1
|
||||
i = 2, i-1 = 1; $clog2(i) = 2
|
||||
i = 3, i-1 = 2; $clog2(i) = 2
|
||||
i = 4, i-1 = 4; $clog2(i) = 3
|
||||
i = 5, i-1 = 5; $clog2(i) = 3
|
||||
i = 6, i-1 = 6; $clog2(i) = 3
|
||||
i = 7, i-1 = 7; $clog2(i) = 3
|
||||
i = 8, i-1 = 8; $clog2(i) = 4
|
||||
i = 9, i-1 = 9; $clog2(i) = 4
|
||||
i = 10, i-1 = 10; $clog2(i) = 4
|
||||
i = 11, i-1 = 11; $clog2(i) = 4
|
||||
i = 12, i-1 = 12; $clog2(i) = 4
|
||||
i = 13, i-1 = 13; $clog2(i) = 4
|
||||
i = 14, i-1 = 14; $clog2(i) = 4
|
||||
i = 15, i-1 = 15; $clog2(i) = 4
|
||||
i = 16, i-1 = 16; $clog2(i) = 4
|
||||
@@ -0,0 +1,324 @@
|
||||
; Copyright 1991-2009 Mentor Graphics Corporation
|
||||
;
|
||||
; All Rights Reserved.
|
||||
;
|
||||
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
|
||||
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
;
|
||||
|
||||
[Library]
|
||||
others = $MODEL_TECH/../modelsim.ini
|
||||
|
||||
; Altera Primitive libraries
|
||||
;
|
||||
; VHDL Section
|
||||
;
|
||||
;
|
||||
; Verilog Section
|
||||
;
|
||||
|
||||
work = work
|
||||
[vcom]
|
||||
; VHDL93 variable selects language version as the default.
|
||||
; Default is VHDL-2002.
|
||||
; Value of 0 or 1987 for VHDL-1987.
|
||||
; Value of 1 or 1993 for VHDL-1993.
|
||||
; Default or value of 2 or 2002 for VHDL-2002.
|
||||
; Default or value of 3 or 2008 for VHDL-2008.
|
||||
VHDL93 = 2002
|
||||
|
||||
; Show source line containing error. Default is off.
|
||||
; Show_source = 1
|
||||
|
||||
; Turn off unbound-component warnings. Default is on.
|
||||
; Show_Warning1 = 0
|
||||
|
||||
; Turn off process-without-a-wait-statement warnings. Default is on.
|
||||
; Show_Warning2 = 0
|
||||
|
||||
; Turn off null-range warnings. Default is on.
|
||||
; Show_Warning3 = 0
|
||||
|
||||
; Turn off no-space-in-time-literal warnings. Default is on.
|
||||
; Show_Warning4 = 0
|
||||
|
||||
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
||||
; Show_Warning5 = 0
|
||||
|
||||
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
||||
; Optimize_1164 = 0
|
||||
|
||||
; Turn on resolving of ambiguous function overloading in favor of the
|
||||
; "explicit" function declaration (not the one automatically created by
|
||||
; the compiler for each type declaration). Default is off.
|
||||
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
|
||||
; will match the behavior of synthesis tools.
|
||||
Explicit = 1
|
||||
|
||||
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
||||
; NoVital = 1
|
||||
|
||||
; Turn off VITAL compliance checking. Default is checking on.
|
||||
; NoVitalCheck = 1
|
||||
|
||||
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
||||
; IgnoreVitalErrors = 1
|
||||
|
||||
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
||||
; Show_VitalChecksWarnings = 0
|
||||
|
||||
; Keep silent about case statement static warnings.
|
||||
; Default is to give a warning.
|
||||
; NoCaseStaticError = 1
|
||||
|
||||
; Keep silent about warnings caused by aggregates that are not locally static.
|
||||
; Default is to give a warning.
|
||||
; NoOthersStaticError = 1
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "Loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on some limited synthesis rule compliance checking. Checks only:
|
||||
; -- signals used (read) by a process must be in the sensitivity list
|
||||
; CheckSynthesis = 1
|
||||
|
||||
; Activate optimizations on expressions that do not involve signals,
|
||||
; waits, or function/procedure/task invocations. Default is off.
|
||||
; ScalarOpts = 1
|
||||
|
||||
; Require the user to specify a configuration for all bindings,
|
||||
; and do not generate a compile time default binding for the
|
||||
; component. This will result in an elaboration error of
|
||||
; 'component not bound' if the user fails to do so. Avoids the rare
|
||||
; issue of a false dependency upon the unused default binding.
|
||||
; RequireConfigForAllDefaultBinding = 1
|
||||
|
||||
; Inhibit range checking on subscripts of arrays. Range checking on
|
||||
; scalars defined with subtypes is inhibited by default.
|
||||
; NoIndexCheck = 1
|
||||
|
||||
; Inhibit range checks on all (implicit and explicit) assignments to
|
||||
; scalar objects defined with subtypes.
|
||||
; NoRangeCheck = 1
|
||||
|
||||
[vlog]
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
||||
; Default is off.
|
||||
; Hazard = 1
|
||||
|
||||
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
||||
; insensitivity for module names. Default is no conversion.
|
||||
; UpCase = 1
|
||||
|
||||
; Turn on incremental compilation of modules. Default is off.
|
||||
; Incremental = 1
|
||||
|
||||
; Turns on lint-style checking.
|
||||
; Show_Lint = 1
|
||||
|
||||
[vsim]
|
||||
; Simulator resolution
|
||||
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
||||
Resolution = ps
|
||||
|
||||
; User time unit for run commands
|
||||
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
||||
; unit specified for Resolution. For example, if Resolution is 100ps,
|
||||
; then UserTimeUnit defaults to ps.
|
||||
; Should generally be set to default.
|
||||
UserTimeUnit = default
|
||||
|
||||
; Default run length
|
||||
RunLength = 100
|
||||
|
||||
; Maximum iterations that can be run without advancing simulation time
|
||||
IterationLimit = 5000
|
||||
|
||||
; Directive to license manager:
|
||||
; vhdl Immediately reserve a VHDL license
|
||||
; vlog Immediately reserve a Verilog license
|
||||
; plus Immediately reserve a VHDL and Verilog license
|
||||
; nomgc Do not look for Mentor Graphics Licenses
|
||||
; nomti Do not look for Model Technology Licenses
|
||||
; noqueue Do not wait in the license queue when a license isn't available
|
||||
; viewsim Try for viewer license but accept simulator license(s) instead
|
||||
; of queuing for viewer license
|
||||
; License = plus
|
||||
|
||||
; Stop the simulator after a VHDL/Verilog assertion message
|
||||
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
||||
BreakOnAssertion = 3
|
||||
|
||||
; Assertion Message Format
|
||||
; %S - Severity Level
|
||||
; %R - Report Message
|
||||
; %T - Time of assertion
|
||||
; %D - Delta
|
||||
; %I - Instance or Region pathname (if available)
|
||||
; %% - print '%' character
|
||||
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||
|
||||
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
|
||||
; AssertFile = assert.log
|
||||
|
||||
; Default radix for all windows and commands...
|
||||
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
||||
DefaultRadix = symbolic
|
||||
|
||||
; VSIM Startup command
|
||||
; Startup = do startup.do
|
||||
|
||||
; File for saving command transcript
|
||||
TranscriptFile = transcript
|
||||
|
||||
; File for saving command history
|
||||
; CommandHistory = cmdhist.log
|
||||
|
||||
; Specify whether paths in simulator commands should be described
|
||||
; in VHDL or Verilog format.
|
||||
; For VHDL, PathSeparator = /
|
||||
; For Verilog, PathSeparator = .
|
||||
; Must not be the same character as DatasetSeparator.
|
||||
PathSeparator = /
|
||||
|
||||
; Specify the dataset separator for fully rooted contexts.
|
||||
; The default is ':'. For example, sim:/top
|
||||
; Must not be the same character as PathSeparator.
|
||||
DatasetSeparator = :
|
||||
|
||||
; Disable VHDL assertion messages
|
||||
; IgnoreNote = 1
|
||||
; IgnoreWarning = 1
|
||||
; IgnoreError = 1
|
||||
; IgnoreFailure = 1
|
||||
|
||||
; Default force kind. May be freeze, drive, deposit, or default
|
||||
; or in other terms, fixed, wired, or charged.
|
||||
; A value of "default" will use the signal kind to determine the
|
||||
; force kind, drive for resolved signals, freeze for unresolved signals
|
||||
; DefaultForceKind = freeze
|
||||
|
||||
; If zero, open files when elaborated; otherwise, open files on
|
||||
; first read or write. Default is 0.
|
||||
; DelayFileOpen = 1
|
||||
|
||||
; Control VHDL files opened for write.
|
||||
; 0 = Buffered, 1 = Unbuffered
|
||||
UnbufferedOutput = 0
|
||||
|
||||
; Control the number of VHDL files open concurrently.
|
||||
; This number should always be less than the current ulimit
|
||||
; setting for max file descriptors.
|
||||
; 0 = unlimited
|
||||
ConcurrentFileLimit = 40
|
||||
|
||||
; Control the number of hierarchical regions displayed as
|
||||
; part of a signal name shown in the Wave window.
|
||||
; A value of zero tells VSIM to display the full name.
|
||||
; The default is 0.
|
||||
; WaveSignalNameWidth = 0
|
||||
|
||||
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
||||
; and std_logic_signed packages.
|
||||
; StdArithNoWarnings = 1
|
||||
|
||||
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
||||
; NumericStdNoWarnings = 1
|
||||
|
||||
; Control the format of the (VHDL) FOR generate statement label
|
||||
; for each iteration. Do not quote it.
|
||||
; The format string here must contain the conversion codes %s and %d,
|
||||
; in that order, and no other conversion codes. The %s represents
|
||||
; the generate_label; the %d represents the generate parameter value
|
||||
; at a particular generate iteration (this is the position number if
|
||||
; the generate parameter is of an enumeration type). Embedded whitespace
|
||||
; is allowed (but discouraged); leading and trailing whitespace is ignored.
|
||||
; Application of the format must result in a unique scope name over all
|
||||
; such names in the design so that name lookup can function properly.
|
||||
; GenerateFormat = %s__%d
|
||||
|
||||
; Specify whether checkpoint files should be compressed.
|
||||
; The default is 1 (compressed).
|
||||
; CheckpointCompressMode = 0
|
||||
|
||||
; List of dynamically loaded objects for Verilog PLI applications
|
||||
; Veriuser = veriuser.sl
|
||||
|
||||
; Specify default options for the restart command. Options can be one
|
||||
; or more of: -force -nobreakpoint -nolist -nolog -nowave
|
||||
; DefaultRestartOptions = -force
|
||||
|
||||
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
||||
; (> 500 megabyte memory footprint). Default is disabled.
|
||||
; Specify number of megabytes to lock.
|
||||
; LockedMemory = 1000
|
||||
|
||||
; Turn on (1) or off (0) WLF file compression.
|
||||
; The default is 1 (compress WLF file).
|
||||
; WLFCompress = 0
|
||||
|
||||
; Specify whether to save all design hierarchy (1) in the WLF file
|
||||
; or only regions containing logged signals (0).
|
||||
; The default is 0 (save only regions with logged signals).
|
||||
; WLFSaveAllRegions = 1
|
||||
|
||||
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
||||
; to the specified amount of simulation time. When the limit is exceeded
|
||||
; the earliest times get truncated from the file.
|
||||
; If both time and size limits are specified the most restrictive is used.
|
||||
; UserTimeUnits are used if time units are not specified.
|
||||
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
|
||||
; WLFTimeLimit = 0
|
||||
|
||||
; WLF file size limit. Limit WLF file size, as closely as possible,
|
||||
; to the specified number of megabytes. If both time and size limits
|
||||
; are specified then the most restrictive is used.
|
||||
; The default is 0 (no limit).
|
||||
; WLFSizeLimit = 1000
|
||||
|
||||
; Specify whether or not a WLF file should be deleted when the
|
||||
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
||||
; The default is 0 (do not delete WLF file when simulation ends).
|
||||
; WLFDeleteOnQuit = 1
|
||||
|
||||
; Automatic SDF compilation
|
||||
; Disables automatic compilation of SDF files in flows that support it.
|
||||
; Default is on, uncomment to turn off.
|
||||
; NoAutoSDFCompile = 1
|
||||
|
||||
[lmc]
|
||||
|
||||
[msg_system]
|
||||
; Change a message severity or suppress a message.
|
||||
; The format is: <msg directive> = <msg number>[,<msg number>...]
|
||||
; Examples:
|
||||
; note = 3009
|
||||
; warning = 3033
|
||||
; error = 3010,3016
|
||||
; fatal = 3016,3033
|
||||
; suppress = 3009,3016,3043
|
||||
; The command verror <msg number> can be used to get the complete
|
||||
; description of a message.
|
||||
|
||||
; Control transcripting of elaboration/runtime messages.
|
||||
; The default is to have messages appear in the transcript and
|
||||
; recorded in the wlf file (messages that are recorded in the
|
||||
; wlf file can be viewed in the MsgViewer). The other settings
|
||||
; are to send messages only to the transcript or only to the
|
||||
; wlf file. The valid values are
|
||||
; both {default}
|
||||
; tran {transcript only}
|
||||
; wlf {wlf file only}
|
||||
; msgmode = both
|
||||
@@ -0,0 +1,20 @@
|
||||
# simulation control script for counters testbench
|
||||
|
||||
# prepare working library
|
||||
file delete -force work
|
||||
vlib work
|
||||
vmap work work
|
||||
|
||||
# compile testbench
|
||||
vlog tb_n_bit_counter.v
|
||||
# compile design under test
|
||||
vlog ../src/n_bit_counter.v
|
||||
|
||||
# execute simulation
|
||||
vsim -c -t ps tb_n_bit_counter
|
||||
|
||||
# display simulation waveforms
|
||||
do wave_counter.tcl
|
||||
|
||||
# run simulation for 500ns
|
||||
run 500 ns
|
||||
@@ -0,0 +1,59 @@
|
||||
//n_bit_counter testbench
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module tb_n_bit_counter();
|
||||
|
||||
reg tb_clk;
|
||||
reg tb_rst;
|
||||
reg tb_en;
|
||||
|
||||
localparam TERMINAL_COUNT = 7 ;
|
||||
|
||||
wire [$clog2(TERMINAL_COUNT)-1 : 0] dut_q;
|
||||
wire dut_tc;
|
||||
|
||||
integer i = 0;
|
||||
|
||||
initial begin
|
||||
tb_clk = 1'b0;
|
||||
tb_rst = 1'b0;
|
||||
tb_en = 1'b0;
|
||||
end
|
||||
|
||||
always begin
|
||||
#10
|
||||
tb_clk = ~tb_clk;
|
||||
end
|
||||
|
||||
initial begin
|
||||
for (i = 0; i < 4; i = i+1) begin
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
|
||||
tb_rst = 1'b1;
|
||||
@(negedge tb_clk);
|
||||
tb_rst = 1'b0;
|
||||
@(negedge tb_clk);
|
||||
|
||||
for (i = 0; i < 4; i = i+1) begin
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
|
||||
tb_en = 1'b1;
|
||||
@(negedge tb_clk);
|
||||
|
||||
for (i = 0; i < 20; i = i+1) begin
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
end
|
||||
|
||||
n_bit_counter #(.terminalCount(TERMINAL_COUNT)) dut(
|
||||
.CLK(tb_clk),
|
||||
.CLK_EN(tb_en),
|
||||
.RST(tb_rst),
|
||||
.Q(dut_q),
|
||||
.TC(dut_tc)
|
||||
);
|
||||
|
||||
endmodule
|
||||
Binary file not shown.
@@ -0,0 +1,25 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /tb_n_bit_counter/tb_clk
|
||||
add wave -noupdate /tb_n_bit_counter/tb_rst
|
||||
add wave -noupdate /tb_n_bit_counter/tb_en
|
||||
add wave -noupdate -radix unsigned /tb_n_bit_counter/dut_q
|
||||
add wave -noupdate /tb_n_bit_counter/dut_tc
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {180405 ps} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 5000
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {98930 ps} {519794 ps}
|
||||
@@ -0,0 +1,43 @@
|
||||
m255
|
||||
K3
|
||||
13
|
||||
cModel Technology
|
||||
Z0 dC:\Users\Musab Erdem\Nextcloud\Dokumente\Studium\DHBW\Semester 4\Labor_EDS\Vorbereitung\4_Getraenkeautomat\aufwaertszaehler\sim
|
||||
vn_bit_counter
|
||||
!i10b 1
|
||||
!s100 7QPmi8gB:5XM`@G_^Y^UN2
|
||||
Iibfh1[JFT1R`eQZM`El:P1
|
||||
VoHO280_3HC[07hjL6?djI0
|
||||
Z1 dC:\Users\Musab Erdem\Nextcloud\Dokumente\Studium\DHBW\Semester 4\Labor_EDS\Vorbereitung\4_Getraenkeautomat\aufwaertszaehler\sim
|
||||
w1707967466
|
||||
8../src/n_bit_counter.v
|
||||
F../src/n_bit_counter.v
|
||||
L0 2
|
||||
Z2 OV;L;10.1d;51
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
!s108 1707967480.131000
|
||||
!s107 ../src/n_bit_counter.v|
|
||||
!s90 -reportprogress|300|../src/n_bit_counter.v|
|
||||
!s101 -O0
|
||||
o-O0
|
||||
vtb_n_bit_counter
|
||||
Z3 IPR4DYFS6VoIFF:Vk[BO813
|
||||
Z4 V?Z`X[2[ZbBLQ9:^Xg2d6O1
|
||||
R1
|
||||
Z5 w1707967478
|
||||
Z6 8tb_n_bit_counter.v
|
||||
Z7 Ftb_n_bit_counter.v
|
||||
L0 5
|
||||
R2
|
||||
r1
|
||||
31
|
||||
o-O0
|
||||
!i10b 1
|
||||
Z8 !s100 B6nQ1S6371jU9``Z@kBhX3
|
||||
!s85 0
|
||||
Z9 !s108 1707967480.065000
|
||||
Z10 !s107 tb_n_bit_counter.v|
|
||||
Z11 !s90 -reportprogress|300|tb_n_bit_counter.v|
|
||||
!s101 -O0
|
||||
@@ -0,0 +1,3 @@
|
||||
m255
|
||||
K3
|
||||
cModel Technology
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,16 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity n_bit_counter is
|
||||
generic(
|
||||
terminalCount : integer := 5
|
||||
);
|
||||
port(
|
||||
CLK : in vl_logic;
|
||||
CLK_EN : in vl_logic;
|
||||
RST : in vl_logic;
|
||||
Q : out vl_logic_vector;
|
||||
TC : out vl_logic
|
||||
);
|
||||
attribute mti_svvh_generic_type : integer;
|
||||
attribute mti_svvh_generic_type of terminalCount : constant is 1;
|
||||
end n_bit_counter;
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,4 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity tb_n_bit_counter is
|
||||
end tb_n_bit_counter;
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,32 @@
|
||||
`timescale 1ns/1ps
|
||||
module n_bit_counter
|
||||
# (parameter terminalCount = 5)
|
||||
(
|
||||
input CLK,
|
||||
input CLK_EN,
|
||||
input RST,
|
||||
output reg [$clog2(terminalCount)-1 : 0] Q,
|
||||
output reg TC
|
||||
);
|
||||
|
||||
always @(posedge CLK or posedge RST) begin
|
||||
if (RST) begin
|
||||
Q = 1'd0;
|
||||
end
|
||||
else if (CLK_EN) begin
|
||||
if(Q<terminalCount) begin
|
||||
Q = Q + 1'd1;
|
||||
if(Q==terminalCount) begin
|
||||
TC = 1'b1;
|
||||
end else begin
|
||||
TC = 1'b0;
|
||||
end
|
||||
end
|
||||
else if(Q==terminalCount) begin
|
||||
Q = 1'd0;
|
||||
TC = 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,324 @@
|
||||
; Copyright 1991-2009 Mentor Graphics Corporation
|
||||
;
|
||||
; All Rights Reserved.
|
||||
;
|
||||
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
|
||||
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
;
|
||||
|
||||
[Library]
|
||||
others = $MODEL_TECH/../modelsim.ini
|
||||
|
||||
; Altera Primitive libraries
|
||||
;
|
||||
; VHDL Section
|
||||
;
|
||||
;
|
||||
; Verilog Section
|
||||
;
|
||||
|
||||
work = work
|
||||
[vcom]
|
||||
; VHDL93 variable selects language version as the default.
|
||||
; Default is VHDL-2002.
|
||||
; Value of 0 or 1987 for VHDL-1987.
|
||||
; Value of 1 or 1993 for VHDL-1993.
|
||||
; Default or value of 2 or 2002 for VHDL-2002.
|
||||
; Default or value of 3 or 2008 for VHDL-2008.
|
||||
VHDL93 = 2002
|
||||
|
||||
; Show source line containing error. Default is off.
|
||||
; Show_source = 1
|
||||
|
||||
; Turn off unbound-component warnings. Default is on.
|
||||
; Show_Warning1 = 0
|
||||
|
||||
; Turn off process-without-a-wait-statement warnings. Default is on.
|
||||
; Show_Warning2 = 0
|
||||
|
||||
; Turn off null-range warnings. Default is on.
|
||||
; Show_Warning3 = 0
|
||||
|
||||
; Turn off no-space-in-time-literal warnings. Default is on.
|
||||
; Show_Warning4 = 0
|
||||
|
||||
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
||||
; Show_Warning5 = 0
|
||||
|
||||
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
||||
; Optimize_1164 = 0
|
||||
|
||||
; Turn on resolving of ambiguous function overloading in favor of the
|
||||
; "explicit" function declaration (not the one automatically created by
|
||||
; the compiler for each type declaration). Default is off.
|
||||
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
|
||||
; will match the behavior of synthesis tools.
|
||||
Explicit = 1
|
||||
|
||||
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
||||
; NoVital = 1
|
||||
|
||||
; Turn off VITAL compliance checking. Default is checking on.
|
||||
; NoVitalCheck = 1
|
||||
|
||||
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
||||
; IgnoreVitalErrors = 1
|
||||
|
||||
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
||||
; Show_VitalChecksWarnings = 0
|
||||
|
||||
; Keep silent about case statement static warnings.
|
||||
; Default is to give a warning.
|
||||
; NoCaseStaticError = 1
|
||||
|
||||
; Keep silent about warnings caused by aggregates that are not locally static.
|
||||
; Default is to give a warning.
|
||||
; NoOthersStaticError = 1
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "Loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on some limited synthesis rule compliance checking. Checks only:
|
||||
; -- signals used (read) by a process must be in the sensitivity list
|
||||
; CheckSynthesis = 1
|
||||
|
||||
; Activate optimizations on expressions that do not involve signals,
|
||||
; waits, or function/procedure/task invocations. Default is off.
|
||||
; ScalarOpts = 1
|
||||
|
||||
; Require the user to specify a configuration for all bindings,
|
||||
; and do not generate a compile time default binding for the
|
||||
; component. This will result in an elaboration error of
|
||||
; 'component not bound' if the user fails to do so. Avoids the rare
|
||||
; issue of a false dependency upon the unused default binding.
|
||||
; RequireConfigForAllDefaultBinding = 1
|
||||
|
||||
; Inhibit range checking on subscripts of arrays. Range checking on
|
||||
; scalars defined with subtypes is inhibited by default.
|
||||
; NoIndexCheck = 1
|
||||
|
||||
; Inhibit range checks on all (implicit and explicit) assignments to
|
||||
; scalar objects defined with subtypes.
|
||||
; NoRangeCheck = 1
|
||||
|
||||
[vlog]
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
||||
; Default is off.
|
||||
; Hazard = 1
|
||||
|
||||
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
||||
; insensitivity for module names. Default is no conversion.
|
||||
; UpCase = 1
|
||||
|
||||
; Turn on incremental compilation of modules. Default is off.
|
||||
; Incremental = 1
|
||||
|
||||
; Turns on lint-style checking.
|
||||
; Show_Lint = 1
|
||||
|
||||
[vsim]
|
||||
; Simulator resolution
|
||||
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
||||
Resolution = ps
|
||||
|
||||
; User time unit for run commands
|
||||
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
||||
; unit specified for Resolution. For example, if Resolution is 100ps,
|
||||
; then UserTimeUnit defaults to ps.
|
||||
; Should generally be set to default.
|
||||
UserTimeUnit = default
|
||||
|
||||
; Default run length
|
||||
RunLength = 100
|
||||
|
||||
; Maximum iterations that can be run without advancing simulation time
|
||||
IterationLimit = 5000
|
||||
|
||||
; Directive to license manager:
|
||||
; vhdl Immediately reserve a VHDL license
|
||||
; vlog Immediately reserve a Verilog license
|
||||
; plus Immediately reserve a VHDL and Verilog license
|
||||
; nomgc Do not look for Mentor Graphics Licenses
|
||||
; nomti Do not look for Model Technology Licenses
|
||||
; noqueue Do not wait in the license queue when a license isn't available
|
||||
; viewsim Try for viewer license but accept simulator license(s) instead
|
||||
; of queuing for viewer license
|
||||
; License = plus
|
||||
|
||||
; Stop the simulator after a VHDL/Verilog assertion message
|
||||
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
||||
BreakOnAssertion = 3
|
||||
|
||||
; Assertion Message Format
|
||||
; %S - Severity Level
|
||||
; %R - Report Message
|
||||
; %T - Time of assertion
|
||||
; %D - Delta
|
||||
; %I - Instance or Region pathname (if available)
|
||||
; %% - print '%' character
|
||||
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||
|
||||
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
|
||||
; AssertFile = assert.log
|
||||
|
||||
; Default radix for all windows and commands...
|
||||
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
||||
DefaultRadix = symbolic
|
||||
|
||||
; VSIM Startup command
|
||||
; Startup = do startup.do
|
||||
|
||||
; File for saving command transcript
|
||||
TranscriptFile = transcript
|
||||
|
||||
; File for saving command history
|
||||
; CommandHistory = cmdhist.log
|
||||
|
||||
; Specify whether paths in simulator commands should be described
|
||||
; in VHDL or Verilog format.
|
||||
; For VHDL, PathSeparator = /
|
||||
; For Verilog, PathSeparator = .
|
||||
; Must not be the same character as DatasetSeparator.
|
||||
PathSeparator = /
|
||||
|
||||
; Specify the dataset separator for fully rooted contexts.
|
||||
; The default is ':'. For example, sim:/top
|
||||
; Must not be the same character as PathSeparator.
|
||||
DatasetSeparator = :
|
||||
|
||||
; Disable VHDL assertion messages
|
||||
; IgnoreNote = 1
|
||||
; IgnoreWarning = 1
|
||||
; IgnoreError = 1
|
||||
; IgnoreFailure = 1
|
||||
|
||||
; Default force kind. May be freeze, drive, deposit, or default
|
||||
; or in other terms, fixed, wired, or charged.
|
||||
; A value of "default" will use the signal kind to determine the
|
||||
; force kind, drive for resolved signals, freeze for unresolved signals
|
||||
; DefaultForceKind = freeze
|
||||
|
||||
; If zero, open files when elaborated; otherwise, open files on
|
||||
; first read or write. Default is 0.
|
||||
; DelayFileOpen = 1
|
||||
|
||||
; Control VHDL files opened for write.
|
||||
; 0 = Buffered, 1 = Unbuffered
|
||||
UnbufferedOutput = 0
|
||||
|
||||
; Control the number of VHDL files open concurrently.
|
||||
; This number should always be less than the current ulimit
|
||||
; setting for max file descriptors.
|
||||
; 0 = unlimited
|
||||
ConcurrentFileLimit = 40
|
||||
|
||||
; Control the number of hierarchical regions displayed as
|
||||
; part of a signal name shown in the Wave window.
|
||||
; A value of zero tells VSIM to display the full name.
|
||||
; The default is 0.
|
||||
; WaveSignalNameWidth = 0
|
||||
|
||||
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
||||
; and std_logic_signed packages.
|
||||
; StdArithNoWarnings = 1
|
||||
|
||||
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
||||
; NumericStdNoWarnings = 1
|
||||
|
||||
; Control the format of the (VHDL) FOR generate statement label
|
||||
; for each iteration. Do not quote it.
|
||||
; The format string here must contain the conversion codes %s and %d,
|
||||
; in that order, and no other conversion codes. The %s represents
|
||||
; the generate_label; the %d represents the generate parameter value
|
||||
; at a particular generate iteration (this is the position number if
|
||||
; the generate parameter is of an enumeration type). Embedded whitespace
|
||||
; is allowed (but discouraged); leading and trailing whitespace is ignored.
|
||||
; Application of the format must result in a unique scope name over all
|
||||
; such names in the design so that name lookup can function properly.
|
||||
; GenerateFormat = %s__%d
|
||||
|
||||
; Specify whether checkpoint files should be compressed.
|
||||
; The default is 1 (compressed).
|
||||
; CheckpointCompressMode = 0
|
||||
|
||||
; List of dynamically loaded objects for Verilog PLI applications
|
||||
; Veriuser = veriuser.sl
|
||||
|
||||
; Specify default options for the restart command. Options can be one
|
||||
; or more of: -force -nobreakpoint -nolist -nolog -nowave
|
||||
; DefaultRestartOptions = -force
|
||||
|
||||
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
||||
; (> 500 megabyte memory footprint). Default is disabled.
|
||||
; Specify number of megabytes to lock.
|
||||
; LockedMemory = 1000
|
||||
|
||||
; Turn on (1) or off (0) WLF file compression.
|
||||
; The default is 1 (compress WLF file).
|
||||
; WLFCompress = 0
|
||||
|
||||
; Specify whether to save all design hierarchy (1) in the WLF file
|
||||
; or only regions containing logged signals (0).
|
||||
; The default is 0 (save only regions with logged signals).
|
||||
; WLFSaveAllRegions = 1
|
||||
|
||||
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
||||
; to the specified amount of simulation time. When the limit is exceeded
|
||||
; the earliest times get truncated from the file.
|
||||
; If both time and size limits are specified the most restrictive is used.
|
||||
; UserTimeUnits are used if time units are not specified.
|
||||
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
|
||||
; WLFTimeLimit = 0
|
||||
|
||||
; WLF file size limit. Limit WLF file size, as closely as possible,
|
||||
; to the specified number of megabytes. If both time and size limits
|
||||
; are specified then the most restrictive is used.
|
||||
; The default is 0 (no limit).
|
||||
; WLFSizeLimit = 1000
|
||||
|
||||
; Specify whether or not a WLF file should be deleted when the
|
||||
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
||||
; The default is 0 (do not delete WLF file when simulation ends).
|
||||
; WLFDeleteOnQuit = 1
|
||||
|
||||
; Automatic SDF compilation
|
||||
; Disables automatic compilation of SDF files in flows that support it.
|
||||
; Default is on, uncomment to turn off.
|
||||
; NoAutoSDFCompile = 1
|
||||
|
||||
[lmc]
|
||||
|
||||
[msg_system]
|
||||
; Change a message severity or suppress a message.
|
||||
; The format is: <msg directive> = <msg number>[,<msg number>...]
|
||||
; Examples:
|
||||
; note = 3009
|
||||
; warning = 3033
|
||||
; error = 3010,3016
|
||||
; fatal = 3016,3033
|
||||
; suppress = 3009,3016,3043
|
||||
; The command verror <msg number> can be used to get the complete
|
||||
; description of a message.
|
||||
|
||||
; Control transcripting of elaboration/runtime messages.
|
||||
; The default is to have messages appear in the transcript and
|
||||
; recorded in the wlf file (messages that are recorded in the
|
||||
; wlf file can be viewed in the MsgViewer). The other settings
|
||||
; are to send messages only to the transcript or only to the
|
||||
; wlf file. The valid values are
|
||||
; both {default}
|
||||
; tran {transcript only}
|
||||
; wlf {wlf file only}
|
||||
; msgmode = both
|
||||
@@ -0,0 +1,20 @@
|
||||
#cola simulation control script
|
||||
|
||||
file delete -force work
|
||||
vlib work
|
||||
vmap work work
|
||||
|
||||
#compile testbench
|
||||
vlog tb_cola.v
|
||||
|
||||
#compile dut
|
||||
vlog ../src/cola.v
|
||||
|
||||
#execute simulation
|
||||
vsim -c -t ps tb_cola
|
||||
|
||||
#display simulation waveforms
|
||||
do wave_cola.tcl
|
||||
|
||||
#run simulation for 1000ns
|
||||
run 1000 ns
|
||||
@@ -0,0 +1,20 @@
|
||||
#cola_rueckgeld simulation control script
|
||||
|
||||
file delete -force work
|
||||
vlib work
|
||||
vmap work work
|
||||
|
||||
#compile testbench
|
||||
vlog tb_cola_rueckgeld.v
|
||||
|
||||
#compile dut
|
||||
vlog ../src/cola_rueckgeld.v
|
||||
|
||||
#execute simulation
|
||||
vsim -c -t ps tb_cola_rueckgeld
|
||||
|
||||
#display simulation waveforms
|
||||
do wave_cola_rueckgeld.tcl
|
||||
|
||||
#run simulation for 1500ns
|
||||
run 1500 ns
|
||||
@@ -0,0 +1,97 @@
|
||||
//cola testbench
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module tb_cola();
|
||||
|
||||
reg tb_clk;
|
||||
reg tb_rst;
|
||||
reg tb_enable;
|
||||
reg dut_eineuro;
|
||||
reg dut_zweieuro;
|
||||
|
||||
wire [1:0] dut_ausgabe;
|
||||
wire [1:0] dut_zustand;
|
||||
|
||||
integer i = 0;
|
||||
|
||||
initial begin
|
||||
tb_clk = 1'b0;
|
||||
tb_rst = 1'b0;
|
||||
tb_enable = 1'b0;
|
||||
end
|
||||
|
||||
always begin
|
||||
#10;
|
||||
tb_clk = ~tb_clk;
|
||||
end
|
||||
|
||||
initial begin
|
||||
for (i=0; i<4; i=i+1) begin
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
|
||||
dut_eineuro = 1'b0;
|
||||
dut_zweieuro = 1'b0;
|
||||
|
||||
tb_rst = 1'b1;
|
||||
@(negedge tb_clk)
|
||||
|
||||
tb_rst = 1'b0;
|
||||
@(negedge tb_clk)
|
||||
|
||||
tb_enable = 1'b1;
|
||||
|
||||
for (i=0; i<8; i=i+1) begin
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
|
||||
//Fall 1: 3 mal 1 Euro
|
||||
for (i=0; i<3; i=i+1) begin
|
||||
dut_eineuro = 1'b1;
|
||||
@(negedge tb_clk);
|
||||
dut_eineuro = 1'b0;
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
|
||||
for (i=0; i<=4; i=i+1) begin
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
|
||||
tb_rst = 1'b1;
|
||||
@(negedge tb_clk)
|
||||
|
||||
tb_rst = 1'b0;
|
||||
@(negedge tb_clk)
|
||||
|
||||
for (i=0; i<4; i=i+1) begin
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
|
||||
//Fall 2: 2 Euro + 1 Euro
|
||||
dut_zweieuro = 1'b1;
|
||||
@(negedge tb_clk);
|
||||
dut_zweieuro = 1'b0;
|
||||
@(negedge tb_clk);
|
||||
|
||||
dut_eineuro = 1'b1;
|
||||
@(negedge tb_clk);
|
||||
dut_eineuro = 1'b0;
|
||||
@(negedge tb_clk);
|
||||
|
||||
for (i=0; i<4; i=i+1) begin
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
cola cola_dut(
|
||||
.CLK(tb_clk),
|
||||
.RST(tb_rst),
|
||||
.ENABLE(tb_enable),
|
||||
.EINEURO(dut_eineuro),
|
||||
.ZWEIEURO(dut_zweieuro),
|
||||
.AUSGABE(dut_ausgabe),
|
||||
.ZUSTAND(dut_zustand)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,119 @@
|
||||
//cola testbench
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module tb_cola_rueckgeld();
|
||||
|
||||
reg tb_clk;
|
||||
reg tb_rst;
|
||||
reg tb_enable;
|
||||
reg dut_eineuro;
|
||||
reg dut_zweieuro;
|
||||
|
||||
wire [2:0] dut_ausgabe;
|
||||
wire [2:0] dut_zustand;
|
||||
|
||||
integer i = 0;
|
||||
|
||||
initial begin
|
||||
tb_clk = 1'b0;
|
||||
tb_rst = 1'b0;
|
||||
tb_enable = 1'b0;
|
||||
end
|
||||
|
||||
always begin
|
||||
#10;
|
||||
tb_clk = ~tb_clk;
|
||||
end
|
||||
|
||||
initial begin
|
||||
for (i=0; i<4; i=i+1) begin
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
|
||||
dut_eineuro = 1'b0;
|
||||
dut_zweieuro = 1'b0;
|
||||
|
||||
tb_rst = 1'b1;
|
||||
@(negedge tb_clk)
|
||||
|
||||
tb_rst = 1'b0;
|
||||
@(negedge tb_clk)
|
||||
|
||||
tb_enable = 1'b1;
|
||||
|
||||
for (i=0; i<8; i=i+1) begin
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
|
||||
//Fall 1: 3 mal 1 Euro
|
||||
for (i=0; i<3; i=i+1) begin
|
||||
dut_eineuro = 1'b1;
|
||||
@(negedge tb_clk);
|
||||
dut_eineuro = 1'b0;
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
|
||||
for (i=0; i<=4; i=i+1) begin
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
|
||||
tb_rst = 1'b1;
|
||||
@(negedge tb_clk)
|
||||
|
||||
tb_rst = 1'b0;
|
||||
@(negedge tb_clk)
|
||||
|
||||
for (i=0; i<4; i=i+1) begin
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
|
||||
//Fall 2: 2 Euro + 1 Euro
|
||||
dut_zweieuro = 1'b1;
|
||||
@(negedge tb_clk);
|
||||
dut_zweieuro = 1'b0;
|
||||
@(negedge tb_clk);
|
||||
|
||||
dut_eineuro = 1'b1;
|
||||
@(negedge tb_clk);
|
||||
dut_eineuro = 1'b0;
|
||||
@(negedge tb_clk);
|
||||
|
||||
for (i=0; i<4; i=i+1) begin
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
|
||||
tb_rst = 1'b1;
|
||||
@(negedge tb_clk)
|
||||
|
||||
tb_rst = 1'b0;
|
||||
@(negedge tb_clk)
|
||||
|
||||
for (i=0; i<4; i=i+1) begin
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
|
||||
//Fall 2: 2 mal 2 Euro
|
||||
for (i=0; i<2; i=i+1) begin
|
||||
dut_zweieuro = 1'b1;
|
||||
@(negedge tb_clk);
|
||||
dut_zweieuro = 1'b0;
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
|
||||
for (i=0; i<4; i=i+1) begin
|
||||
@(negedge tb_clk);
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
cola_rueckgeld cola_rueckgeld_dut(
|
||||
.CLK(tb_clk),
|
||||
.RST(tb_rst),
|
||||
.ENABLE(tb_enable),
|
||||
.EINEURO(dut_eineuro),
|
||||
.ZWEIEURO(dut_zweieuro),
|
||||
.AUSGABE(dut_ausgabe),
|
||||
.ZUSTAND(dut_zustand)
|
||||
);
|
||||
|
||||
endmodule
|
||||
Binary file not shown.
@@ -0,0 +1,27 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /tb_cola/tb_clk
|
||||
add wave -noupdate /tb_cola/tb_rst
|
||||
add wave -noupdate /tb_cola/tb_enable
|
||||
add wave -noupdate /tb_cola/dut_eineuro
|
||||
add wave -noupdate /tb_cola/dut_zweieuro
|
||||
add wave -noupdate /tb_cola/dut_ausgabe
|
||||
add wave -noupdate /tb_cola/dut_zustand
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {999632 ps} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 5000
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {1683456 ps}
|
||||
@@ -0,0 +1,27 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /tb_cola_rueckgeld/tb_clk
|
||||
add wave -noupdate /tb_cola_rueckgeld/tb_rst
|
||||
add wave -noupdate /tb_cola_rueckgeld/tb_enable
|
||||
add wave -noupdate /tb_cola_rueckgeld/dut_eineuro
|
||||
add wave -noupdate /tb_cola_rueckgeld/dut_zweieuro
|
||||
add wave -noupdate /tb_cola_rueckgeld/dut_ausgabe
|
||||
add wave -noupdate /tb_cola_rueckgeld/dut_zustand
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {142446 ps} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 5000
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {1683456 ps}
|
||||
@@ -0,0 +1,43 @@
|
||||
m255
|
||||
K3
|
||||
13
|
||||
cModel Technology
|
||||
Z0 dC:\Users\Musab Erdem\Nextcloud\Dokumente\Studium\DHBW\Semester 4\Labor_EDS\Vorbereitung\4_Getraenkeautomat\automat\sim
|
||||
vcola_rueckgeld
|
||||
!i10b 1
|
||||
!s100 >cCL=5jZeGbGQV[:Y9UhL1
|
||||
IZSkAo]@S8F=dfS8>][d7;1
|
||||
VDIX1DJ_BmH4:dVjeX`zgV3
|
||||
Z1 dC:\Users\Musab Erdem\Nextcloud\Dokumente\Studium\DHBW\Semester 4\Labor_EDS\Vorbereitung\4_Getraenkeautomat\automat\sim
|
||||
w1707995519
|
||||
8../src/cola_rueckgeld.v
|
||||
F../src/cola_rueckgeld.v
|
||||
L0 3
|
||||
Z2 OV;L;10.1d;51
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
!s108 1708007253.591000
|
||||
!s107 ../src/cola_rueckgeld.v|
|
||||
!s90 -reportprogress|300|../src/cola_rueckgeld.v|
|
||||
!s101 -O0
|
||||
o-O0
|
||||
vtb_cola_rueckgeld
|
||||
Z3 I7h94;3XVPCf<ZAM>oT=d[0
|
||||
Z4 VC89UZ6Z[G9L1gE_^a]W7L1
|
||||
R1
|
||||
Z5 w1707964314
|
||||
Z6 8tb_cola_rueckgeld.v
|
||||
Z7 Ftb_cola_rueckgeld.v
|
||||
L0 4
|
||||
R2
|
||||
r1
|
||||
31
|
||||
o-O0
|
||||
!i10b 1
|
||||
Z8 !s100 ]0hOHefd:95SR?]SFdj>H1
|
||||
!s85 0
|
||||
Z9 !s108 1708007253.523000
|
||||
Z10 !s107 tb_cola_rueckgeld.v|
|
||||
Z11 !s90 -reportprogress|300|tb_cola_rueckgeld.v|
|
||||
!s101 -O0
|
||||
@@ -0,0 +1,3 @@
|
||||
m255
|
||||
K3
|
||||
cModel Technology
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,13 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity cola_rueckgeld is
|
||||
port(
|
||||
CLK : in vl_logic;
|
||||
RST : in vl_logic;
|
||||
ENABLE : in vl_logic;
|
||||
EINEURO : in vl_logic;
|
||||
ZWEIEURO : in vl_logic;
|
||||
AUSGABE : out vl_logic_vector(2 downto 0);
|
||||
ZUSTAND : out vl_logic_vector(2 downto 0)
|
||||
);
|
||||
end cola_rueckgeld;
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,4 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity tb_cola_rueckgeld is
|
||||
end tb_cola_rueckgeld;
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,65 @@
|
||||
//Cola Automat
|
||||
|
||||
module cola (CLK, RST, ENABLE, EINEURO, ZWEIEURO, AUSGABE, ZUSTAND);
|
||||
|
||||
//Ein-/Ausgaenge
|
||||
input CLK;
|
||||
input EINEURO, ZWEIEURO, ENABLE, RST;
|
||||
output reg [1:0] AUSGABE;
|
||||
output reg [1:0] ZUSTAND;
|
||||
|
||||
//Bitweise Zuordnung der Ausgabe
|
||||
localparam EIN_EUREO_EINWERFEN = 2'b01;
|
||||
localparam ZWEI_EURO_EINWERFEN = 2'b10;
|
||||
localparam DREI_EURO_EINWERFEN = 2'b11;
|
||||
localparam COLA_ENTNEHMEN = 2'b00;
|
||||
|
||||
//Immer bei CLK oder RST: 0 -> 1
|
||||
always @(posedge CLK or posedge RST)
|
||||
if(RST)
|
||||
begin
|
||||
AUSGABE <= DREI_EURO_EINWERFEN;
|
||||
ZUSTAND <= 2'b00;
|
||||
end
|
||||
else if (ENABLE)
|
||||
case(ZUSTAND)
|
||||
2'b00:
|
||||
begin
|
||||
AUSGABE <= DREI_EURO_EINWERFEN;
|
||||
if (EINEURO)
|
||||
ZUSTAND <= 2'b01;
|
||||
else if(ZWEIEURO)
|
||||
ZUSTAND <= 2'b10;
|
||||
else
|
||||
ZUSTAND <= 2'b00;
|
||||
end
|
||||
|
||||
2'b01:
|
||||
begin
|
||||
AUSGABE <= ZWEI_EURO_EINWERFEN;
|
||||
if(EINEURO)
|
||||
ZUSTAND <= 2'b10;
|
||||
else if(ZWEIEURO)
|
||||
ZUSTAND <= 2'b11;
|
||||
else
|
||||
ZUSTAND <= 2'b01;
|
||||
end
|
||||
|
||||
2'b10:
|
||||
begin
|
||||
AUSGABE <= EIN_EUREO_EINWERFEN;
|
||||
if(EINEURO)
|
||||
ZUSTAND <= 2'b11;
|
||||
else
|
||||
ZUSTAND <= 2'b10;
|
||||
end
|
||||
|
||||
2'b11:
|
||||
begin
|
||||
AUSGABE <= COLA_ENTNEHMEN;
|
||||
ZUSTAND <= 2'b00;
|
||||
end
|
||||
|
||||
endcase
|
||||
|
||||
endmodule //cola
|
||||
@@ -0,0 +1,74 @@
|
||||
//Cola Automat
|
||||
|
||||
module cola_rueckgeld (CLK, RST, ENABLE, EINEURO, ZWEIEURO, AUSGABE, ZUSTAND);
|
||||
|
||||
//Ein-/Ausgaenge
|
||||
input CLK;
|
||||
input EINEURO, ZWEIEURO, ENABLE, RST;
|
||||
output reg [2:0] AUSGABE;
|
||||
output reg [2:0] ZUSTAND;
|
||||
|
||||
//Bitweise Zuordnung der Ausgabe
|
||||
localparam EIN_EUREO_EINWERFEN = 3'b001;
|
||||
localparam ZWEI_EURO_EINWERFEN = 3'b010;
|
||||
localparam DREI_EURO_EINWERFEN = 3'b011;
|
||||
localparam COLA_ENTNEHMEN = 3'b000;
|
||||
localparam RUECKGELD = 3'b100;
|
||||
|
||||
//Immer bei CLK oder RST: 0 -> 1
|
||||
always @(posedge CLK or posedge RST)
|
||||
if(RST)
|
||||
begin
|
||||
AUSGABE <= DREI_EURO_EINWERFEN;
|
||||
ZUSTAND <= 3'b000;
|
||||
end
|
||||
else if (ENABLE)
|
||||
case(ZUSTAND)
|
||||
3'b000:
|
||||
begin
|
||||
AUSGABE <= DREI_EURO_EINWERFEN;
|
||||
if (EINEURO)
|
||||
ZUSTAND <= 3'b001;
|
||||
else if(ZWEIEURO)
|
||||
ZUSTAND <= 3'b010;
|
||||
else
|
||||
ZUSTAND <= 3'b000;
|
||||
end
|
||||
|
||||
3'b001:
|
||||
begin
|
||||
AUSGABE <= ZWEI_EURO_EINWERFEN;
|
||||
if(EINEURO)
|
||||
ZUSTAND <= 3'b010;
|
||||
else if(ZWEIEURO)
|
||||
ZUSTAND <= 3'b100;
|
||||
else
|
||||
ZUSTAND <= 3'b001;
|
||||
end
|
||||
|
||||
3'b010:
|
||||
begin
|
||||
AUSGABE <= EIN_EUREO_EINWERFEN;
|
||||
if(EINEURO)
|
||||
ZUSTAND <= 3'b100;
|
||||
else if(ZWEIEURO)
|
||||
ZUSTAND <= 3'b011;
|
||||
else
|
||||
ZUSTAND <= 3'b010;
|
||||
end
|
||||
|
||||
3'b011:
|
||||
begin
|
||||
AUSGABE <= RUECKGELD;
|
||||
ZUSTAND <= 3'b100;
|
||||
end
|
||||
|
||||
3'b100:
|
||||
begin
|
||||
AUSGABE <= COLA_ENTNEHMEN;
|
||||
ZUSTAND <= 3'b000;
|
||||
end
|
||||
|
||||
endcase
|
||||
|
||||
endmodule //cola
|
||||
@@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 13:26:59 February 15, 2024
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.0"
|
||||
DATE = "13:26:59 February 15, 2024"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "counters_leds"
|
||||
@@ -0,0 +1,486 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 13:26:59 February 15, 2024
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# counters_leds_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone II"
|
||||
set_global_assignment -name DEVICE EP2C35F672C6
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY counters_leds
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:26:59 FEBRUARY 15, 2024"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name VERILOG_FILE ../src/mod_n_counter_10bit.v
|
||||
set_global_assignment -name VERILOG_FILE ../src/d_ff.v
|
||||
set_global_assignment -name VERILOG_FILE ../src/counters_leds.v
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_location_assignment PIN_N25 -to SW[0]
|
||||
set_location_assignment PIN_N26 -to SW[1]
|
||||
set_location_assignment PIN_P25 -to SW[2]
|
||||
set_location_assignment PIN_AE14 -to SW[3]
|
||||
set_location_assignment PIN_AF14 -to SW[4]
|
||||
set_location_assignment PIN_AD13 -to SW[5]
|
||||
set_location_assignment PIN_AC13 -to SW[6]
|
||||
set_location_assignment PIN_C13 -to SW[7]
|
||||
set_location_assignment PIN_B13 -to SW[8]
|
||||
set_location_assignment PIN_A13 -to SW[9]
|
||||
set_location_assignment PIN_N1 -to SW[10]
|
||||
set_location_assignment PIN_P1 -to SW[11]
|
||||
set_location_assignment PIN_P2 -to SW[12]
|
||||
set_location_assignment PIN_T7 -to SW[13]
|
||||
set_location_assignment PIN_U3 -to SW[14]
|
||||
set_location_assignment PIN_U4 -to SW[15]
|
||||
set_location_assignment PIN_V1 -to SW[16]
|
||||
set_location_assignment PIN_V2 -to SW[17]
|
||||
set_location_assignment PIN_T6 -to DRAM_ADDR[0]
|
||||
set_location_assignment PIN_V4 -to DRAM_ADDR[1]
|
||||
set_location_assignment PIN_V3 -to DRAM_ADDR[2]
|
||||
set_location_assignment PIN_W2 -to DRAM_ADDR[3]
|
||||
set_location_assignment PIN_W1 -to DRAM_ADDR[4]
|
||||
set_location_assignment PIN_U6 -to DRAM_ADDR[5]
|
||||
set_location_assignment PIN_U7 -to DRAM_ADDR[6]
|
||||
set_location_assignment PIN_U5 -to DRAM_ADDR[7]
|
||||
set_location_assignment PIN_W4 -to DRAM_ADDR[8]
|
||||
set_location_assignment PIN_W3 -to DRAM_ADDR[9]
|
||||
set_location_assignment PIN_Y1 -to DRAM_ADDR[10]
|
||||
set_location_assignment PIN_V5 -to DRAM_ADDR[11]
|
||||
set_location_assignment PIN_AE2 -to DRAM_BA_0
|
||||
set_location_assignment PIN_AE3 -to DRAM_BA_1
|
||||
set_location_assignment PIN_AB3 -to DRAM_CAS_N
|
||||
set_location_assignment PIN_AA6 -to DRAM_CKE
|
||||
set_location_assignment PIN_AA7 -to DRAM_CLK
|
||||
set_location_assignment PIN_AC3 -to DRAM_CS_N
|
||||
set_location_assignment PIN_V6 -to DRAM_DQ[0]
|
||||
set_location_assignment PIN_AA2 -to DRAM_DQ[1]
|
||||
set_location_assignment PIN_AA1 -to DRAM_DQ[2]
|
||||
set_location_assignment PIN_Y3 -to DRAM_DQ[3]
|
||||
set_location_assignment PIN_Y4 -to DRAM_DQ[4]
|
||||
set_location_assignment PIN_R8 -to DRAM_DQ[5]
|
||||
set_location_assignment PIN_T8 -to DRAM_DQ[6]
|
||||
set_location_assignment PIN_V7 -to DRAM_DQ[7]
|
||||
set_location_assignment PIN_W6 -to DRAM_DQ[8]
|
||||
set_location_assignment PIN_AB2 -to DRAM_DQ[9]
|
||||
set_location_assignment PIN_AB1 -to DRAM_DQ[10]
|
||||
set_location_assignment PIN_AA4 -to DRAM_DQ[11]
|
||||
set_location_assignment PIN_AA3 -to DRAM_DQ[12]
|
||||
set_location_assignment PIN_AC2 -to DRAM_DQ[13]
|
||||
set_location_assignment PIN_AC1 -to DRAM_DQ[14]
|
||||
set_location_assignment PIN_AA5 -to DRAM_DQ[15]
|
||||
set_location_assignment PIN_AD2 -to DRAM_LDQM
|
||||
set_location_assignment PIN_Y5 -to DRAM_UDQM
|
||||
set_location_assignment PIN_AB4 -to DRAM_RAS_N
|
||||
set_location_assignment PIN_AD3 -to DRAM_WE_N
|
||||
set_location_assignment PIN_AC18 -to FL_ADDR[0]
|
||||
set_location_assignment PIN_AB18 -to FL_ADDR[1]
|
||||
set_location_assignment PIN_AE19 -to FL_ADDR[2]
|
||||
set_location_assignment PIN_AF19 -to FL_ADDR[3]
|
||||
set_location_assignment PIN_AE18 -to FL_ADDR[4]
|
||||
set_location_assignment PIN_AF18 -to FL_ADDR[5]
|
||||
set_location_assignment PIN_Y16 -to FL_ADDR[6]
|
||||
set_location_assignment PIN_AA16 -to FL_ADDR[7]
|
||||
set_location_assignment PIN_AD17 -to FL_ADDR[8]
|
||||
set_location_assignment PIN_AC17 -to FL_ADDR[9]
|
||||
set_location_assignment PIN_AE17 -to FL_ADDR[10]
|
||||
set_location_assignment PIN_AF17 -to FL_ADDR[11]
|
||||
set_location_assignment PIN_W16 -to FL_ADDR[12]
|
||||
set_location_assignment PIN_W15 -to FL_ADDR[13]
|
||||
set_location_assignment PIN_AC16 -to FL_ADDR[14]
|
||||
set_location_assignment PIN_AD16 -to FL_ADDR[15]
|
||||
set_location_assignment PIN_AE16 -to FL_ADDR[16]
|
||||
set_location_assignment PIN_AC15 -to FL_ADDR[17]
|
||||
set_location_assignment PIN_AB15 -to FL_ADDR[18]
|
||||
set_location_assignment PIN_AA15 -to FL_ADDR[19]
|
||||
set_location_assignment PIN_Y15 -to FL_ADDR[20]
|
||||
set_location_assignment PIN_Y14 -to FL_ADDR[21]
|
||||
set_location_assignment PIN_V17 -to FL_CE_N
|
||||
set_location_assignment PIN_W17 -to FL_OE_N
|
||||
set_location_assignment PIN_AD19 -to FL_DQ[0]
|
||||
set_location_assignment PIN_AC19 -to FL_DQ[1]
|
||||
set_location_assignment PIN_AF20 -to FL_DQ[2]
|
||||
set_location_assignment PIN_AE20 -to FL_DQ[3]
|
||||
set_location_assignment PIN_AB20 -to FL_DQ[4]
|
||||
set_location_assignment PIN_AC20 -to FL_DQ[5]
|
||||
set_location_assignment PIN_AF21 -to FL_DQ[6]
|
||||
set_location_assignment PIN_AE21 -to FL_DQ[7]
|
||||
set_location_assignment PIN_AA18 -to FL_RST_N
|
||||
set_location_assignment PIN_AA17 -to FL_WE_N
|
||||
set_location_assignment PIN_AF10 -to HEX0[0]
|
||||
set_location_assignment PIN_AB12 -to HEX0[1]
|
||||
set_location_assignment PIN_AC12 -to HEX0[2]
|
||||
set_location_assignment PIN_AD11 -to HEX0[3]
|
||||
set_location_assignment PIN_AE11 -to HEX0[4]
|
||||
set_location_assignment PIN_V14 -to HEX0[5]
|
||||
set_location_assignment PIN_V13 -to HEX0[6]
|
||||
set_location_assignment PIN_V20 -to HEX1[0]
|
||||
set_location_assignment PIN_V21 -to HEX1[1]
|
||||
set_location_assignment PIN_W21 -to HEX1[2]
|
||||
set_location_assignment PIN_Y22 -to HEX1[3]
|
||||
set_location_assignment PIN_AA24 -to HEX1[4]
|
||||
set_location_assignment PIN_AA23 -to HEX1[5]
|
||||
set_location_assignment PIN_AB24 -to HEX1[6]
|
||||
set_location_assignment PIN_AB23 -to HEX2[0]
|
||||
set_location_assignment PIN_V22 -to HEX2[1]
|
||||
set_location_assignment PIN_AC25 -to HEX2[2]
|
||||
set_location_assignment PIN_AC26 -to HEX2[3]
|
||||
set_location_assignment PIN_AB26 -to HEX2[4]
|
||||
set_location_assignment PIN_AB25 -to HEX2[5]
|
||||
set_location_assignment PIN_Y24 -to HEX2[6]
|
||||
set_location_assignment PIN_Y23 -to HEX3[0]
|
||||
set_location_assignment PIN_AA25 -to HEX3[1]
|
||||
set_location_assignment PIN_AA26 -to HEX3[2]
|
||||
set_location_assignment PIN_Y26 -to HEX3[3]
|
||||
set_location_assignment PIN_Y25 -to HEX3[4]
|
||||
set_location_assignment PIN_U22 -to HEX3[5]
|
||||
set_location_assignment PIN_W24 -to HEX3[6]
|
||||
set_location_assignment PIN_U9 -to HEX4[0]
|
||||
set_location_assignment PIN_U1 -to HEX4[1]
|
||||
set_location_assignment PIN_U2 -to HEX4[2]
|
||||
set_location_assignment PIN_T4 -to HEX4[3]
|
||||
set_location_assignment PIN_R7 -to HEX4[4]
|
||||
set_location_assignment PIN_R6 -to HEX4[5]
|
||||
set_location_assignment PIN_T3 -to HEX4[6]
|
||||
set_location_assignment PIN_T2 -to HEX5[0]
|
||||
set_location_assignment PIN_P6 -to HEX5[1]
|
||||
set_location_assignment PIN_P7 -to HEX5[2]
|
||||
set_location_assignment PIN_T9 -to HEX5[3]
|
||||
set_location_assignment PIN_R5 -to HEX5[4]
|
||||
set_location_assignment PIN_R4 -to HEX5[5]
|
||||
set_location_assignment PIN_R3 -to HEX5[6]
|
||||
set_location_assignment PIN_R2 -to HEX6[0]
|
||||
set_location_assignment PIN_P4 -to HEX6[1]
|
||||
set_location_assignment PIN_P3 -to HEX6[2]
|
||||
set_location_assignment PIN_M2 -to HEX6[3]
|
||||
set_location_assignment PIN_M3 -to HEX6[4]
|
||||
set_location_assignment PIN_M5 -to HEX6[5]
|
||||
set_location_assignment PIN_M4 -to HEX6[6]
|
||||
set_location_assignment PIN_L3 -to HEX7[0]
|
||||
set_location_assignment PIN_L2 -to HEX7[1]
|
||||
set_location_assignment PIN_L9 -to HEX7[2]
|
||||
set_location_assignment PIN_L6 -to HEX7[3]
|
||||
set_location_assignment PIN_L7 -to HEX7[4]
|
||||
set_location_assignment PIN_P9 -to HEX7[5]
|
||||
set_location_assignment PIN_N9 -to HEX7[6]
|
||||
set_location_assignment PIN_G26 -to KEY[0]
|
||||
set_location_assignment PIN_N23 -to KEY[1]
|
||||
set_location_assignment PIN_P23 -to KEY[2]
|
||||
set_location_assignment PIN_W26 -to KEY[3]
|
||||
set_location_assignment PIN_AE23 -to LEDR[0]
|
||||
set_location_assignment PIN_AF23 -to LEDR[1]
|
||||
set_location_assignment PIN_AB21 -to LEDR[2]
|
||||
set_location_assignment PIN_AC22 -to LEDR[3]
|
||||
set_location_assignment PIN_AD22 -to LEDR[4]
|
||||
set_location_assignment PIN_AD23 -to LEDR[5]
|
||||
set_location_assignment PIN_AD21 -to LEDR[6]
|
||||
set_location_assignment PIN_AC21 -to LEDR[7]
|
||||
set_location_assignment PIN_AA14 -to LEDR[8]
|
||||
set_location_assignment PIN_Y13 -to LEDR[9]
|
||||
set_location_assignment PIN_AA13 -to LEDR[10]
|
||||
set_location_assignment PIN_AC14 -to LEDR[11]
|
||||
set_location_assignment PIN_AD15 -to LEDR[12]
|
||||
set_location_assignment PIN_AE15 -to LEDR[13]
|
||||
set_location_assignment PIN_AF13 -to LEDR[14]
|
||||
set_location_assignment PIN_AE13 -to LEDR[15]
|
||||
set_location_assignment PIN_AE12 -to LEDR[16]
|
||||
set_location_assignment PIN_AD12 -to LEDR[17]
|
||||
set_location_assignment PIN_AE22 -to LEDG[0]
|
||||
set_location_assignment PIN_AF22 -to LEDG[1]
|
||||
set_location_assignment PIN_W19 -to LEDG[2]
|
||||
set_location_assignment PIN_V18 -to LEDG[3]
|
||||
set_location_assignment PIN_U18 -to LEDG[4]
|
||||
set_location_assignment PIN_U17 -to LEDG[5]
|
||||
set_location_assignment PIN_AA20 -to LEDG[6]
|
||||
set_location_assignment PIN_Y18 -to LEDG[7]
|
||||
set_location_assignment PIN_Y12 -to LEDG[8]
|
||||
set_location_assignment PIN_D13 -to CLOCK_27
|
||||
set_location_assignment PIN_N2 -to CLOCK_50
|
||||
set_location_assignment PIN_P26 -to EXT_CLOCK
|
||||
set_location_assignment PIN_D26 -to PS2_CLK
|
||||
set_location_assignment PIN_C24 -to PS2_DAT
|
||||
set_location_assignment PIN_C25 -to UART_RXD
|
||||
set_location_assignment PIN_B25 -to UART_TXD
|
||||
set_location_assignment PIN_K4 -to LCD_RW
|
||||
set_location_assignment PIN_K3 -to LCD_EN
|
||||
set_location_assignment PIN_K1 -to LCD_RS
|
||||
set_location_assignment PIN_J1 -to LCD_DATA[0]
|
||||
set_location_assignment PIN_J2 -to LCD_DATA[1]
|
||||
set_location_assignment PIN_H1 -to LCD_DATA[2]
|
||||
set_location_assignment PIN_H2 -to LCD_DATA[3]
|
||||
set_location_assignment PIN_J4 -to LCD_DATA[4]
|
||||
set_location_assignment PIN_J3 -to LCD_DATA[5]
|
||||
set_location_assignment PIN_H4 -to LCD_DATA[6]
|
||||
set_location_assignment PIN_H3 -to LCD_DATA[7]
|
||||
set_location_assignment PIN_L4 -to LCD_ON
|
||||
set_location_assignment PIN_K2 -to LCD_BLON
|
||||
set_location_assignment PIN_AE4 -to SRAM_ADDR[0]
|
||||
set_location_assignment PIN_AF4 -to SRAM_ADDR[1]
|
||||
set_location_assignment PIN_AC5 -to SRAM_ADDR[2]
|
||||
set_location_assignment PIN_AC6 -to SRAM_ADDR[3]
|
||||
set_location_assignment PIN_AD4 -to SRAM_ADDR[4]
|
||||
set_location_assignment PIN_AD5 -to SRAM_ADDR[5]
|
||||
set_location_assignment PIN_AE5 -to SRAM_ADDR[6]
|
||||
set_location_assignment PIN_AF5 -to SRAM_ADDR[7]
|
||||
set_location_assignment PIN_AD6 -to SRAM_ADDR[8]
|
||||
set_location_assignment PIN_AD7 -to SRAM_ADDR[9]
|
||||
set_location_assignment PIN_V10 -to SRAM_ADDR[10]
|
||||
set_location_assignment PIN_V9 -to SRAM_ADDR[11]
|
||||
set_location_assignment PIN_AC7 -to SRAM_ADDR[12]
|
||||
set_location_assignment PIN_W8 -to SRAM_ADDR[13]
|
||||
set_location_assignment PIN_W10 -to SRAM_ADDR[14]
|
||||
set_location_assignment PIN_Y10 -to SRAM_ADDR[15]
|
||||
set_location_assignment PIN_AB8 -to SRAM_ADDR[16]
|
||||
set_location_assignment PIN_AC8 -to SRAM_ADDR[17]
|
||||
set_location_assignment PIN_AD8 -to SRAM_DQ[0]
|
||||
set_location_assignment PIN_AE6 -to SRAM_DQ[1]
|
||||
set_location_assignment PIN_AF6 -to SRAM_DQ[2]
|
||||
set_location_assignment PIN_AA9 -to SRAM_DQ[3]
|
||||
set_location_assignment PIN_AA10 -to SRAM_DQ[4]
|
||||
set_location_assignment PIN_AB10 -to SRAM_DQ[5]
|
||||
set_location_assignment PIN_AA11 -to SRAM_DQ[6]
|
||||
set_location_assignment PIN_Y11 -to SRAM_DQ[7]
|
||||
set_location_assignment PIN_AE7 -to SRAM_DQ[8]
|
||||
set_location_assignment PIN_AF7 -to SRAM_DQ[9]
|
||||
set_location_assignment PIN_AE8 -to SRAM_DQ[10]
|
||||
set_location_assignment PIN_AF8 -to SRAM_DQ[11]
|
||||
set_location_assignment PIN_W11 -to SRAM_DQ[12]
|
||||
set_location_assignment PIN_W12 -to SRAM_DQ[13]
|
||||
set_location_assignment PIN_AC9 -to SRAM_DQ[14]
|
||||
set_location_assignment PIN_AC10 -to SRAM_DQ[15]
|
||||
set_location_assignment PIN_AE10 -to SRAM_WE_N
|
||||
set_location_assignment PIN_AD10 -to SRAM_OE_N
|
||||
set_location_assignment PIN_AF9 -to SRAM_UB_N
|
||||
set_location_assignment PIN_AE9 -to SRAM_LB_N
|
||||
set_location_assignment PIN_AC11 -to SRAM_CE_N
|
||||
set_location_assignment PIN_K7 -to OTG_ADDR[0]
|
||||
set_location_assignment PIN_F2 -to OTG_ADDR[1]
|
||||
set_location_assignment PIN_F1 -to OTG_CS_N
|
||||
set_location_assignment PIN_G2 -to OTG_RD_N
|
||||
set_location_assignment PIN_G1 -to OTG_WR_N
|
||||
set_location_assignment PIN_G5 -to OTG_RST_N
|
||||
set_location_assignment PIN_F4 -to OTG_DATA[0]
|
||||
set_location_assignment PIN_D2 -to OTG_DATA[1]
|
||||
set_location_assignment PIN_D1 -to OTG_DATA[2]
|
||||
set_location_assignment PIN_F7 -to OTG_DATA[3]
|
||||
set_location_assignment PIN_J5 -to OTG_DATA[4]
|
||||
set_location_assignment PIN_J8 -to OTG_DATA[5]
|
||||
set_location_assignment PIN_J7 -to OTG_DATA[6]
|
||||
set_location_assignment PIN_H6 -to OTG_DATA[7]
|
||||
set_location_assignment PIN_E2 -to OTG_DATA[8]
|
||||
set_location_assignment PIN_E1 -to OTG_DATA[9]
|
||||
set_location_assignment PIN_K6 -to OTG_DATA[10]
|
||||
set_location_assignment PIN_K5 -to OTG_DATA[11]
|
||||
set_location_assignment PIN_G4 -to OTG_DATA[12]
|
||||
set_location_assignment PIN_G3 -to OTG_DATA[13]
|
||||
set_location_assignment PIN_J6 -to OTG_DATA[14]
|
||||
set_location_assignment PIN_K8 -to OTG_DATA[15]
|
||||
set_location_assignment PIN_B3 -to OTG_INT0
|
||||
set_location_assignment PIN_C3 -to OTG_INT1
|
||||
set_location_assignment PIN_C2 -to OTG_DACK0_N
|
||||
set_location_assignment PIN_B2 -to OTG_DACK1_N
|
||||
set_location_assignment PIN_F6 -to OTG_DREQ0
|
||||
set_location_assignment PIN_E5 -to OTG_DREQ1
|
||||
set_location_assignment PIN_F3 -to OTG_FSPEED
|
||||
set_location_assignment PIN_G6 -to OTG_LSPEED
|
||||
set_location_assignment PIN_B14 -to TDI
|
||||
set_location_assignment PIN_A14 -to TCS
|
||||
set_location_assignment PIN_D14 -to TCK
|
||||
set_location_assignment PIN_F14 -to TDO
|
||||
set_location_assignment PIN_C4 -to TD_RESET
|
||||
set_location_assignment PIN_C8 -to VGA_R[0]
|
||||
set_location_assignment PIN_F10 -to VGA_R[1]
|
||||
set_location_assignment PIN_G10 -to VGA_R[2]
|
||||
set_location_assignment PIN_D9 -to VGA_R[3]
|
||||
set_location_assignment PIN_C9 -to VGA_R[4]
|
||||
set_location_assignment PIN_A8 -to VGA_R[5]
|
||||
set_location_assignment PIN_H11 -to VGA_R[6]
|
||||
set_location_assignment PIN_H12 -to VGA_R[7]
|
||||
set_location_assignment PIN_F11 -to VGA_R[8]
|
||||
set_location_assignment PIN_E10 -to VGA_R[9]
|
||||
set_location_assignment PIN_B9 -to VGA_G[0]
|
||||
set_location_assignment PIN_A9 -to VGA_G[1]
|
||||
set_location_assignment PIN_C10 -to VGA_G[2]
|
||||
set_location_assignment PIN_D10 -to VGA_G[3]
|
||||
set_location_assignment PIN_B10 -to VGA_G[4]
|
||||
set_location_assignment PIN_A10 -to VGA_G[5]
|
||||
set_location_assignment PIN_G11 -to VGA_G[6]
|
||||
set_location_assignment PIN_D11 -to VGA_G[7]
|
||||
set_location_assignment PIN_E12 -to VGA_G[8]
|
||||
set_location_assignment PIN_D12 -to VGA_G[9]
|
||||
set_location_assignment PIN_J13 -to VGA_B[0]
|
||||
set_location_assignment PIN_J14 -to VGA_B[1]
|
||||
set_location_assignment PIN_F12 -to VGA_B[2]
|
||||
set_location_assignment PIN_G12 -to VGA_B[3]
|
||||
set_location_assignment PIN_J10 -to VGA_B[4]
|
||||
set_location_assignment PIN_J11 -to VGA_B[5]
|
||||
set_location_assignment PIN_C11 -to VGA_B[6]
|
||||
set_location_assignment PIN_B11 -to VGA_B[7]
|
||||
set_location_assignment PIN_C12 -to VGA_B[8]
|
||||
set_location_assignment PIN_B12 -to VGA_B[9]
|
||||
set_location_assignment PIN_B8 -to VGA_CLK
|
||||
set_location_assignment PIN_D6 -to VGA_BLANK
|
||||
set_location_assignment PIN_A7 -to VGA_HS
|
||||
set_location_assignment PIN_D8 -to VGA_VS
|
||||
set_location_assignment PIN_B7 -to VGA_SYNC
|
||||
set_location_assignment PIN_A6 -to I2C_SCLK
|
||||
set_location_assignment PIN_B6 -to I2C_SDAT
|
||||
set_location_assignment PIN_J9 -to TD_DATA[0]
|
||||
set_location_assignment PIN_E8 -to TD_DATA[1]
|
||||
set_location_assignment PIN_H8 -to TD_DATA[2]
|
||||
set_location_assignment PIN_H10 -to TD_DATA[3]
|
||||
set_location_assignment PIN_G9 -to TD_DATA[4]
|
||||
set_location_assignment PIN_F9 -to TD_DATA[5]
|
||||
set_location_assignment PIN_D7 -to TD_DATA[6]
|
||||
set_location_assignment PIN_C7 -to TD_DATA[7]
|
||||
set_location_assignment PIN_D5 -to TD_HS
|
||||
set_location_assignment PIN_K9 -to TD_VS
|
||||
set_location_assignment PIN_C5 -to AUD_ADCLRCK
|
||||
set_location_assignment PIN_B5 -to AUD_ADCDAT
|
||||
set_location_assignment PIN_C6 -to AUD_DACLRCK
|
||||
set_location_assignment PIN_A4 -to AUD_DACDAT
|
||||
set_location_assignment PIN_A5 -to AUD_XCK
|
||||
set_location_assignment PIN_B4 -to AUD_BCLK
|
||||
set_location_assignment PIN_D17 -to ENET_DATA[0]
|
||||
set_location_assignment PIN_C17 -to ENET_DATA[1]
|
||||
set_location_assignment PIN_B18 -to ENET_DATA[2]
|
||||
set_location_assignment PIN_A18 -to ENET_DATA[3]
|
||||
set_location_assignment PIN_B17 -to ENET_DATA[4]
|
||||
set_location_assignment PIN_A17 -to ENET_DATA[5]
|
||||
set_location_assignment PIN_B16 -to ENET_DATA[6]
|
||||
set_location_assignment PIN_B15 -to ENET_DATA[7]
|
||||
set_location_assignment PIN_B20 -to ENET_DATA[8]
|
||||
set_location_assignment PIN_A20 -to ENET_DATA[9]
|
||||
set_location_assignment PIN_C19 -to ENET_DATA[10]
|
||||
set_location_assignment PIN_D19 -to ENET_DATA[11]
|
||||
set_location_assignment PIN_B19 -to ENET_DATA[12]
|
||||
set_location_assignment PIN_A19 -to ENET_DATA[13]
|
||||
set_location_assignment PIN_E18 -to ENET_DATA[14]
|
||||
set_location_assignment PIN_D18 -to ENET_DATA[15]
|
||||
set_location_assignment PIN_B24 -to ENET_CLK
|
||||
set_location_assignment PIN_A21 -to ENET_CMD
|
||||
set_location_assignment PIN_A23 -to ENET_CS_N
|
||||
set_location_assignment PIN_B21 -to ENET_INT
|
||||
set_location_assignment PIN_A22 -to ENET_RD_N
|
||||
set_location_assignment PIN_B22 -to ENET_WR_N
|
||||
set_location_assignment PIN_B23 -to ENET_RST_N
|
||||
set_location_assignment PIN_AE24 -to IRDA_TXD
|
||||
set_location_assignment PIN_AE25 -to IRDA_RXD
|
||||
set_location_assignment PIN_AD24 -to SD_DAT
|
||||
set_location_assignment PIN_AC23 -to SD_DAT3
|
||||
set_location_assignment PIN_Y21 -to SD_CMD
|
||||
set_location_assignment PIN_AD25 -to SD_CLK
|
||||
set_location_assignment PIN_D25 -to GPIO_0[0]
|
||||
set_location_assignment PIN_J22 -to GPIO_0[1]
|
||||
set_location_assignment PIN_E26 -to GPIO_0[2]
|
||||
set_location_assignment PIN_E25 -to GPIO_0[3]
|
||||
set_location_assignment PIN_F24 -to GPIO_0[4]
|
||||
set_location_assignment PIN_F23 -to GPIO_0[5]
|
||||
set_location_assignment PIN_J21 -to GPIO_0[6]
|
||||
set_location_assignment PIN_J20 -to GPIO_0[7]
|
||||
set_location_assignment PIN_F25 -to GPIO_0[8]
|
||||
set_location_assignment PIN_F26 -to GPIO_0[9]
|
||||
set_location_assignment PIN_N18 -to GPIO_0[10]
|
||||
set_location_assignment PIN_P18 -to GPIO_0[11]
|
||||
set_location_assignment PIN_G23 -to GPIO_0[12]
|
||||
set_location_assignment PIN_G24 -to GPIO_0[13]
|
||||
set_location_assignment PIN_K22 -to GPIO_0[14]
|
||||
set_location_assignment PIN_G25 -to GPIO_0[15]
|
||||
set_location_assignment PIN_H23 -to GPIO_0[16]
|
||||
set_location_assignment PIN_H24 -to GPIO_0[17]
|
||||
set_location_assignment PIN_J23 -to GPIO_0[18]
|
||||
set_location_assignment PIN_J24 -to GPIO_0[19]
|
||||
set_location_assignment PIN_H25 -to GPIO_0[20]
|
||||
set_location_assignment PIN_H26 -to GPIO_0[21]
|
||||
set_location_assignment PIN_H19 -to GPIO_0[22]
|
||||
set_location_assignment PIN_K18 -to GPIO_0[23]
|
||||
set_location_assignment PIN_K19 -to GPIO_0[24]
|
||||
set_location_assignment PIN_K21 -to GPIO_0[25]
|
||||
set_location_assignment PIN_K23 -to GPIO_0[26]
|
||||
set_location_assignment PIN_K24 -to GPIO_0[27]
|
||||
set_location_assignment PIN_L21 -to GPIO_0[28]
|
||||
set_location_assignment PIN_L20 -to GPIO_0[29]
|
||||
set_location_assignment PIN_J25 -to GPIO_0[30]
|
||||
set_location_assignment PIN_J26 -to GPIO_0[31]
|
||||
set_location_assignment PIN_L23 -to GPIO_0[32]
|
||||
set_location_assignment PIN_L24 -to GPIO_0[33]
|
||||
set_location_assignment PIN_L25 -to GPIO_0[34]
|
||||
set_location_assignment PIN_L19 -to GPIO_0[35]
|
||||
set_location_assignment PIN_K25 -to GPIO_1[0]
|
||||
set_location_assignment PIN_K26 -to GPIO_1[1]
|
||||
set_location_assignment PIN_M22 -to GPIO_1[2]
|
||||
set_location_assignment PIN_M23 -to GPIO_1[3]
|
||||
set_location_assignment PIN_M19 -to GPIO_1[4]
|
||||
set_location_assignment PIN_M20 -to GPIO_1[5]
|
||||
set_location_assignment PIN_N20 -to GPIO_1[6]
|
||||
set_location_assignment PIN_M21 -to GPIO_1[7]
|
||||
set_location_assignment PIN_M24 -to GPIO_1[8]
|
||||
set_location_assignment PIN_M25 -to GPIO_1[9]
|
||||
set_location_assignment PIN_N24 -to GPIO_1[10]
|
||||
set_location_assignment PIN_P24 -to GPIO_1[11]
|
||||
set_location_assignment PIN_R25 -to GPIO_1[12]
|
||||
set_location_assignment PIN_R24 -to GPIO_1[13]
|
||||
set_location_assignment PIN_R20 -to GPIO_1[14]
|
||||
set_location_assignment PIN_T22 -to GPIO_1[15]
|
||||
set_location_assignment PIN_T23 -to GPIO_1[16]
|
||||
set_location_assignment PIN_T24 -to GPIO_1[17]
|
||||
set_location_assignment PIN_T25 -to GPIO_1[18]
|
||||
set_location_assignment PIN_T18 -to GPIO_1[19]
|
||||
set_location_assignment PIN_T21 -to GPIO_1[20]
|
||||
set_location_assignment PIN_T20 -to GPIO_1[21]
|
||||
set_location_assignment PIN_U26 -to GPIO_1[22]
|
||||
set_location_assignment PIN_U25 -to GPIO_1[23]
|
||||
set_location_assignment PIN_U23 -to GPIO_1[24]
|
||||
set_location_assignment PIN_U24 -to GPIO_1[25]
|
||||
set_location_assignment PIN_R19 -to GPIO_1[26]
|
||||
set_location_assignment PIN_T19 -to GPIO_1[27]
|
||||
set_location_assignment PIN_U20 -to GPIO_1[28]
|
||||
set_location_assignment PIN_U21 -to GPIO_1[29]
|
||||
set_location_assignment PIN_V26 -to GPIO_1[30]
|
||||
set_location_assignment PIN_V25 -to GPIO_1[31]
|
||||
set_location_assignment PIN_V24 -to GPIO_1[32]
|
||||
set_location_assignment PIN_V23 -to GPIO_1[33]
|
||||
set_location_assignment PIN_W25 -to GPIO_1[34]
|
||||
set_location_assignment PIN_W23 -to GPIO_1[35]
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name CDF_FILE output_files/Chain4.cdf
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -0,0 +1,51 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 13:26:59 February 15, 2024
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# counters_leds_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone II"
|
||||
set_global_assignment -name DEVICE EP2C35F672C6
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY counters_leds
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:26:59 FEBRUARY 15, 2024"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name VERILOG_FILE ../src/mod_n_counter_10bit.v
|
||||
set_global_assignment -name VERILOG_FILE ../src/d_ff.v
|
||||
set_global_assignment -name VERILOG_FILE ../src/counters_leds.v
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
Binary file not shown.
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Binary file not shown.
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Binary file not shown.
@@ -0,0 +1,6 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1708005769472 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1708005769473 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 15 15:02:49 2024 " "Processing started: Thu Feb 15 15:02:49 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1708005769473 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1708005769473 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off counters_leds -c counters_leds " "Command: quartus_asm --read_settings_files=off --write_settings_files=off counters_leds -c counters_leds" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1708005769473 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1708005770518 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1708005770565 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4560 " "Peak virtual memory: 4560 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1708005771005 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 15 15:02:51 2024 " "Processing ended: Thu Feb 15 15:02:51 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1708005771005 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1708005771005 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1708005771005 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1708005771005 ""}
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0" ?>
|
||||
<LOG_ROOT>
|
||||
<PROJECT NAME="counters_leds">
|
||||
</PROJECT>
|
||||
</LOG_ROOT>
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1 @@
|
||||
v1
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,3 @@
|
||||
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Version_Index = 302049280
|
||||
Creation_Time = Thu Feb 15 15:02:22 2024
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1,211 @@
|
||||
|counters_leds
|
||||
CLOCK_50 => clk.IN7
|
||||
KEY[0] => rst.IN7
|
||||
LEDG[0] <= d_ff:d_ff_1.Q
|
||||
LEDG[1] <= d_ff:d_ff_2.Q
|
||||
LEDG[2] <= d_ff:d_ff_3.Q
|
||||
|
||||
|
||||
|counters_leds|mod_n_counter_10bit:div_1
|
||||
CLK => Q[0]~reg0.CLK
|
||||
CLK => Q[1]~reg0.CLK
|
||||
CLK => Q[2]~reg0.CLK
|
||||
CLK => Q[3]~reg0.CLK
|
||||
CLK => Q[4]~reg0.CLK
|
||||
CLK => Q[5]~reg0.CLK
|
||||
CLK => Q[6]~reg0.CLK
|
||||
CLK => Q[7]~reg0.CLK
|
||||
CLK => Q[8]~reg0.CLK
|
||||
CLK => Q[9]~reg0.CLK
|
||||
RST => Q[0]~reg0.ACLR
|
||||
RST => Q[1]~reg0.ACLR
|
||||
RST => Q[2]~reg0.ACLR
|
||||
RST => Q[3]~reg0.ACLR
|
||||
RST => Q[4]~reg0.ACLR
|
||||
RST => Q[5]~reg0.ACLR
|
||||
RST => Q[6]~reg0.ACLR
|
||||
RST => Q[7]~reg0.ACLR
|
||||
RST => Q[8]~reg0.ACLR
|
||||
RST => Q[9]~reg0.ACLR
|
||||
EN => Q[9]~reg0.ENA
|
||||
EN => Q[8]~reg0.ENA
|
||||
EN => Q[7]~reg0.ENA
|
||||
EN => Q[6]~reg0.ENA
|
||||
EN => Q[5]~reg0.ENA
|
||||
EN => Q[4]~reg0.ENA
|
||||
EN => Q[3]~reg0.ENA
|
||||
EN => Q[2]~reg0.ENA
|
||||
EN => Q[1]~reg0.ENA
|
||||
EN => Q[0]~reg0.ENA
|
||||
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
TC <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|mod_n_counter_10bit:div_2
|
||||
CLK => Q[0]~reg0.CLK
|
||||
CLK => Q[1]~reg0.CLK
|
||||
CLK => Q[2]~reg0.CLK
|
||||
CLK => Q[3]~reg0.CLK
|
||||
CLK => Q[4]~reg0.CLK
|
||||
CLK => Q[5]~reg0.CLK
|
||||
CLK => Q[6]~reg0.CLK
|
||||
CLK => Q[7]~reg0.CLK
|
||||
CLK => Q[8]~reg0.CLK
|
||||
CLK => Q[9]~reg0.CLK
|
||||
RST => Q[0]~reg0.ACLR
|
||||
RST => Q[1]~reg0.ACLR
|
||||
RST => Q[2]~reg0.ACLR
|
||||
RST => Q[3]~reg0.ACLR
|
||||
RST => Q[4]~reg0.ACLR
|
||||
RST => Q[5]~reg0.ACLR
|
||||
RST => Q[6]~reg0.ACLR
|
||||
RST => Q[7]~reg0.ACLR
|
||||
RST => Q[8]~reg0.ACLR
|
||||
RST => Q[9]~reg0.ACLR
|
||||
EN => Q[9]~reg0.ENA
|
||||
EN => Q[8]~reg0.ENA
|
||||
EN => Q[7]~reg0.ENA
|
||||
EN => Q[6]~reg0.ENA
|
||||
EN => Q[5]~reg0.ENA
|
||||
EN => Q[4]~reg0.ENA
|
||||
EN => Q[3]~reg0.ENA
|
||||
EN => Q[2]~reg0.ENA
|
||||
EN => Q[1]~reg0.ENA
|
||||
EN => Q[0]~reg0.ENA
|
||||
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
TC <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|mod_n_counter_10bit:div_3
|
||||
CLK => Q[0]~reg0.CLK
|
||||
CLK => Q[1]~reg0.CLK
|
||||
CLK => Q[2]~reg0.CLK
|
||||
CLK => Q[3]~reg0.CLK
|
||||
CLK => Q[4]~reg0.CLK
|
||||
CLK => Q[5]~reg0.CLK
|
||||
CLK => Q[6]~reg0.CLK
|
||||
CLK => Q[7]~reg0.CLK
|
||||
CLK => Q[8]~reg0.CLK
|
||||
CLK => Q[9]~reg0.CLK
|
||||
RST => Q[0]~reg0.ACLR
|
||||
RST => Q[1]~reg0.ACLR
|
||||
RST => Q[2]~reg0.ACLR
|
||||
RST => Q[3]~reg0.ACLR
|
||||
RST => Q[4]~reg0.ACLR
|
||||
RST => Q[5]~reg0.ACLR
|
||||
RST => Q[6]~reg0.ACLR
|
||||
RST => Q[7]~reg0.ACLR
|
||||
RST => Q[8]~reg0.ACLR
|
||||
RST => Q[9]~reg0.ACLR
|
||||
EN => Q[0]~reg0.ENA
|
||||
EN => Q[9]~reg0.ENA
|
||||
EN => Q[8]~reg0.ENA
|
||||
EN => Q[7]~reg0.ENA
|
||||
EN => Q[6]~reg0.ENA
|
||||
EN => Q[5]~reg0.ENA
|
||||
EN => Q[4]~reg0.ENA
|
||||
EN => Q[3]~reg0.ENA
|
||||
EN => Q[2]~reg0.ENA
|
||||
EN => Q[1]~reg0.ENA
|
||||
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
TC <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|mod_n_counter_10bit:div_4
|
||||
CLK => Q[0]~reg0.CLK
|
||||
CLK => Q[1]~reg0.CLK
|
||||
CLK => Q[2]~reg0.CLK
|
||||
CLK => Q[3]~reg0.CLK
|
||||
CLK => Q[4]~reg0.CLK
|
||||
CLK => Q[5]~reg0.CLK
|
||||
CLK => Q[6]~reg0.CLK
|
||||
CLK => Q[7]~reg0.CLK
|
||||
CLK => Q[8]~reg0.CLK
|
||||
CLK => Q[9]~reg0.CLK
|
||||
RST => Q[0]~reg0.ACLR
|
||||
RST => Q[1]~reg0.ACLR
|
||||
RST => Q[2]~reg0.ACLR
|
||||
RST => Q[3]~reg0.ACLR
|
||||
RST => Q[4]~reg0.ACLR
|
||||
RST => Q[5]~reg0.ACLR
|
||||
RST => Q[6]~reg0.ACLR
|
||||
RST => Q[7]~reg0.ACLR
|
||||
RST => Q[8]~reg0.ACLR
|
||||
RST => Q[9]~reg0.ACLR
|
||||
EN => Q[0]~reg0.ENA
|
||||
EN => Q[9]~reg0.ENA
|
||||
EN => Q[8]~reg0.ENA
|
||||
EN => Q[7]~reg0.ENA
|
||||
EN => Q[6]~reg0.ENA
|
||||
EN => Q[5]~reg0.ENA
|
||||
EN => Q[4]~reg0.ENA
|
||||
EN => Q[3]~reg0.ENA
|
||||
EN => Q[2]~reg0.ENA
|
||||
EN => Q[1]~reg0.ENA
|
||||
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
TC <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|d_ff:d_ff_1
|
||||
D => Q~reg0.DATAIN
|
||||
CLK => Q~reg0.CLK
|
||||
RST => Q~reg0.ACLR
|
||||
ENA => Q~reg0.ENA
|
||||
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Qn <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|d_ff:d_ff_2
|
||||
D => Q~reg0.DATAIN
|
||||
CLK => Q~reg0.CLK
|
||||
RST => Q~reg0.ACLR
|
||||
ENA => Q~reg0.ENA
|
||||
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Qn <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|counters_leds|d_ff:d_ff_3
|
||||
D => Q~reg0.DATAIN
|
||||
CLK => Q~reg0.CLK
|
||||
RST => Q~reg0.ACLR
|
||||
ENA => Q~reg0.ENA
|
||||
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
Qn <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,130 @@
|
||||
<TABLE>
|
||||
<TR bgcolor="#C0C0C0">
|
||||
<TH>Hierarchy</TH>
|
||||
<TH>Input</TH>
|
||||
<TH>Constant Input</TH>
|
||||
<TH>Unused Input</TH>
|
||||
<TH>Floating Input</TH>
|
||||
<TH>Output</TH>
|
||||
<TH>Constant Output</TH>
|
||||
<TH>Unused Output</TH>
|
||||
<TH>Floating Output</TH>
|
||||
<TH>Bidir</TH>
|
||||
<TH>Constant Bidir</TH>
|
||||
<TH>Unused Bidir</TH>
|
||||
<TH>Input only Bidir</TH>
|
||||
<TH>Output only Bidir</TH>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >d_ff_3</TD>
|
||||
<TD >4</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >d_ff_2</TD>
|
||||
<TD >4</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >d_ff_1</TD>
|
||||
<TD >4</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >div_4</TD>
|
||||
<TD >3</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >11</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >div_3</TD>
|
||||
<TD >3</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >11</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >div_2</TD>
|
||||
<TD >3</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >11</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >div_1</TD>
|
||||
<TD >3</TD>
|
||||
<TD >1</TD>
|
||||
<TD >0</TD>
|
||||
<TD >1</TD>
|
||||
<TD >11</TD>
|
||||
<TD >1</TD>
|
||||
<TD >1</TD>
|
||||
<TD >1</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
Binary file not shown.
@@ -0,0 +1,13 @@
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Legal Partition Candidates ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; d_ff_3 ; 4 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; d_ff_2 ; 4 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; d_ff_1 ; 4 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; div_4 ; 3 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; div_3 ; 3 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; div_2 ; 3 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; div_1 ; 3 ; 1 ; 0 ; 1 ; 11 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1 @@
|
||||
v1
|
||||
@@ -0,0 +1,18 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1708005761629 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1708005761630 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 15 15:02:41 2024 " "Processing started: Thu Feb 15 15:02:41 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1708005761630 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1708005761630 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off counters_leds -c counters_leds " "Command: quartus_map --read_settings_files=on --write_settings_files=off counters_leds -c counters_leds" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1708005761630 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1708005762025 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/mod_n_counter_10bit.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/mod_n_counter_10bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 mod_n_counter_10bit " "Found entity 1: mod_n_counter_10bit" { } { { "../src/mod_n_counter_10bit.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/mod_n_counter_10bit.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1708005762108 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1708005762108 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/d_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/d_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 d_ff " "Found entity 1: d_ff" { } { { "../src/d_ff.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/d_ff.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1708005762112 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1708005762112 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/counters_leds.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/musab erdem/nextcloud/dokumente/studium/dhbw/semester 4/labor_eds/uebungen/counters_leds/src/counters_leds.v" { { "Info" "ISGN_ENTITY_NAME" "1 counters_leds " "Found entity 1: counters_leds" { } { { "../src/counters_leds.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1708005762115 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1708005762115 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "en_ff_1 counters_leds.v(60) " "Verilog HDL Implicit Net warning at counters_leds.v(60): created implicit net for \"en_ff_1\"" { } { { "../src/counters_leds.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 60 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1708005762116 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "en_ff_2 counters_leds.v(61) " "Verilog HDL Implicit Net warning at counters_leds.v(61): created implicit net for \"en_ff_2\"" { } { { "../src/counters_leds.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 61 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1708005762116 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "en_ff_3 counters_leds.v(62) " "Verilog HDL Implicit Net warning at counters_leds.v(62): created implicit net for \"en_ff_3\"" { } { { "../src/counters_leds.v" "" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 62 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1708005762116 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "counters_leds " "Elaborating entity \"counters_leds\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1708005762154 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mod_n_counter_10bit mod_n_counter_10bit:div_1 " "Elaborating entity \"mod_n_counter_10bit\" for hierarchy \"mod_n_counter_10bit:div_1\"" { } { { "../src/counters_leds.v" "div_1" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 71 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1708005762188 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mod_n_counter_10bit mod_n_counter_10bit:div_3 " "Elaborating entity \"mod_n_counter_10bit\" for hierarchy \"mod_n_counter_10bit:div_3\"" { } { { "../src/counters_leds.v" "div_3" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 89 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1708005762194 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mod_n_counter_10bit mod_n_counter_10bit:div_4 " "Elaborating entity \"mod_n_counter_10bit\" for hierarchy \"mod_n_counter_10bit:div_4\"" { } { { "../src/counters_leds.v" "div_4" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 98 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1708005762198 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d_ff d_ff:d_ff_1 " "Elaborating entity \"d_ff\" for hierarchy \"d_ff:d_ff_1\"" { } { { "../src/counters_leds.v" "d_ff_1" { Text "C:/Users/Musab Erdem/Nextcloud/Dokumente/Studium/DHBW/Semester 4/Labor_EDS/Uebungen/counters_leds/src/counters_leds.v" 108 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1708005762201 ""}
|
||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1708005762907 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1708005762907 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "79 " "Implemented 79 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1708005762979 ""} { "Info" "ICUT_CUT_TM_OPINS" "3 " "Implemented 3 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1708005762979 ""} { "Info" "ICUT_CUT_TM_LCELLS" "74 " "Implemented 74 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1708005762979 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1708005762979 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4602 " "Peak virtual memory: 4602 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1708005763008 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 15 15:02:43 2024 " "Processing ended: Thu Feb 15 15:02:43 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1708005763008 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1708005763008 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1708005763008 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1708005763008 ""}
|
||||
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|
||||
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|
||||
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||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1708005776992 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 64-Bit " "Running Quartus II 64-Bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1708005776993 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 15 15:02:56 2024 " "Processing started: Thu Feb 15 15:02:56 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1708005776993 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1708005776993 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp counters_leds -c counters_leds --netlist_type=sgate " "Command: quartus_rpp counters_leds -c counters_leds --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1708005776993 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4428 " "Peak virtual memory: 4428 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1708005777034 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 15 15:02:57 2024 " "Processing ended: Thu Feb 15 15:02:57 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1708005777034 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1708005777034 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1708005777034 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1708005777034 ""}
|
||||
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Reference in New Issue
Block a user