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Lösung vom Drive kopiert und mit ChatGPT korrigieren lassen.

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This commit is contained in:
Musab Erdem
2024-02-29 16:33:57 +01:00
parent 673abf9c48
commit 8f9d0cd001
31 changed files with 1313 additions and 107 deletions
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47
labor_4/Aufgabe_6-4/src/sr_fsm.v
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@@ -3,13 +3,14 @@ module sr_fsm (
input reset,
input run,
input Sync,
input CYCLE_CTR,
input MISO,
output MOSI,
output [7:0] SSn,
output ENA
);
reg CYCLE_CTR; //= Anzahl der zu verschickende Daten
//Definition der States
parameter STATE_WAIT = 3'h0;
parameter STATE_INIT = 3'h1;
@@ -36,51 +37,65 @@ always @(STATE) begin
case (STATE)
STATE_WAIT:
if (run == 1'b1) begin
NEXT_STATE = STATE_INIT;
NEXT_STATE <= STATE_INIT;
end
else begin
NEXT_STATE = STATE_WAIT;
NEXT_STATE <= STATE_WAIT;
end
STATE_INIT:
if (Sync == 1'b1) begin
NEXT_STATE = STATE_SHIFT;
NEXT_STATE <= STATE_SHIFT;
end
else begin
NEXT_STATE = STATE_INIT;
NEXT_STATE <= STATE_INIT;
end
STATE_SHIFT:
CYCLE_CTR = CYCLE_CTR - 1; //CYCLE_CTR dekrementieren
//Schieberegister schieben??
if (Sync == 1'b1) begin
NEXT_STATE = STATE_LATCH;
NEXT_STATE <= STATE_LATCH;
end
else begin
NEXT_STATE = STATE_SHIFT;
NEXT_STATE <= STATE_SHIFT;
end
STATE_LATCH:
if (Sync == 1'b1 && CYCLE_CTR != 6'h0) begin
NEXT_STATE = STATE_SHIFT;
NEXT_STATE <= STATE_SHIFT;
end
else if (Sync == 1'b1 && CYCLE_CTR == 6'h0) begin
NEXT_STATE = STATE_CLEAR;
NEXT_STATE <= STATE_CLEAR;
end
else begin
NEXT_STATE = STATE_LATCH;
NEXT_STATE <= STATE_LATCH;
end
STATE_CLEAR:
if (Sync == 1'b1) begin
NEXT_STATE = STATE_WAIT;
NEXT_STATE <= STATE_WAIT;
end
else begin
NEXT_STATE = STATE_CLEAR;
NEXT_STATE <= STATE_CLEAR;
end
default: NEXT_STATE = STATE;
default: NEXT_STATE <= STATE_WAIT;
endcase
end
always @(STATE) begin
case (STATE)
STATE_WAIT:
STATE_INIT:
STATE_SHIFT:
CYCLE_CTR <= CYCLE_CTR - 1;
STATE_LATCH:
STATE_CLEAR:
default:
endcase
end

10
labor_4/Aufgabe_6-5/src/down_counter.v
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@@ -1,13 +1,13 @@
module down_counter #(
parameter CLOCK_DIVIDER = 5
)
module down_counter
(
input [7:0] CLK_DIVIDER;
input CLK,
input RESETn,
output reg [$clog2(CLOCK_DIVIDER)-1 : 0] Q,
output wire SYNC
);
output reg [$clog2(CLK_DIVIDER)-1 : 0] Q,
always @(posedge CLK or negedge RESETn) begin
if(~RESETn) begin
Q <= 1'd0;
@@ -17,7 +17,7 @@ always @(posedge CLK or negedge RESETn) begin
Q <= Q - 1'd1;
end
else if(Q == 1'd0) begin
Q <= CLOCK_DIVIDER;
Q <= CLK_DIVIDER;
end
end
end

325
labor_4/res/spi_master/sim/modelsim.ini Normal file
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@@ -0,0 +1,325 @@
; Copyright 1991-2009 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
[Library]
others = $MODEL_TECH/../modelsim.ini
; Altera Primitive libraries
;
; VHDL Section
;
;
; Verilog Section
;
work = work
spi_master = libs/spi_master
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
; Default or value of 3 or 2008 for VHDL-2008.
VHDL93 = 2002
; Show source line containing error. Default is off.
; Show_source = 1
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
; Turn on incremental compilation of modules. Default is off.
; Incremental = 1
; Turns on lint-style checking.
; Show_Lint = 1
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ps
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
; Default run length
RunLength = 100
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
; Directive to license manager:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license isn't available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license
; License = plus
; Stop the simulator after a VHDL/Verilog assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
; Assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
; AssertFile = assert.log
; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
; VSIM Startup command
; Startup = do startup.do
; File for saving command transcript
TranscriptFile = transcript
; File for saving command history
; CommandHistory = cmdhist.log
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type). Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave
; DefaultRestartOptions = -force
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
; Automatic SDF compilation
; Disables automatic compilation of SDF files in flows that support it.
; Default is on, uncomment to turn off.
; NoAutoSDFCompile = 1
[lmc]
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.
; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer). The other settings
; are to send messages only to the transcript or only to the
; wlf file. The valid values are
; both {default}
; tran {transcript only}
; wlf {wlf file only}
; msgmode = both

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labor_4/res/spi_master/sim/vsim.wlf Normal file
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24
labor_4/res/spi_master/sim/work/_info Normal file
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@@ -0,0 +1,24 @@
m255
K3
13
cModel Technology
Z0 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_4\res\spi_master\sim
vspi_master_tb
!i10b 1
!s100 WzH7KW]Xga2>VXnFzWQ6=2
I_fR75FE<PVdhQ0XH_iiNO3
VGVIa@54JI5PLOVOW3THe=0
Z1 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_4\res\spi_master\sim
w1709203964
8spi_master_tb.v
Fspi_master_tb.v
L0 3
OV;L;10.1d;51
r1
!s85 0
31
!s108 1709217349.397000
!s107 spi_master_tb.v|
!s90 -reportprogress|300|spi_master_tb.v|
!s101 -O0
o-O0

3
labor_4/res/spi_master/sim/work/_vmake Normal file
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@@ -0,0 +1,3 @@
m255
K3
cModel Technology

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labor_4/res/spi_master/sim/work/spi_master_tb/_primary.dat Normal file
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labor_4/res/spi_master/sim/work/spi_master_tb/_primary.dbs Normal file
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4
labor_4/res/spi_master/sim/work/spi_master_tb/_primary.vhd Normal file
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@@ -0,0 +1,4 @@
library verilog;
use verilog.vl_types.all;
entity spi_master_tb is
end spi_master_tb;

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labor_4/res/spi_master/sim/work/spi_master_tb/verilog.prw Normal file
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labor_4/res/spi_master/sim/work/spi_master_tb/verilog.psm Normal file
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203
labor_4/res/spi_master/src/spi_master.v Normal file
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@@ -0,0 +1,203 @@
// module spi_master
// Author: M. Walz
module spi_master(
//module inputs
// --- Definition of control inputs ---
input wire RESETn,
input wire CLK,
input wire [7:0] CLK_DIVIDER,
input wire [7:0] SLAVE_SELECT,
input wire [1:0] DATA_LENGTH,
input wire [1:0] MODE,
input wire MISO,
input wire [31:0] TX,
input wire RUN,
//module outputs
output reg [31:0] RX,
output SCLK,
output reg MOSI,
output reg [7:0] SSn,
output reg BUSY,
// module test outputs
output wire SYNC_TEST,
output wire [2:0] STATE_TEST,
output wire ENA_TEST
);
// --- Definition of internal varibles ---
reg [31:0]TX_SR, RX_SR;
reg [7:0] CLK_DIVIDER_REG;
reg [5:0] CYCLE_CTR;
reg [2:0] STATE;
reg ENA; // Enables operation of SCLK generator
reg T1, Q1; // Used for SLCK generation
wire CPOL, CPHA; // SPI Mode
wire SYNC; // SYNC Signal
// --- Implementation ---
// assignments of test signals
assign STATE_TEST = STATE;
assign ENA_TEST = ENA;
assign SYNC_TEST = SYNC;
// assignments MODE to control wires
assign CPOL = MODE [1];
assign CPHA = MODE [0];
// Clockdivider for generation of SYNC signal
always @ (posedge CLK or negedge RESETn) begin
end
//Definition der States
parameter STATE_WAIT = 3'h0;
parameter STATE_INIT = 3'h1;
parameter STATE_SHIFT = 3'h2;
parameter STATE_LATCH = 3'h3;
parameter STATE_CLEAR = 3'h4;
reg [2:0] NEXT_STATE;
// SPI-interface control logic
//Bei jedem Takt wird der State auf den nächsten State gesetzt, wenn ein Reset anliegt wird der State 'Wait' vorgegeben.
always @(posedge CLK) begin
if(reset) begin
STATE = STATE_WAIT;
end
else begin
STATE = NEXT_STATE;
end
end
always @ (posedge CLK or negedge RESETn) begin
if (~RESETn) begin
NEXT_STATE = STATE_WAIT;
TX_SR[31:0] = 32'h0;
RX_SR[31:0] <= 32'h0;
CYCLE_CTR[5:0] <= 5'h0;
SSn[7:0] <= 8'hFF;
ENA <= 1'b0;
MOSI <= 1'b0;
RX <= 32'b0;
BUSY <= 1'b0;
end
else case (STATE)
STATE_WAIT:
if (RUN == 1'b1) begin
NEXT_STATE <= STATE_INIT;
end
else begin
NEXT_STATE <= STATE_WAIT;
end
STATE_INIT:
if (SYNC == 1'b1) begin
NEXT_STATE <= STATE_SHIFT;
if(CPHA) begin
SSn [7:0] <= (~SLAVE_SELECT);
end
ENA <= 1'b1;
case (DATA_LENGTH[1:0]) begin
2'h0:
CYCLE_CTR[5:0] <= 6'h8;
TX_SR[31:24] <= TX[7:0];
end
endcase
end
else begin
NEXT_STATE <= STATE_INIT;
end
STATE_SHIFT:
if (SYNC == 1'b1) begin
NEXT_STATE <= STATE_LATCH;
end
else begin
NEXT_STATE <= STATE_SHIFT;
end
STATE_LATCH:
if (SYNC == 1'b1 && CYCLE_CTR != 6'h0) begin
NEXT_STATE <= STATE_SHIFT;
end
else if (SYNC == 1'b1 && CYCLE_CTR == 6'h0) begin
NEXT_STATE <= STATE_CLEAR;
end
else begin
NEXT_STATE <= STATE_LATCH;
end
STATE_CLEAR:
if (SYNC == 1'b1) begin
NEXT_STATE <= STATE_WAIT;
end
else begin
NEXT_STATE <= STATE_CLEAR;
end
default: NEXT_STATE <= STATE_WAIT;
// When transfering data from RX to RX_SR, ignore previously received bytes
case (DATA_LENGTH[1:0])
2'h0 : RX[31:0] <= {24'h0, RX_SR[ 7:0]}; // 1 Byte received
2'h1 : RX[31:0] <= {16'h0, RX_SR[15:0]}; // 2 Bytes received // 2 Bytes received
2'h2 : RX[31:0] <= {8'h0, RX_SR[23:0]}; // 2 Bytes received// 3 Bytes received
2'h3 : RX_SR[ 31:0]; // 4 Bytes received
endcase
endcase
end
always @(STATE) begin
case (STATE)
STATE_WAIT:
STATE_INIT:
STATE_SHIFT:
CYCLE_CTR <= CYCLE_CTR - 1;
STATE_LATCH:
STATE_CLEAR:
default:
endcase
end
// SPI SCLK generation
//SCLK_X Variablen
reg SCLK_0;
reg SCLK_1;
reg SCLK_2;
reg SCLK_3;
//D-FlipFlops
always @(posedge CLK or negedge RESETn) begin
if(~RESETn) begin
T1 <= 1'b0;
Q1 <= 1'b0;
end
else if (SYNC) begin
T1 <= ENA && ~T1;
Q1 <= T1;
end
end
//EXOR
always @(*) begin
SCLK_1 = CPHA && T1;
SCLK_0 = Q1 && ~CPHA;
SCLK_2 = SCLK_0 || SCLK_1;
SCLK_3 = SCLK_2 ^ CPOL;
SCLK = SCLK_3;
end
endmodule

86
labor_4/res/spi_master/src/spi_master_template.v
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@@ -1,86 +0,0 @@
// module spi_master
// Author: M. Walz
module spi_master(
//module inputs
// --- Definition of control inputs ---
input wire RESETn,
input wire CLK,
input wire [7:0] CLK_DIVIDER,
input wire [7:0] SLAVE_SELECT,
input wire [1:0] DATA_LENGTH,
input wire [1:0] MODE,
input wire MISO,
input wire [31:0] TX,
input wire RUN,
//module outputs
output reg [31:0] RX,
output SCLK,
output reg MOSI,
output reg [7:0] SSn,
output reg BUSY,
// module test outputs
output wire SYNC_TEST,
output wire [2:0] STATE_TEST,
output wire ENA_TEST
);
// --- Definition of internal varibles ---
reg [31:0]TX_SR, RX_SR;
reg [7:0] CLK_DIVIDER_REG;
reg [5:0] CYCLE_CTR;
reg [2:0] STATE;
reg ENA; // Enables operation of SCLK generator
reg T1, Q1; // Used for SLCK generation
wire CPOL, CPHA; // SPI Mode
wire SYNC; // SYNC Signal
// --- Implementation ---
// assignments of test signals
assign STATE_TEST = STATE;
assign ENA_TEST = ENA;
assign SYNC_TEST = SYNC;
// assignments MODE to control wires
assign CPOL = MODE [1];
assign CPHA = MODE [0];
// Clockdivider for generation of SYNC signal
always @ (posedge CLK or negedge RESETn) begin
end
// SPI-interface control logic
always @ (posedge CLK or negedge RESETn) begin
if (~RESETn) begin
end
else case (STATE)
// STATE: Wait
// STATE: Initialize
// STATE: Shift
// STATE: Latch
// STATE:
// When transfering data from RX to RX_SR, ignore previously received bytes
case (DATA_LENGTH[1:0])
2'h0 : RX[31:0] <= {24'h0, RX_SR[ 7:0]}; // 1 Byte received
2'h1 : // 2 Bytes received
2'h2 : // 3 Bytes received
2'h3 : // 4 Bytes received
endcase
endcase
end
// SPI SCLK generation
endmodule