Lösung vom Drive kopiert und mit ChatGPT korrigieren lassen.

labor_4_drive/sim/work/_info

@@ -0,0 +1,43 @@
+m255
+K3
+13
+cModel Technology
+Z0 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_4_drive\sim
+vspi_master
+!i10b 1
+!s100 eeKK<m[<0HH?9RRM<C5Ao0
+ILVV0Ed7VP83Raz[nlH`MA1
+VVAEF_7[2`JEP650]dTjC60
+Z1 dC:\Users\Musab Erdem\Desktop\labor_eds\labor_4_drive\sim
+w1709218513
+8../src/spi_master.v
+F../src/spi_master.v
+L0 1
+Z2 OV;L;10.1d;51
+r1
+!s85 0
+31
+Z3 !s108 1709218559.376000
+Z4 !s107 ../src/spi_master.v|spi_master_tb.v|
+Z5 !s90 -reportprogress|300|spi_master_tb.v|../src/spi_master.v|
+!s101 -O0
+o-O0
+vspi_master_tb
+!i10b 1
+!s100 WzH7KW]Xga2>VXnFzWQ6=2
+I_fR75FE<PVdhQ0XH_iiNO3
+VGVIa@54JI5PLOVOW3THe=0
+R1
+w1709217265
+8spi_master_tb.v
+Fspi_master_tb.v
+L0 3
+R2
+r1
+!s85 0
+31
+R3
+R4
+R5
+!s101 -O0
+o-O0

labor_4_drive/sim/work/_vmake

@@ -0,0 +1,3 @@
+m255
+K3
+cModel Technology

labor_4_drive/sim/work/spi_master/_primary.vhd

@@ -0,0 +1,23 @@
+library verilog;
+use verilog.vl_types.all;
+entity spi_master is
+    port(
+        RESETn          : in     vl_logic;
+        CLK             : in     vl_logic;
+        CLK_DIVIDER     : in     vl_logic_vector(7 downto 0);
+        SLAVE_SELECT    : in     vl_logic_vector(7 downto 0);
+        DATA_LENGTH     : in     vl_logic_vector(1 downto 0);
+        MODE            : in     vl_logic_vector(1 downto 0);
+        MISO            : in     vl_logic;
+        TX              : in     vl_logic_vector(31 downto 0);
+        RUN             : in     vl_logic;
+        RX              : out    vl_logic_vector(31 downto 0);
+        SCLK            : out    vl_logic;
+        MOSI            : out    vl_logic;
+        SSn             : out    vl_logic_vector(7 downto 0);
+        BUSY            : out    vl_logic;
+        SYNC_TEST       : out    vl_logic;
+        STATE_TEST      : out    vl_logic_vector(2 downto 0);
+        ENA_TEST        : out    vl_logic
+    );
+end spi_master;

labor_4_drive/sim/work/spi_master_tb/_primary.vhd

@@ -0,0 +1,4 @@
+library verilog;
+use verilog.vl_types.all;
+entity spi_master_tb is
+end spi_master_tb;